On-chip transaction processing system and method, electronic equipment and storage medium

Abstract

The invention discloses an on-chip transaction processing system and method, electronic equipment and a storage medium, and relates to the technical field of computers, an interconnection module is arranged between a plurality of initiating ends and a plurality of receiving ends, the interconnection module supports an AXI4 protocol, the interconnection module can receive to-be-processed transactions sent by the initiating ends, and the to-be-processed transactions are sent to the receiving ends; according to the AXI4 protocol transmission method, the AXI4 protocol is used for receiving the transmission control information of the transaction, screening out the to-be-transmitted transaction according to the transmission control information of the transaction, accurately sending the to-be-transmitted transaction to the corresponding receiving end, and accurately returning the read response data or the write response data to the source initiating end of the to-be-transmitted transaction by the receiving end, so that the AXI4 protocol is applied to application scenes of a plurality of initiating ends and a plurality of receiving ends. And disordered transmission of transactions is avoided.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to an on-chip transaction processing system, method, electronic device, and storage medium. Background Art

[0002] The Advanced Microcontroller Bus Architecture (AMBA for short) is an open and standard on-chip interconnect bus specification protocol cluster. The fourth-generation Advanced eXtensible Interface 4 (AXI4 for short) is an important part of AMBA, used to achieve high-speed communication between various functional modules on the chip.

[0003] In the related art, the AXI4 protocol is a point-to-point transmission protocol, that is, it can only implement information transmission between two modules. The transmission is initiated by the initiating end and responded by the receiving end. However, in actual applications, an on-chip system generally includes multiple initiating ends and multiple receiving ends. Therefore, how to apply the AXI4 protocol to scenarios with multiple initiating ends and multiple receiving ends has become a technical problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides an on-chip transaction processing system, method, electronic device, and storage medium to at least solve the problem of how to apply the AXI4 protocol to application scenarios with multiple initiating ends and multiple receiving ends in the related art.

[0005] This application provides an on-chip transaction processing system, including: multiple initiating ends, an interconnect module, and multiple receiving ends; The initiating end is used to send a transaction to be processed to the interconnect module; The interconnect module is used to receive transactions to be processed sent by multiple initiating ends, screen transactions to be transmitted from the transactions to be processed sent by multiple initiating ends according to the transmission control information of the transactions to be processed, and send the transactions to be transmitted to the corresponding receiving end; The receiving end is used to receive the transaction to be transmitted sent by the interconnect module and return read response data or write response data to the source initiating end of the transaction to be transmitted.

[0006] This application also provides an on-chip transaction processing method, which is applied to any of the above on-chip transaction processing systems. The method includes: Sending the transaction to be processed of the initiating end to the interconnect module; After controlling the interconnection module to receive the to-be-processed transactions sent by multiple said initiators, according to the transmission control information of the to-be-processed transactions, screen the to-be-transmitted transactions among the to-be-processed transactions sent by multiple said initiators, and send the to-be-transmitted transactions to the corresponding receivers; Based on the receiver receiving the to-be-transmitted transactions sent by the interconnection module, and returning read response data or write response data to the source initiator of the to-be-transmitted transactions.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above on-chip transaction processing methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any of the above on-chip transaction processing methods when executed by a processor.

[0009] This application also provides a computer program product, including a computer program, and the computer program implements the steps of any of the above on-chip transaction processing methods when executed by a processor.

[0010] Through this application, since an interconnection module is provided between multiple initiators and multiple receivers, the interconnection module supports the AXI4 protocol, the interconnection module can receive the to-be-processed transactions sent by multiple initiators, screen out the to-be-transmitted transactions according to the transmission control information of the transactions, and then accurately send them to the corresponding receivers, and the receivers accurately return the read response data or write response data to the source initiator of the to-be-transmitted transactions, so that the AXI4 protocol is applied to the application scenarios of multiple initiators and multiple receivers, and chaotic transmission of transactions is avoided. Description of the Drawings

[0011] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a schematic diagram of the interaction process of the on-chip transaction processing system provided by the embodiment of this application; Figure 2 It is a schematic diagram of the structure of the on-chip transaction processing system provided by the embodiment of this application; Figure 3 It is a schematic diagram of the data structure of the transaction entry provided by the embodiment of this application; Figure 4 It is a schematic diagram of the structure of a preset circular queue provided by the embodiment of this application; Figure 5 Another structural schematic diagram of the preset circular queue provided by the embodiment of the present application; Figure 6 Schematic diagram of the read transaction response process provided by the embodiment of the present application; Figure 7 Schematic diagram of the write transaction response process provided by the embodiment of the present application; Figure 8 Schematic diagram of the process of the on-chip transaction processing method provided by the embodiment of the present application; Figure 9 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0014] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0015] AXI4 is the full name of the fourth-generation Advanced eXtensible Interface, which is an important part of AMBA4 and is used to achieve high-speed communication between various on-chip modules. The AXI4 protocol is a point-to-point transmission protocol, that is, it can only realize the information transmission between two modules. The transmission is initiated by the master device (initiator) and responded by the slave device (receiver). To implement the AXI4 protocol transmission between multiple master devices and multiple slave devices, the embodiment of the present application proposes to use the AXI Interconnect module to realize the routing of AXI transmission transactions between devices.

[0016] The AXI4 protocol only describes the interface specifications for point-to-point connections. The topology, routing mechanism, arbitration logic, etc. within the AXI interconnect module need to be designed according to actual requirements. The AXI interconnect module should be transparent to the devices connected to it, which requires the AXI interconnect module to implement many features of AXI4, such as Outstanding, Out of order, read interleave, etc., on the basis of correctly routing transmission transactions. This requires designing corresponding read and write operation mechanisms to meet the normal AXI4 communication requirements between multiple master and multiple slave devices.

[0017] To enable those skilled in the art of this technology to better understand the solution of this application, the following further elaborates on this application in conjunction with the accompanying drawings and specific implementation manners.

[0018] The embodiment of this application provides a on-chip transaction processing system for applying the AXI4 protocol to application scenarios with multiple initiators and multiple receivers.

[0019] As Figure 1 shown, it is a schematic diagram of the interaction process of the on-chip transaction processing system provided by the embodiment of this application. The system includes: multiple initiators, an interconnect module, and multiple receivers; Among them, the initiator is used to send pending transactions to the interconnect module; the interconnect module is used to receive the pending transactions sent by multiple initiators, screen the pending transactions to be transmitted according to the transmission control information of the pending transactions, and send the pending transactions to be transmitted to the corresponding receivers; the receiver is used to receive the pending transactions sent by the interconnect module and return read response data or write response data to the source initiator of the pending transaction.

[0020] It should be noted that the pending transaction is the read and write request initiated by the initiator. According to the AXI4 protocol, the interconnect module supporting the AXI4 protocol provided by the embodiment of this application needs to support the following functions: 1) Support the Outstanding function of the read and write address interfaces; that is, it allows the initiator to initiate new read and write address requests when the current transaction has not been completed. The initiator can continuously issue multiple address requests without having to wait for responses one by one.

[0021] 2) Support the Out of Order function of the read and write return interfaces; that is, the order of the return data of the read and write operations can be different from the request order. In the high-parallel environment of the AXI4 bus, multiple read or write requests may occur simultaneously. Due to different processing speeds of each request, allowing the return order to be inconsistent with the request order can avoid resource waste caused by waiting for data to return in a specific order.

[0022] 3) Support read interleave function (read interleave); the initiator can interleave multiple read requests without waiting for the previous read request to complete. This function reduces the total delay of read operations and improves the efficiency of system data reading by processing multiple read operations in parallel.

[0023] 4) The read and write order of the same address remains unchanged; that is, no matter how other transactions are executed concurrently in the system, the read and write operations on the same address must be performed in the order in which they are initiated.

[0024] 5) For any master device, multiple transmission transactions with the same ID and the same read / write direction are returned sequentially; that is, for multiple pending transactions with the same transaction identifier (transaction ID) and read / write direction (the same write request or the same read request) issued by the same initiator, the order of the returned results is consistent with the initiation order.

[0025] 6) The ID codes of each master device are independent of each other, and there is no need to consider the same ID problem between master devices; that is, the transaction identification (transaction ID) code of each initiator is independent, and even if different initiators use the same transaction ID, the system can correctly distinguish and process their transactions.

[0026] 7) The slave responds to timeout, automatically ends the corresponding transmission transaction, and reports an error to the source master device; that is, if the receiving end does not respond to the initiator's request within the specified time, the system will automatically terminate the transmission transaction and send an error report to the initiator of the request to handle the abnormal situation in time.

[0027] Based on the above embodiments, Figure 2 A schematic diagram of the structure of an on-chip transaction processing system provided in an embodiment of the present application, as an implementable manner, in one embodiment, the interconnection module includes: An arbitration module, used for sending the pending transactions to the transmission control module in order according to the priority of each initiator and the attribute information of the pending transactions; The transmission control module is used to parse any pending transaction, obtain the transmission control information of the pending transaction, write the transmission control information into a preset circular queue as a transaction entry, and filter the pending transaction by traversing the preset circular queue.

[0028] The transmission control information of the transaction to be processed includes at least a source initiator identifier, a destination receiver identifier, an address to be accessed, a transaction identifier, a read / write identifier, and a transmission status identifier.

[0029] Specifically, since multiple initiators will simultaneously generate a large number of transactions to be processed, the urgency, importance, etc. of these transactions vary. The arbitration module comprehensively evaluates and sorts all the transactions to be processed based on the priorities preset by each initiator and the attribute information carried by the transaction to be transmitted (such as QoS signals, region signals, urgent signals, etc.). The arbitration module can determine the order of transaction processing and send the transactions to be processed to the transmission control module in this order, ensuring that important and urgent transactions can be processed first, improving the utilization efficiency of system resources and the overall performance of transaction processing.

[0030] Specifically, after receiving the transactions to be processed from the arbitration module, the transmission control module parses each transaction. Through parsing, the key information of the transaction, that is, the transmission control information, is extracted. These information include the source initiator identifier (the number of the initiator that sends the transaction to be processed), the destination receiver identifier (the destination receiver number), the address to be accessed, the transaction identifier, the read / write identifier, and the transmission status identifier. The transmission control module organizes these transmission control information into transaction entries and writes them into a preset circular queue. The circular queue, as an efficient data storage structure, facilitates the unified management and scheduling of transactions. The transmission control module traverses the preset circular queue and filters out the transactions suitable for transmission at the current moment from numerous transaction entries according to certain filtering rules, thereby realizing the control of transaction transmission and ensuring the orderly transmission of the transactions to be processed in a complex on-chip environment.

[0031] It should be noted that the transmission control module can determine the destination receiver corresponding to the transaction to be processed according to the address range represented by the address to be accessed, so as to avoid using sideband signals and extended IDs to determine the target receiver, reducing the requirement for the number of system interfaces and improving the adaptability to each receiver at the same time.

[0032] Among them, such as Figure 3As shown, it is a schematic diagram of the data structure of transaction entries provided by an embodiment of the present application. The transaction entries sequentially record the source initiator identifier, the destination receiver identifier, the address to be accessed, the transaction identifier, the read / write identifier, the transmission status identifier, the response counter, the response timer, the processing counter, the position of the previous transmission transaction, the position of the previous response transaction, and the transmission transaction parameters. Among them, the response counter records the number of times this transaction currently needs to respond, and the initial value is the same as the burst length. The burst length is the number of consecutive data units transmitted in a single transaction (Transaction). When transmitting the data of this transaction, when a valid signal (used to indicate the validity of the response data) appears at the corresponding data interface once, this value is decremented by 1; when it is decremented to 0, it means that the transmission of this transaction is completed. The response timer is used to record the response countdown of this transaction. When the transaction is in the transmission process, when it starts and when a valid signal appears at the corresponding data interface, this member is initialized to the allowed response time value; when this member becomes 0, a timeout is triggered, and the transmission of this transaction ends, and the transmission status identifier becomes the idle state. The processing counter is used to record the processing countdown of this transaction. When the transaction is stored in the circular queue, the countdown starts. If this transaction is still not processed (i.e., has not exited the "waiting for transmission to start" state) before the countdown ends, a timeout is triggered, and the transmission of this transaction ends, and the transmission status identifier becomes "timeout". The transmission transaction parameters include the transmission control parameters of the AXI address interface, such as size, burst length, burst type, QoS, region, protect, etc.

[0033] Specifically, in one embodiment, the transmission control module is specifically configured to: When obtaining the transmission control information of any pending transaction, according to the source initiator identifier represented by the transmission control information, locate the tail of the corresponding transmission transaction waiting sequence in the preset circular queue; Start from the tail of the transmission transaction waiting sequence and search clockwise for the queue maintenance pointer for a node with a transmission status identifier of idle, and use this node as the target insertion node; Insert the transmission control information as a transaction entry into the target insertion node, and modify the transmission status identifier of the target insertion node to waiting for transmission to start.

[0034] It should be noted that the preset circular queue is set in the transmission control module. The preset circular queue faces multiple initiators and is used to cache the transaction entries of all pending transactions initiated by the initiators. The preset circular queue includes the head and tail of the transmission transaction waiting sequence corresponding to each initiator.

[0035] Specifically, after obtaining the transmission control information of the transaction to be processed, the transmission control module first locates the tail of the transmission transaction waiting sequence corresponding to it in the preset circular queue according to the source initiator identifier therein. Each source initiator has its corresponding transaction waiting sequence in the circular queue, and the tail of the transmission transaction waiting sequence marks the position of the latest deposited transaction of the initiator. Starting from the tail of the transmission transaction waiting sequence, search clockwise towards the queue maintenance pointer (P T ). During the search, find the first node with a free transmission status flag. The free status indicates that the node is not currently in use and can be used to store new transaction entries. After finding the node, determine it as the target insertion node, and the transmission control module inserts the transmission control information of the transaction to be processed as a transaction entry into this node. At the same time, to indicate that the transaction has entered the queue and is waiting for transmission, modify the transmission status flag of the target insertion node from free to waiting for transmission start. This enables the system to clearly track the processing progress of the transaction and facilitates subsequent scheduling and management of the transaction.

[0036] Exemplarily, as Figure 4 shown, it is a schematic structural diagram of a preset circular queue provided by an embodiment of the present application. P Hn (n = 1, 2, …, N) represents the heads of the transmission transaction waiting sequences of initiators 1 to initiator N, and P Ln (n = 1, 2, …, N) represents the tails of the transmission transaction waiting sequences of initiators 1 to initiator N. N represents the number of initiators in the system. Taking the transmission control information of the transaction to be processed as an example, where its source initiator is initiator 1, first locate the tail of the transmission transaction waiting sequence P L1 in the preset circular queue, and then start from the tail of the transmission transaction waiting sequence P L1 and search clockwise towards the queue maintenance pointer P T to find the first node with a free transmission status flag, that is, if the transmission status flags of P 1 and P 2 in the preset circular queue are both free, then use P 1 as the target insertion node.

[0037] Among them, when the preset circular queue is initialized, P Hn (n = 1, 2, …, N) and the queue maintenance pointer P T are both recorded as non-normal values (such as 0).

[0038] Correspondingly, in one embodiment, the transmission control module is further configured to: Select any head of the transmission transaction waiting sequence in the preset circular queue as the destination node; Select a node in the preset circular queue whose transmission status flag meets the preset maintenance condition as the node to be maintained; Take the node to be maintained that is closest to the destination node in the counterclockwise direction as the target maintenance node, and move the queue maintenance pointer to the target maintenance node, so that the queue maintenance pointer moves to the boundary position between the nodes to be responded to and the idle nodes in the preset circular queue.

[0039] Among them, the target maintenance node is the earliest node to be responded to.

[0040] Specifically, the transmission control module selects any one of the transmission transaction waiting sequence headers (such as P H1 ) in the preset circular queue as the destination node. Screen the nodes to be maintained in the preset circular queue to determine the nodes whose transmission status identifiers meet the preset maintenance conditions as the nodes to be maintained. The preset maintenance conditions can be set in advance according to the requirements and logic of transaction processing. For example, when the transmission status of a node is "waiting for response", "initiator timeout waiting for response", or "receiver timeout waiting for response", etc., it is determined that the node meets the preset maintenance conditions. These states indicate that the transaction corresponding to the node is about to be completed or ended. After determining the nodes to be maintained, among these nodes to be maintained, find the node that is closest to the destination node in the counterclockwise direction and use it as the target maintenance node. Since the target maintenance node is the earliest node to be responded to, moving the queue maintenance pointer to this node position can make the queue maintenance pointer accurately located at the boundary position between the nodes to be responded to and the idle nodes in the preset circular queue, which helps the system to make more reasonable use of the storage space of the circular queue. When a new transaction arrives, the corresponding idle node can be quickly found for insertion, avoiding the time overhead of searching for idle nodes in the entire queue on a large scale.

[0041] Specifically, in one embodiment, for the determination of the previous transmission transaction position in the transaction entry, the transmission control module is further configured to: After inserting the transmission control information as a transaction entry into the target insertion node, start from the target insertion node and search counterclockwise in the direction of the queue maintenance pointer to find the first transmission previous node with the same destination receiver identifier; Take the position of the transmission previous node as the previous transmission transaction position and write it into the transaction entry of the target insertion node; In the case where no transmission previous node is found, record the previous transmission transaction position of the transaction entry of the target insertion node as an abnormal value.

[0042] Specifically, starting from the current storage position, search counterclockwise to P TWhen the position ends, search for the first node whose "destination receiver identifier" of the stored entry is the same as this entry and whose access addresses overlap. Use this node as the pre - transmission node, and use the position of the pre - transmission node as the pre - transmission transaction position, write it into the transaction entry of the target insertion node, and exit the search; if not found, the pre - transmission transaction position of this entry is recorded as an abnormal value (such as 0).

[0043] Among them, only after the pre - transmission transaction is completed can this transaction start transmission to meet the function of the AXI4 protocol that the read - write order for the same address remains unchanged.

[0044] Specifically, in one embodiment, for the determination of the pre - order response transaction position in the transaction entry, the transmission control module is further configured to: After inserting the transmission control information as a transaction entry into the target insertion node, start searching counter - clockwise from the target insertion node towards the queue maintenance pointer to find the first pre - order response node whose source initiator identifier, transaction identifier, and read - write identifier are all the same; Use the position of the pre - order response node as the pre - order response transaction position and write it into the transaction entry of the target insertion node; In the case where no response pre - order node is found, record the pre - order response transaction position of the transaction entry of the target insertion node as an abnormal value.

[0045] Specifically, starting from the current storage position, search counter - clockwise until the PT position ends, find the first node whose "source initiator identifier", "transaction identifier", and "read - write identifier" of the stored transaction entry are the same as this transaction entry, and use this node as the pre - order response node. Use the position of the pre - order response node as the pre - order response transaction position and write it into the transaction entry of the target insertion node, and exit the search; if not found, the "pre - order response transaction position" of this entry is recorded as an abnormal value (such as 0).

[0046] Among them, only after the pre - order response transaction is completed can this transaction make a response to meet the function of the AXI4 protocol that for any master device, multiple transmission transactions with the same ID and the same read - write direction are returned in order.

[0047] Specifically, in one embodiment, the transmission control module is further configured to: When inserting the transmission control information as a transaction entry into the target insertion node, preset a processing timer to load the timing limit and start counting down; When the countdown of the preset processing timer ends, if the transmission status identifier of the target insertion node is still waiting for transmission to start, trigger a timeout and modify the transmission status identifier of the target insertion node to the receiver timeout waiting for response.

[0048] Specifically, when the transmission control module inserts the transmission control information as a transaction entry into the target insertion node, a preset processing timer is synchronously started and loaded with a specific timing limit. This timing limit can be preset according to system performance requirements and the expected time for transaction processing, and is used to represent the maximum allowable waiting time for a transaction in the waiting transmission start state. After the preset processing timer starts counting down, the system continuously monitors its timing status. When the timer countdown ends, the system checks the transmission status flag of the target insertion node. If the transmission status flag of this node is still waiting for transmission to start at this time, it indicates that the transaction fails to enter the transmission stage within the specified time, that is, a timeout occurs. In response to this situation, the system triggers the timeout handling mechanism, modifies the transmission status flag of the target insertion node to receiving end timeout waiting for response to record the timeout situation of the transaction, and also provides a basis for subsequent system processing of this transaction.

[0049] Based on the above embodiments, as an implementable manner, in one embodiment, for a write transaction request, the transmission control module is specifically configured to: Generate an entry sending thread for each initiator; For any initiator, based on the entry sending thread, starting from the head of the transmission transaction waiting sequence corresponding to this initiator, search clockwise for the first node whose source initiator identifier is the initiator number, transmission status identifier is waiting for transmission to start, and read / write identifier is write, and use this node as the write node to be sent (the node corresponding to the transaction to be transmitted); When it is determined that the write transaction interface status of the destination receiver corresponding to the write node to be sent meets the preset write transaction reception condition, and the previous transmission transaction position of the transaction entry of the write node to be sent is a non-normal value, write the initiator number of the write node to be sent into the write data initiator queue and the write response initiator queue of the destination receiver, so that the destination receiver responds to the write transactions of each initiator in order; After writing the initiator number of any write node to be sent into the write data initiator queue and the write response initiator queue of the corresponding destination receiver, modify the transmission status identifier of this write node to be sent from waiting for transmission to start to in transmission.

[0050] It should be noted that the interconnection module sets three queues for each receiver in the system, which respectively store the Master device numbers (source initiator identifiers) when read and write transmission transactions arrive, denoted as the write data Master queue (write data initiator queue), the write response Master queue (write response initiator queue), and the read response Master queue (read response initiator queue).

[0051] Specifically, in one embodiment, the transmission control module is further configured to, when it is determined that the write transaction interface status of the destination receiver corresponding to the write node to be sent meets the preset write transaction receiving condition, but the previous transmission transaction position of the transaction entry of the write node to be sent is the previous transmission transaction position, after determining that the transmission status flag of the previous transmission node at the previous transmission transaction position is "in transmission", write the originator number of the write node to be sent into the write data originator queue and the write response originator queue of the destination receiver.

[0052] It should be noted that the transmission status flag includes "idle", "waiting for transmission start", "in transmission", "waiting for response", "originator response timeout", "receiver response timeout", "originator waiting for response timeout", and "receiver waiting for response timeout". Among them, the "idle" state represents that this transaction has been transmitted; the "waiting for transmission start" state represents that this transaction is queuing up waiting to start transmission; the "in transmission" state represents that the Master device is sending data to the Slave device through the data interface; the "waiting for response" state represents that the Master device is waiting for the Slave device to complete the response process through the response or data interface; the "originator response timeout" state represents that the Master device has a response timeout; the "receiver response timeout" state represents that the Slave device has a response timeout; the "originator waiting for response timeout" state represents that the Master device is waiting for the Slave device to respond or the data interface to complete the response process after the timeout; the "receiver waiting for response timeout" state represents that the Slave device is waiting for a forced response after the timeout.

[0053] Specifically, in one embodiment, for a read transaction request, the transmission control module is further configured to: For any originator, based on the entry sending thread, start from the head of the transmission transaction waiting sequence corresponding to the originator and search clockwise for the queue maintenance pointer to find the first node with the source originator identifier being the originator number, the transmission status flag being "waiting for transmission start", and the read / write flag being read, and use this node as the read node to be sent (the node corresponding to the transaction to be transmitted, that is, the transaction to be transmitted includes the write transaction to be sent and the read transaction to be sent); When it is determined that the read transaction interface status of the destination receiver corresponding to the read node to be sent meets the preset read transaction receiving condition, and the previous transmission transaction position of the transaction entry of the read node to be sent is a non-normal value, write the originator number of the read node to be sent into the read response originator queue of the destination receiver, so that the destination receiver responds to the read transactions of each originator in sequence; After reading the originator number of any read node to be sent into the read response originator queue of the corresponding destination receiver, modify the transmission status flag of the read node to be sent from "waiting for transmission start" to "waiting for response".

[0054] Specifically, an entry sending thread is generated for each Master device, and the transmission control module loops through the following process: Step 1, if P Hn (n = 1, 2, …, N) is not equal to P T , it indicates that there are transactions to be processed, and then proceed to Step 2; otherwise, there are no new pending transactions currently, and the thread will enter the waiting state until a new transaction is added to the queue; Step 2, search clockwise from P Hn to P T . For a write transaction request, find the first entry with the "source initiator ID" being n, the "transmission status ID" being "waiting for transmission start", and the "read / write ID" being "write". If the write address interface of the receiver corresponding to the "destination receiver ID" of this entry is in the ready state (the write transaction interface status of the destination receiver meets the preset write transaction reception conditions) and the "previous transmission transaction position" is a non-normal value (such as 0, indicating no previous transmission transaction or the previous transmission transaction has completed transmission), then this entry is selected. At the same time, for a read transaction request, find the first entry that meets the following conditions: the "source initiator ID" of this entry is n, the "transmission status ID" is "waiting for transmission start", the "read / write ID" is "read", the read address interface of the Slave device corresponding to the "destination receiver ID" is in the ready state, and the "previous transmission transaction position" is a non-normal value. Then this entry is selected. If no entry is selected, the corresponding read or write operation process is not performed.

[0055] Step 3, if among the entries found by multiple Master devices in Step 2, the "read / write IDs" are the same and the "destination receiver IDs" are the same, that is, the previous transmission transaction position of the transaction entry of the write node to be sent is the previous transmission transaction position (normal value), then select the entry closest to P T in the counterclockwise direction for sending, that is, preferentially send the previous transmission node that was first written into the circular queue, and the rest are not sent. The remaining entries have different "read / write IDs" or "destination receiver IDs" from any other entry, and these entries are sent in parallel with the above entries. For a write transaction, insert the "source initiator ID" into the tails of the write data initiator queue and the write response initiator queue of the receiver; for a read transaction, insert the "source initiator ID" into the tail of the read response initiator queue of the receiver to ensure that the write data / responses of the same receiver are processed in the order of the initiator requests, meeting the functional requirements of the AXI4 protocol (the read / write order for the same address remains unchanged).

[0056] Step 4: The entries sent in Step 3 are still in the preset circular queue. If its "read / write flag" is "write", then the "transmission status flag" is changed from "waiting for transmission start" to "transmission in progress"; if its "read / write flag" is "read", then the "transmission status flag" is changed from "waiting for transmission start" to "waiting for response".

[0057] Step 5: The response timer loads the timing limit and starts counting down to monitor the response time of the transaction and confirm whether the receiving end can give a response within the specified time.

[0058] Step 6: Update P Hn . Search clockwise from P Hn to P T to find the first entry with "source initiator ID" as n and "transmission status flag" as "waiting for transmission start", and update P Hn to the position of this entry in the circular queue. If not found, set P Hn to P T to indicate that there is no pending transaction with "source initiator ID" as n in the current circular queue.

[0059] Among them, in this process, if the entry in the circular queue with "transmission status flag" as "waiting for transmission start", its "processing timer" is always counting down. If the countdown ends, the "transmission status flag" is changed to "receiving end timeout waiting for response". Through the above steps, the transmission control module can effectively manage and schedule the read / write transactions between the initiator and the receiving end, handle transaction conflicts, ensure that transactions are processed in order and efficiently, and at the same time monitor the response time of transactions to improve the reliability and performance of the system.

[0060] It should be noted that the embodiments of the present application are based on the characteristics of the circular queue, and comprehensively determine the actual sending order of each transmission control information entry according to the position order of the transmission control information entries in the circular queue, the status of the previous transmission transaction, the status of the Master device interface, and the status of the Slave device interface, so as to realize parallel transmission of each device. At the same time, the "previous transmission transaction position" flag is used to control the entries with sending order requirements to be sent in the expected order to ensure the sending order. In addition, the sending waiting process is timed to avoid blocking caused by device non-response. At the same time, each Slave device records the Master information of the transmission transaction in order to analyze the source Master device during subsequent response processing.

[0061] Based on the above embodiments, as an implementable manner, in an embodiment, the initiator is used for: Starting from the queue maintenance pointer, search clockwise for the first node in the transmission transaction waiting sequence header corresponding to the initiating end, where the source initiating end identifier is the initiating end number, the transmission status identifier is "in transmission", and the read / write identifier is "write", and use this node as the write node for the data to be transmitted; When it is determined that both the destination receiving end corresponding to the write node for the data to be transmitted and the write data interface status of the initiating end meet the preset write data reception conditions, transmit the write data to the destination receiving end once; When it is determined that the destination receiving end corresponding to the write node for the data to be transmitted meets the preset write data reception conditions, but the write data interface status of the initiating end does not meet the preset write data reception conditions, or when both the destination receiving end and the write data interface status of the initiating end do not meet the preset write data reception conditions, end the transmission of the write data and modify the transmission status identifier of the write node for the data to be transmitted to "initiating end response timeout"; When it is determined that the write data interface status of the initiating end corresponding to the write node for the data to be transmitted meets the preset write data reception conditions, but the destination receiving end does not meet the preset write data reception conditions, forcefully transmit the write data to the destination receiving end once and modify the transmission status identifier of the write node for the data to be transmitted to "receiving end response timeout".

[0062] When the write node for the data to be transmitted meets the preset status modification conditions, if the transmission status identifier of the write node for the data to be transmitted is "in transmission", modify it to "waiting for response"; If the transmission status identifier of the write node for the data to be transmitted is "initiating end response timeout", modify it to "initiating end timeout waiting for response"; If the transmission status identifier of the write node for the data to be transmitted is "receiving end response timeout", modify it to "receiving end timeout waiting for response"; Among them, when the transmission status identifier of any node in the preset circular queue is "waiting for response", "initiating end timeout waiting for response", or "receiving end timeout waiting for response", it is determined that the node meets the preset maintenance conditions. For forcefully transmitting the write data to the destination receiving end once, under the AXI4 protocol, there are strict order requirements for transaction processing, and forced transmission can ensure that in abnormal situations, the transaction can still proceed in the direction of completion, avoiding long-term stagnation of the transaction and affecting subsequent transaction processing.

[0063] Specifically, each initiating end interface generates a thread and loops through the following process: Step 1, from P T to P Hn (n = 1, 2,..., N) (excluding P Hn ), search clockwise to find the first transaction entry where the "source initiating end identifier" is n, the "read / write identifier" is "write", and the "transmission status identifier" is "in transmission" or "receiving end response timeout", and use this node as the write node for the data to be transmitted.

[0064] If the "transmission status flag" of this entry is "in transmission", the write data interface of the current Master device is ready (the write data interface statuses of the initiating ends all meet the preset write data reception conditions), the write data interface of the destination receiving end is ready (the write data interface statuses of the destination receiving end all meet the preset write data reception conditions), and the write data Master queue head is n, then a write data transmission is performed. At the same time, the value in the "response counter" is decremented by 1, the "response timer" is loaded with the timing limit value, and the countdown restarts, entering step 2.

[0065] If the "transmission status flag" of this entry is "in transmission", the write data initiating end queue head of the Slave device corresponding to the "destination receiving end identifier" is n, but the data transmission is forcibly ended due to the write data interface of the Master device not being ready or both the write data interfaces of the Master and Slave devices not being ready resulting in a timeout. The "transmission status flag" is changed to "initiating end response timeout", and step 3 is entered.

[0066] If the "transmission status flag" of this entry is "in transmission", the write data interface of the current Master device is ready, the write data Master queue head of the Slave device corresponding to the "destination receiving end identifier" is n, but the data transmission is forcibly ended due to the write data interface of the Slave device not being ready resulting in a timeout. The "transmission status flag" is changed to "Slave timeout", a write data transmission is forcibly performed. At the same time, the value in the "response counter" is decremented by 1, the "response timer" is loaded with the timing limit value, and the countdown restarts, entering step 2.

[0067] If the "transmission status flag" of this entry is "receiving end response timeout", if the write data interface of the Master device is ready, a write data transmission is forcibly performed. At the same time, the value in the "response counter" is decremented by 1, the "response timer" is loaded with the timing limit value, and the countdown restarts, entering step 2; if the data transmission is forcibly ended due to the write data interface of the Master device not being ready resulting in a timeout, the "transmission status flag" is changed to "initiating end response timeout", and step 3 is entered.

[0068] Step 2, repeat step 1 until the write data end signal arrives or the value in the "response counter" is decremented to 0, that is, the write data transmission is completed, and step 3 is entered.

[0069] Step 3: If the "transmission status flag" of the current data transmission entry is "in transmission", change it to "awaiting response"; if the "transmission status flag" of the current data transmission entry is "initiator timeout response", change it to "initiator timeout awaiting response"; if the "transmission status flag" of the current data transmission entry is "receiver timeout response", change it to "initiator timeout awaiting response". Meanwhile, change the value in the "response counter" to 1; dequeue (delete) the head of the write data initiator queue of the initiator corresponding to the "destination receiver identifier", indicating that the record of this write transaction of the initiator in this queue has been processed.

[0070] Among them, through the above steps, during the write transaction data transmission process, the initiator flexibly determines the data transmission method according to the interface status of itself and the destination receiver, processes and records different timeout situations, and updates the status flag and relevant queues of the transaction node when the transmission is completed or the termination condition is reached, ensuring that the write transaction can proceed orderly and reliably.

[0071] It should be noted that in the embodiment of the present application, considering that the write data and the write address are in the same order in AXI4 and there is no write interleaving, the position of the entry being processed is determined by the write transmission transaction Master order recorded by the Slave device and the Master information of each write entry in the circular queue, and the data of the Master write data interface is received one by one. The communication with this Master write data interface is disconnected only after receiving all the write data of this transaction or when the Master times out, and the processing of the next write transmission transaction is started. If the Slave times out and responds, it can still support the Master to transmit the remaining write data; if the Master times out and responds, the write data process is forced to end. If a timeout occurs, the timeout information is recorded for subsequent processing of the write response information.

[0072] Based on the above embodiments, as an implementable manner, in an embodiment, the receiver is used for: When any read response data is obtained at the read data interface, find the first node whose destination receiver identifier is the receiver number and the transaction identifier matches the return identifier of the read response data in the clockwise direction starting from the queue maintenance pointer, and use this node as the read node to be returned; Judge whether the source initiator identifier of the read node to be returned is the first node to be matched in the read response initiator queue of the receiver; In the case where the source initiating end identifier of the read node to be returned is not the first node to be matched in the read response initiating end queue of the receiving end, modify the node to be matched to a non-matching node, define the read node to be returned as the node not to be searched in the next round, and return to execute the step of searching clockwise from the queue maintenance pointer to find the first node whose destination receiving end identifier is the receiving end number and the transaction identifier matches the return identifier of the read response data, and use this node as the read node to be returned to re-screen the read node to be returned; In the case where the source initiating end identifier of the read node to be returned is the first node to be matched in the read response initiating end queue of the receiving end, transmit the read response data to the source initiating end corresponding to the read node to be returned.

[0073] Specifically, generate a thread for each receiving end interface. Taking the mth receiving end as an example, the following process is executed in a loop: Step 1, after detecting that there is data incoming at the read data interface, obtain the transmission transaction ID (transaction identifier) from the read data interface, and then determine which initiating end to send the data to according to the Slave number (destination receiving end identifier), transmission transaction ID, read response initiating end queue, and the transmission control information entry in the circular queue. According to the above, the transmission transactions with the same read / write direction, the same Master device, and the same Slave device are sent sequentially in the clockwise direction along the circular queue. Then, according to the read response initiating end queue, the order of the read transmission control information entries sent to this receiving end can be deduced. Based on this, search according to the following steps: In the preset circular queue, start from P T Search clockwise for the first entry with a "transmission status identifier" of "waiting for response", a "destination receiving end identifier" of m, not marked "not to be searched", and a "source initiating end identifier" of the Master number of the first unmarked "not matching" in the read response initiating end queue (the first node to be matched). If the "transaction identifier (transaction ID)" of this entry is the same as the ID received by this interface, the Master device corresponding to the "source initiating end identifier" of this entry is the destination device of this read response; if not, mark this entry as "not to be searched" (define the read node to be returned as the node not to be searched in the next round), mark the head of the read response initiating end queue as "not matching" (modify the node to be matched to a non-matching node), and then perform this step of searching again until the correct destination Master device is found.

[0074] Step 2, wait for the read data interface of the corresponding destination Master device (the source initiating end corresponding to the read node to be returned) to receive. After completion, wait for the next time there is data incoming at the read data interface.

[0075] Among them, through the above steps, after receiving the read data, the receiving end can accurately return the read data to the corresponding initiating end by performing precise search and matching operations in the circular queue and combining the sequence information of the read response initiating end queue, ensuring the accuracy and orderliness of the read data transmission and avoiding the problems of data chaos and incorrect transmission.

[0076] Exemplarily, as Figure 5 shown, it is a schematic structural diagram of another preset circular queue provided by an embodiment of the present application. For the entries whose "transmission status identifier" of the stored entries from P9 to P14 is "waiting for response" or "receiving end timeout waiting for response", the content in the box next to it represents part of the entry content. M1 represents that the "Master number (source initiating end identifier)" is 1, S1 represents that the "Slave number (destination receiving end identifier)" is 1, ID1 represents that the "transaction ID" is ID1, and R represents that the "read / write identifier" is read. Then M2 - S1 - ID2 - R represents a read transaction sent by initiating end 1 to receiving end 1 with ID ID2. At this time, the read response initiating end queue of receiving end 1 is M1 - M1 - M1 - M2 - M2 - M1, and it can be known that the sending order of the read transactions is P9 - P10 - P12 - P11 - P14 - P13. If there is data at the read data interface of receiving end 1 and the ID is ID2, it can be known from the above search method that it is a transaction responding to P12; if there is data at the read data interface of receiving end 1 and the ID is ID1, it can be known from the above search method that it is a transaction responding to node P9.

[0077] Specifically, in one embodiment, the transmission control module is used for: When the transmission status identifier of any node in the preset circular queue is modified to waiting for response, taking this node as a read response node; When it is determined that the transmission status identifier of the response pre - node corresponding to the pre - response transaction position of the read response node is idle, starting to wait for the read data interface of the destination receiving end corresponding to the read response node to obtain the read response data; If within the preset waiting period, the read data interface of the destination receiving end obtains the read response data, then determining whether the read data interface of the source initiating end corresponding to the read response node meets the preset read data reception condition; When it is determined that the read data interface of the source initiating end corresponding to the read response node meets the preset read data reception condition, the source initiating end receives the read response data returned by the destination receiving end based on the read data interface.

[0078] Correspondingly, in one embodiment, the transmission control module is further configured to determine that the pending read transaction of the read response node has been completed and modify the transmission status flag of the read response node to idle when the target number of responses for the pending read transaction corresponding to the read response node is completed; if the read data interface of the destination receiving end does not obtain the read response data within the preset waiting period, the pending read transaction corresponding to the read response node is forcibly ended, and the transmission status flag of the read response node is modified to idle.

[0079] Specifically, as Figure 6 shown, it is a schematic diagram of the read transaction response process provided by the embodiment of the present application, and the specific process is as follows: Step 1: Wait for the entry "transmission status flag" to be changed to "waiting for response"; Step 2: If the "transmission status flag" of the entry corresponding to the entry "previous response transaction position" (denoted as entry A) is not "idle", that is, the previous response transaction is not completed, then wait, and the "response timer" pauses the countdown until the "transmission status flag" of entry A becomes "idle", that is, the previous response transaction is completed, and then jump to the next step; Step 3: Start waiting for the read data interface of the destination receiving end to obtain the read response data, and at the same time, the "response timer" starts timing. If there is data (read response data) at the read data interface of the destination receiving end before the "response timer" times out (within the preset waiting period), then go to Step 4; otherwise, go to Step 8.

[0080] Step 4: If the "transmission status flag" is "initiator timeout waiting for response", then force the initiator to immediately receive the data and go to Step 6; otherwise, the "response timer" loads the limit value and restarts timing, and go to Step 5; Step 5: Wait for the read interface of the initiator (read channel) to be ready to receive the data (the read data interface of the source initiator corresponding to the read response node meets the preset read data reception condition). If it is ready before the "response timer" times out, then go to Step 6 to enable the read data interface of the source initiator to receive the data; otherwise, force the initiator with the "transmission status flag" of "initiator timeout waiting for response" to immediately receive the data and go to Step 6.

[0081] Step 6: The read interface of the initiator receives the data, completes this transmission, and the entry "response counter" is decremented by 1.

[0082] Step 7: If the entry "response counter" is decremented to 0, then the transmission transaction of this entry is completed, and the "transmission status flag" is changed to "idle"; otherwise, jump back to Step 3 to receive the next read data.

[0083] Step 8: Forcefully end the transmission transaction of this entry, send a read error response to the corresponding initiator, and change the "transmission status flag" to "idle".

[0084] Among them, through the above steps, the transmission control module can reasonably handle the reception, timeout, etc. of read data according to factors such as the states of the initiator and the receiver and the response time during the read transaction response process, ensuring that the read transaction can be correctly completed according to the rule requirements and maintaining the orderliness and stability of transaction processing in the system.

[0085] It should be noted that after there is data at the read data interface of the receiver, the position of the entry being processed is determined according to the read ID information on the interface, the recorded order of the read transmission transaction initiators (read response initiator queue), and the initiator information of each read entry in the circular queue. The read data thread in the circular queue transfers the data on the read data interface of the receiver to the initiator device according to the obtained destination initiator device number and updates the content in the corresponding transmission control information entry. During this process, only after the entry corresponding to the "previous response transaction position" in the entry is completed, is this entry allowed to transmit data to handle the situation of the same initiator, different receivers, and the same transaction ID. After a read entry is completed, the data at the corresponding position is removed from the read response initiator queue. The design of this mechanism supports read Interleave and Out of Order, and at the same time ensures that the read messages of the same initiator device and the same ID are returned in order, and the read operations of different Master devices or different IDs do not affect each other. During this process, if there is a timeout response from the initiator or the receiver, the corresponding entry will be forced to end or forced to be transmitted, and an error will be reported at the same time to ensure that the overall communication process is not blocked after any device suddenly stops responding.

[0086] Specifically, in one embodiment, the transmission control module is used for: When the transmission status flag of any node in the preset circular queue is modified to waiting for response, initiator timeout waiting for response, or receiver timeout waiting for response, this node is used as a write response node; When it is determined that the transmission status flag of the response previous node corresponding to the previous response transaction position of the write response node is idle, start waiting for the write response interface of the destination receiver corresponding to the write response node to obtain the write response data; If within the preset waiting period, the write response interface of the destination receiver obtains the write response data, then determine whether the write response interface of the source initiator corresponding to the write response node meets the preset write response reception condition; When it is determined that the write response interface of the source initiator corresponding to the write response node meets the preset write response reception condition, the source initiator receives the write response data returned by the destination receiver based on the write response interface.

[0087] Correspondingly, in one embodiment, the transmission control module is further used for: When the write transaction corresponding to the write response node obtains the target number of write response data, it is determined that the write transaction to be processed by the write response node is completed, and the transmission status flag of the write response node is modified to idle; If the write response interface of the destination receiving end does not obtain the write response data within the preset waiting period, the write transaction to be processed corresponding to the write response node is forcibly ended, and the transmission status flag of the write response node is modified to idle.

[0088] Specifically, as Figure 7 shown, it is a schematic diagram of the write transaction response process provided by the embodiment of the present application, and the specific process is as follows: Step 1, wait for the entry "transmission status flag" to be changed to "waiting for response" or "initiator timeout waiting for response" or "receiver timeout waiting for response"; Step 2, if the "transmission status flag" of the entry corresponding to the entry "previous response transaction position" (denoted as entry A) is not "idle", then wait, and the "response timer" pauses the countdown until the "transmission status flag" of entry A becomes "idle", and then jump to the next step; Step 3, if the entry "transmission status flag" is "waiting for response" or "initiator timeout waiting for response", start waiting for the write response data, and at the same time the "response timer" starts timing. If there is data at the receiver write response interface before the "response timer" times out, then enter Step 4; otherwise, enter Step 7. If the entry "transmission status flag" is "receiver timeout waiting for response", enter Step 7.

[0089] Step 4, if the entry "transmission status flag" is "initiator timeout waiting for response", enter Step 7; otherwise, the "response timer" loads the limit value and restarts timing, and enter Step 5.

[0090] Step 5, wait for the initiator write response interface (write response channel) to be ready to receive data (the write response interface of the source initiator corresponding to the write response node meets the preset write response reception condition). If it is ready before the "response timer" times out, then enter Step 6 to enable the initiator write response interface to receive data; otherwise, enter Step 7.

[0091] Step 6, the initiator write response interface receives the data, the entry "response counter" is set to 0, the transmission transaction of this entry is completed, and the "transmission status flag" is changed to "idle".

[0092] Step 7, forcibly end the transmission transaction of this entry, and send a write response error to the corresponding source initiator, and the "transmission status flag" is changed to "idle".

[0093] Among them, through the above steps, the transmission control module can reasonably handle the reception, timeout, etc. of the write response data according to factors such as the states of the initiator and the receiver and the response time during the write transaction response process, ensure that the read transaction can be correctly completed according to the rule requirements, and maintain the orderliness and stability of transaction processing in the system.

[0094] It should be noted that after there is data in the receiver write response interface, the position of the entry being processed is determined according to the write response ID information on the interface, the recorded read transmission transaction initiator order (write response initiator queue), and the initiator information of each write entry in the circular queue. The write response thread in the circular queue passes the data on the receiver write response interface to the initiator device according to the obtained destination initiator device number, and updates the content in the corresponding transmission control information entry. During this process, only after the entry corresponding to the "previous response transaction position" in the entry is completed, can this entry allow data transmission to handle the situation of the same initiator, different receivers, and the same transaction ID. After a write entry is completed, the data at the corresponding position will be removed from the write response initiator queue. The design of this mechanism supports Out of Order, ensures that the write response messages with the same initiator and the same ID are returned in order, and the write response operations of different initiators or different IDs do not affect each other. During this process, if there is an initiator or receiver timeout response, the corresponding entry will be forced to end or forced to be transmitted to ensure that the overall communication process is not blocked after any device suddenly stops responding.

[0095] The on-chip transaction processing system provided by the embodiment of the present application includes: a plurality of initiators, an interconnection module, and a plurality of receivers; the initiators are used to send transactions to be processed to the interconnection module; the interconnection module is used to receive the transactions to be processed sent by the plurality of initiators, screen the transactions to be transmitted from the transactions to be processed sent by the plurality of initiators according to the transmission control information of the transactions to be processed, and send the transactions to be transmitted to the corresponding receivers; the receivers are used to receive the transactions to be transmitted sent by the interconnection module, and return read response data or write response data to the source initiator of the transaction to be transmitted. In the system provided by the above solution, since an interconnection module is provided between the plurality of initiators and the plurality of receivers, the interconnection module supports the AXI4 protocol, the interconnection module can receive the transactions to be processed sent by the plurality of initiators, screen out the transactions to be transmitted according to the transmission control information of the transactions, and then accurately send them to the corresponding receivers, and the receivers accurately return the read response data or write response data to the source initiator of the transaction to be transmitted, so that the AXI4 protocol can be applied to the application scenarios of the plurality of initiators and the plurality of receivers, and chaotic transmission of transactions is avoided. Moreover, a multi-master multi-slave AXI interconnection mechanism is implemented, meeting the protocol requirements of AXI4 and ensuring the correct transmission order; a timeout mechanism and an error reporting mechanism are designed for the Master device interface and the Slave device interface to handle communication exceptions during the transmission process of the device; a transmission transaction source device identification scheme is designed to determine the destination Master device of the Slave device response data according to the storage order of each entry in the circular queue, the read / write Master device queue of the Slave device, and the AXI4 protocol, without increasing the ID width or sideband signals, realizing transparent transmission.

[0096] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0097] The embodiment of the present application also provides an on-chip transaction processing method, which is applied to the on-chip transaction processing system provided by the above embodiment.

[0098] As Figure 8 shown, it is a schematic flowchart of the on-chip transaction processing method provided by the embodiment of the present application. The on-chip transaction processing method includes: Step 801, sending the transaction to be processed of the initiator to the interconnection module; Step 802, controlling the interconnection module to screen out the transactions to be transmitted from the transactions to be processed sent by the plurality of initiators according to the transmission control information of the transactions to be processed after receiving the transactions to be processed sent by the plurality of initiators, and sending the transactions to be transmitted to the corresponding receivers; Step 803: Based on the transaction to be transmitted received by the receiving end, return a read response data or a write response data to the source initiator of the transaction to be transmitted.

[0099] For the description of the features in the corresponding embodiments of the on-chip transaction processing method, reference can be made to the relevant descriptions in the corresponding embodiments of the on-chip transaction processing system, which will not be elaborated here one by one.

[0100] An embodiment of the present application also provides an electronic device, such as Figure 9 As shown, it is a schematic structural diagram of the electronic device provided by the embodiment of the present application, including a processor 10 and a memory 20. A computer program is stored in the memory 20, and the processor 10 is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the on-chip transaction processing method.

[0101] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any of the above-mentioned embodiments of the on-chip transaction processing method when running.

[0102] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (abbreviated as ROM), random access memory (abbreviated as RAM), mobile hard disk, magnetic disk or optical disc, etc., various media that can store computer programs.

[0103] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the on-chip transaction processing method.

[0104] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned embodiments of the on-chip transaction processing method.

[0105] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0106] The above has introduced in detail a on-chip transaction processing system, method, electronic device, and storage medium provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An on-chip transaction processing system, characterized in that: include: Multiple initiators, interconnect modules and multiple receivers; The initiator is used to send the pending transaction to the interconnection module; The interconnection module is used to receive the pending transactions sent by the multiple initiators, filter the pending transactions from the pending transactions sent by the multiple initiators according to the transmission control information of the pending transactions, and send the pending transactions to the corresponding receiving end; The receiving end is used to receive the transaction to be transmitted sent by the interconnection module, and return read response data or write response data to the source initiator of the transaction to be transmitted.

2. The on-chip transaction processing system according to claim 1, characterized in that: The interconnection module comprises: An arbitration module, configured to send the pending transactions to the transmission control module in order according to the priority of each of the initiating terminals and the attribute information of the pending transactions; A transmission control module, used to parse any of the pending transactions, obtain transmission control information of the pending transaction, write the transmission control information as a transaction entry into a preset circular queue, and filter the pending transactions by traversing the preset circular queue; The transmission control information of the transaction to be processed at least includes a source initiator identifier, a destination receiver identifier, an address to be accessed, a transaction identifier, a read / write identifier, and a transmission status identifier.

3. The on-chip transaction processing system according to claim 2, characterized in that: The transmission control module is specifically used for: When transmission control information of any transaction to be processed is obtained, locating the tail of the corresponding transmission transaction waiting sequence in the preset ring queue according to the source initiator identifier represented by the transmission control information; Starting from the end of the transmission transaction waiting sequence, search for a node whose transmission status is marked as idle in a clockwise direction toward the queue maintenance pointer, and insert the node as a target node; The transmission control information is inserted into the target insertion node as a transaction entry, and the transmission state flag of the target insertion node is modified to wait for transmission to start.

4. The on-chip transaction processing system according to claim 3, characterized in that: The transmission control module is further used for: Select any transmission transaction waiting sequence head in the preset ring queue as the destination node; Selecting a node whose transmission status identifier satisfies a preset maintenance condition in the preset ring queue as a node to be maintained; The node to be maintained that is closest to the destination node in the counterclockwise direction is used as the target maintenance node, and the queue maintenance pointer is moved to the target maintenance node, so that the queue maintenance pointer moves to the boundary position between the transaction node to be responded and the idle node in the preset ring queue; The target maintenance node is the earliest transaction node to be responded to.

5. The on-chip transaction processing system according to claim 3, characterized in that: The transmission control module is further used for: After inserting the transmission control information as a transaction entry into the target insertion node, searching for the first transmission preceding node with the same destination receiving end identifier in a counterclockwise direction from the target insertion node toward the queue maintenance pointer; Using the position of the transmission pre-order node as the pre-order transmission transaction position, and writing the transaction entry of the target insertion node; In the case where the transmission preceding node is not found, the preceding transmission transaction position of the transaction entry of the target insertion node is recorded as an abnormal value.

6. The on-chip transaction processing system according to claim 3, characterized in that: The transmission control module is further used for: After inserting the transmission control information as a transaction entry into the target insertion node, searching for the first preceding response node having the same source initiator identifier, transaction identifier, and read / write identifier in a counterclockwise direction from the target insertion node toward the queue maintenance pointer; Using the position of the preceding response node as the preceding response transaction position, and writing the transaction entry of the target insertion node; In the case where the preceding response node is not found, the preceding response transaction position of the transaction entry of the target insertion node is recorded as an abnormal value.

7. The on-chip transaction processing system according to claim 3, characterized in that: The transmission control module is further used for: When the transmission control information is inserted into the target insertion node as a transaction entry, a preset processing timer is loaded with a timing limit value and starts a countdown; When the countdown of the preset processing timer ends, if the transmission status flag of the target insertion node is still waiting for transmission start, a timeout is triggered, and the transmission status flag of the target insertion node is modified to receiving end timeout waiting for response.

8. The on-chip transaction processing system according to claim 5, characterized in that: The transmission control module is specifically used for: Generate an entry sending thread for each initiator; For any of the initiators, based on the entry sending thread, starting from the head of the transmission transaction waiting sequence corresponding to the initiator, look for the first node whose source initiator identifier is the initiator number, whose transmission status identifier is waiting for transmission to start, and whose read / write identifier is writing, in a clockwise direction toward the queue maintenance pointer, and use the node as the write node to be sent; When it is determined that the write transaction interface state of the destination receiving end corresponding to the to-be-sent write node meets the preset write transaction receiving condition, and the preceding transmission transaction position of the transaction entry of the to-be-sent write node is an abnormal value, the initiator number of the to-be-sent write node is written into the write data initiator queue and the write response initiator queue of the destination receiving end, so that the destination receiving end responds to the write transactions of each of the initiators in sequence; After the initiator number of any of the to-be-sent write nodes is written into the write data initiator queue and the write response initiator queue of the corresponding destination receiving end, the transmission status flag of the to-be-sent write node is changed from waiting for transmission start to transmitting.

9. The on-chip transaction processing system according to claim 8, characterized in that: The transmission control module is further used for: When it is determined that the write transaction interface status of the destination receiving end corresponding to the write node to be sent meets the preset write transaction reception condition, but the preceding transmission transaction position of the transaction entry of the write node to be sent is the preceding transmission transaction position, after determining that the transmission status identifier of the preceding transmission node of the preceding transmission transaction position is in transmission, the initiator number of the write node to be sent is written into the write data initiator queue and the write response initiator queue of the destination receiving end.

10. The on-chip transaction processing system according to claim 8, characterized in that: The transmission control module is further used for: For any of the initiators, based on the entry sending thread, starting from the head of the transmission transaction waiting sequence corresponding to the initiator, look for the first node whose source initiator identifier is the initiator number, whose transmission status identifier is waiting for transmission to start, and whose read / write identifier is read, in a clockwise direction toward the queue maintenance pointer, and use the node as the read node to be sent; When it is determined that the read transaction interface state of the destination receiving end corresponding to the to-be-sent read node meets the preset read transaction receiving condition, and the preceding transmission transaction position of the transaction entry of the to-be-sent read node is an abnormal value, the initiator number of the to-be-sent read node is written into the read response initiator queue of the destination receiving end, so that the destination receiving end responds to the read transactions of each of the initiators in sequence; After the initiator number of any of the to-be-sent read nodes is read into the read response initiator queue of the corresponding destination receiving end, the transmission status identifier of the to-be-sent read node is modified from waiting for transmission start to waiting for response.

11. The on-chip transaction processing system according to claim 8, characterized in that: The initiator is used for: Starting from the queue maintenance pointer, search clockwise toward the transmission transaction waiting sequence head corresponding to the initiator for the first node whose source initiator identifier is the initiator number, whose transmission status identifier is transmitting, and whose read / write identifier is writing, and use the node as the write node for the data to be transmitted; When it is determined that the write data interface states of the destination receiving end and the initiating end corresponding to the write node of the data to be transmitted both meet the preset write data receiving condition, transmitting the write data to the destination receiving end once; When it is determined that the destination receiving end corresponding to the write node of the data to be transmitted meets the preset write data receiving condition, but the write data interface state of the initiating end does not meet the preset write data receiving condition, or when the write data interface states of both the destination receiving end and the initiating end do not meet the preset write data receiving condition, the transmission of the write data is terminated, and the transmission state flag of the write node of the data to be transmitted is modified to the initiating end response timeout; When it is determined that the write data interface state of the initiator corresponding to the write node of the data to be transmitted meets the preset write data receiving condition, but the destination receiving end does not meet the preset write data receiving condition, forcibly transmit the write data to the destination receiving end once, and modify the transmission state flag of the write node of the data to be transmitted to the receiving end response timeout; When the data writing node to be transmitted meets the preset state modification condition, if the transmission state of the data writing node to be transmitted is marked as transmitting, then the state is modified to waiting for response; If the transmission status of the write node of the data to be transmitted is marked as the initiator response timeout, modify it to the initiator timeout waiting for response; If the transmission status of the write node of the data to be transmitted is marked as receiving end response timeout, modify it to receiving end timeout waiting for response; When the transmission status of any node in the preset ring queue is marked as waiting for response, the initiator timed out waiting for response, or the receiver timed out waiting for response, it is determined that the node meets the preset maintenance condition.

12. The on-chip transaction processing system according to claim 10, characterized in that: The receiving end is used for: When the read data interface obtains any read response data, the node whose first destination receiving end identifier is the receiving end number and whose transaction identifier matches the return identifier of the read response data is searched clockwise from the queue maintenance pointer, and the node is used as the read node to be returned; Determine whether the source initiator identifier of the to-be-returned read node is the first to-be-matched node in the read response initiator queue of the receiving end; In the case where the source initiator identifier of the read node to be returned is not the first node to be matched in the read response initiator queue of the receiving end, the node to be matched is modified to an unmatched node, the read node to be returned is defined as a node not to be searched in the next round, and the step of searching in a clockwise direction from the queue maintenance pointer for the first node whose destination receiving end identifier is the receiving end number and whose transaction identifier matches the return identifier of the read response data, and taking the node as the read node to be returned, so as to re-screen the read node to be returned; In a case where the source initiator of the to-be-returned read node is identified as the first to-be-matched node in the read response initiator queue of the receiving end, the read response data is transmitted to the source initiator corresponding to the to-be-returned read node.

13. The on-chip transaction processing system according to claim 12, characterized in that: The transmission control module is used to: When the transmission status flag of any node in the preset ring queue is changed to waiting for response, the node is used as a read response node; When it is determined that the transmission status identifier of the response predecessor node corresponding to the predecessor response transaction position of the read response node is idle, start waiting for the read data interface of the destination receiving end corresponding to the read response node to obtain the read response data; If the read data interface of the destination receiving end obtains the read response data within the preset waiting period, then determining whether the read data interface of the source initiating end corresponding to the read response node meets the preset read data receiving condition; When it is determined that the read data interface of the source initiator corresponding to the read response node meets the preset read data receiving condition, the source initiator receives the read response data returned by the destination receiving end based on the read data interface.

14. The on-chip transaction processing system according to claim 13, characterized in that: The transmission control module is further used for: When the pending read transaction corresponding to the read response node completes the target number of responses, determining that the pending read transaction of the read response node has been completed, and modifying the transmission status flag of the read response node to idle; If the read data interface of the destination receiving end does not obtain the read response data within the preset waiting period, the pending read transaction corresponding to the read response node is forcibly terminated, and the transmission status flag of the read response node is modified to idle.

15. The on-chip transaction processing system according to claim 11, characterized in that: The transmission control module is used to: When the transmission status flag of any node in the preset ring queue is changed to waiting for response, the initiator timed out waiting for response, or the receiver timed out waiting for response, the node is used as a write response node; When it is determined that the transmission status identifier of the response predecessor node corresponding to the predecessor response transaction position of the write response node is idle, start waiting for the write response interface of the destination receiving end corresponding to the write response node to obtain write response data; If the write response interface of the destination receiving end obtains write response data within the preset waiting period, then determining whether the write response interface of the source initiating end corresponding to the write response node meets the preset write response receiving condition; When it is determined that the write response interface of the source initiator corresponding to the write response node meets a preset write response receiving condition, the source initiator receives the write response data returned by the destination receiving end based on the write response interface.

16. The on-chip transaction processing system according to claim 15, characterized in that: The transmission control module is further used for: When the pending write transaction corresponding to the write response node obtains a target number of write response data, determining that the pending write transaction of the write response node has been completed, and modifying the transmission status flag of the write response node to idle; If the write response interface of the destination receiving end does not obtain write response data within the preset waiting period, the pending write transaction corresponding to the write response node is forcibly terminated, and the transmission status flag of the write response node is modified to idle.

17. An on-chip transaction processing method, characterized in that: Applied to the on-chip transaction processing system according to any one of claims 1 to 16, the method comprising: Sending pending transactions of the initiator to the interconnection module; After receiving the pending transactions sent by the multiple initiators, the interconnection module is controlled to select the pending transactions from the pending transactions sent by the multiple initiators according to the transmission control information of the pending transactions, and send the pending transactions to the corresponding receiving end; The receiving end receives the transaction to be transmitted sent by the interconnection module, and returns read response data or write response data to the source initiator of the transaction to be transmitted.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to implement the steps of the on-chip transaction processing method as claimed in claim 17 when executing the computer program.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the on-chip transaction processing method as claimed in claim 17.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the on-chip transaction processing method according to claim 17 are implemented.

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