Chip port correction method and device

Abstract

The invention provides a chip port correction method and device, and the method can obtain a first chip design file and a second chip design file, and the second chip design file is a chip design file of a previous version of the first chip design file. And analyzing the chip port information in the first chip design file and the chip port information in the second chip design file. Comparing the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly-added chip port information and / or deleted chip port information, adding the newly-added chip port information in the second chip design file, and / or deleting the newly-added chip port information in the second chip design file. Deleting the deleted chip port information in the second chip design file. According to the method, the change of the chip port can be automatically checked and corrected, and the chip simulation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a chip port correction method and device. Background Art

[0002] Chip verification, also known as chip simulation, refers to a comprehensive inspection and verification of the chip design through a series of tests and simulation methods to ensure that the chip can work properly in actual applications. It mainly includes two types of simulation scenarios. The first type is the functional verification of the chip's functions, also known as pre-simulation or pre-emulation. The second type is the timing verification of the delay caused by the electrical signal flowing through the gate units and electrical circuits inside the chip under specific manufacturing processes (such as 4nm process, etc.) and specific temperature conditions to ensure the stability of clock sampling and the stability of chip operation, also known as post-simulation or post-emulation.

[0003] During chip development, as chip functionality requirements change, ports are often added, removed, renamed, or their directions modified. Each time port information changes, simulation becomes unavailable, requiring manual inspection and individual revisions. Simulation can only resume normal operation after all modifications are complete and correct, reducing efficiency. Summary of the Invention

[0004] The present application provides a chip port correction method and device to solve the problem of low chip simulation efficiency.

[0005] In a first aspect, the present application provides a chip port correction method, the method comprising:

[0006] Obtaining a first chip design file and a second chip design file, where the second chip design file is a chip design file that is a previous version of the first chip design file;

[0007] parsing chip port information in the first chip design file and chip port information in the second chip design file;

[0008] Comparing the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information; the newly added chip port information is chip port information that exists in the first chip design file but does not exist in the second chip design file, and the deleted chip port information is chip port information that does not exist in the first chip design file but exists in the second chip design file;

[0009] The newly added chip port information is added to the second chip design file, and / or the deleted chip port information is deleted from the second chip design file.

[0010] In a second aspect, the present application provides a chip port correction device, comprising a parameter parser, a file parser, a port checker, and a port corrector; wherein:

[0011] The parameter parser is configured to obtain a first chip design file and a second chip design file, where the second chip design file is a chip design file of a previous version of the first chip design file;

[0012] The file parser is configured to parse the chip port information in the first chip design file and the chip port information in the second chip design file;

[0013] The port checker is used to compare the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information; the newly added chip port information is chip port information that exists in the first chip design file and does not exist in the second chip design file, and the deleted chip port information is chip port information that does not exist in the first chip design file and exists in the second chip design file;

[0014] The port corrector is used to add the newly added chip port information to the second chip design file, and / or delete the deleted chip port information in the second chip design file.

[0015] It can be seen from the above technical solution that the present application provides a chip port correction method and device, the method can obtain a first chip design file and a second chip design file, the second chip design file is a chip design file of the previous version of the first chip design file. Parse the chip port information in the first chip design file and the chip port information in the second chip design file. Compare the chip port information in the first chip design file and the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information, add the newly added chip port information in the second chip design file, and / or delete the deleted chip port information in the second chip design file. The method can automatically check and correct changes in chip ports and improve chip simulation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic diagram of a pre-simulation verification system provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of a post-simulation verification system provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of a verification system for DC netlist simulation provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the architecture of a chip port correction device provided in an embodiment of the present application;

[0021] Figure 5 A schematic flow chart of a chip port correction method provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of a first chip design file provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of a second chip design file provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of a first chip design file added to a port provided in an embodiment of the present application;

[0025] Figure 9 A schematic diagram of a first chip design file with reduced ports provided in an embodiment of the present application;

[0026] Figure 10 A schematic diagram of a first chip design file with modified port information provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following embodiments are described in detail, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numbers in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following embodiments are not intended to represent all possible implementations consistent with the present application. They are merely examples of systems and methods consistent with certain aspects of the present application, as detailed in the claims.

[0028] Chip verification, also known as chip simulation, refers to a comprehensive inspection and verification of the chip design through a series of tests and simulation methods to ensure that the chip can work properly in actual applications. It mainly includes two types of simulation scenarios. The first type is the functional verification of the chip's functions, also known as pre-simulation or pre-emulation. The second type is the timing verification of the delay caused by the electrical signal flowing through the gate units and electrical circuits inside the chip under specific manufacturing processes (such as 4nm process, etc.) and specific temperature conditions to ensure the stability of clock sampling and the stability of chip operation, also known as post-simulation or post-emulation.

[0029] The different stages or forms of a chip in the design process can be represented by the register transfer level (RTL), the netlist generated after place and route (PR), and the netlist generated after design synthesis (DC). In other words, the RTL, PR, and DC netlists are all different forms of the same chip in the design process, used in different verification scenarios, but they are essentially the same chip.

[0030] like Figure 1 As shown, in the basic process of pre-simulation, the chip RTL module and the verification system are instantiated. The verification engineer manually connects the chip RTL module and the verification system to complete the information exchange and functional verification between the RTL module and the verification system. During the RTL development process, as the chip functional requirements change, ports are often added, reduced, modified, and their directions are modified. Each time the functional port of the RTL module changes, simulation will be unable to proceed. The verification engineer needs to manually compare the functional ports of the RTL module instantiated on the current test platform with the newly changed RTL module, and manually modify and debug all change points. Only after all modifications are completed and correct can the pre-simulation resume normal operation.

[0031] like Figure 2As shown in the figure, the basic post-simulation process instantiates the chip PR netlist module and the verification system. Verification engineers manually connect the chip PR netlist module and the verification system to complete the interaction and timing verification between the PR netlist and the verification system. Chip manufacturing defects can cause chip functional failures. Therefore, design for test (DFT) is performed during the chip design phase. Test ports, such as the production test scan port (ptest_scan) and the memory built-in self-test port (mbist), are reserved during the design phase to detect defects introduced by chip manufacturing after chip return. The ptest_scan port and the mbist port are both used to detect and locate chip manufacturing faults and defects after chip return. The ptest_scan port is used to detect whether the manufacturing process has caused physical damage to the chip's registers and logic circuits, while the mbist port is used to detect whether the manufacturing process has caused physical damage to the chip's memory (such as static random access memory (SRAM)).

[0032] During the chip post-simulation stage, the port information and quantity of test ports such as the ptest_scan port and mbist port in each version of the PR netlist provided by the back-end engineer will change. Therefore, each version of the netlist also requires verification engineers to manually compare the signal changes of the ptest_scan port, mbist port and other test ports between the new and previous versions, and manually modify and debug all change points. Only after all modifications are completed and correct can the post-simulation resume normal operation.

[0033] like Figure 3 As shown in the figure, in addition to pre- and post-simulation, verification engineers may also need to perform DC netlist simulation, which is in between. The difference between a DC netlist and a PR netlist is that a DC netlist only contains logical connection information for gate units and electrical connections, without layout and routing information, while a PR netlist contains both logical connection information for gate units and electrical connections, as well as layout and routing information. The basic DC netlist simulation process also involves changes to functional ports and test ports, requiring verification engineers to manually modify port information and connections. Only after all modifications are complete and correct can the simulation resume normal operation.

[0034] In the above embodiment, during the chip pre-simulation stage, as the requirements for chip functions change during the RTL development process, the port information and number of functional ports may change, such as port addition, port reduction, port name modification, port direction modification, etc. After each version of RTL changes, simulation will be unable to proceed. In order to restore the normal operation of the pre-simulation, the verification engineer needs to manually compare the differences in functional ports between the RTL instantiated on the current test platform and the newly changed RTL, and modify all change points. However, when the number of ports is large and the number of changed ports is large, manual comparison and modification will consume a lot of time, and too many ports can easily lead to human error correction.

[0035] During the chip post-simulation phase, the port information and number of test ports, such as the ptest_scan port and mbist port, will change with each version of the PR netlist provided by the backend engineer. Since the chip's power consumption needs to be continuously analyzed and optimized, and power analysis requires the use of waveform files generated by post-simulation, post-simulation will be performed throughout the chip development phase. Each version of the PR netlist also requires verification engineers to manually compare the signal changes of the ptest_scan port, mbist port, and other test ports between the new and previous versions. Manually comparing and modifying each version is time-consuming and prone to errors. If the input ptest_scan port or mbist port is omitted and left floating (i.e., not connected to a valid signal source), the post-simulation will fall into X-state propagation and cause errors, increasing the engineer's debugging time and reducing simulation efficiency.

[0036] Therefore, in order to solve the above problems, some embodiments of this application provide a chip port correction device for fully or semi-automatically correcting port changes to improve simulation efficiency. Figure 4 FIG2 is a schematic diagram of the architecture of a chip port correction device provided by an embodiment of the present application. The chip port correction device includes a parameter parser, an initialization module, a file parser, a port checker, a port corrector, and an operation controller.

[0037] It should be noted that if Figure 1-3 As shown, the chip port correction device can be used in chip simulation verification systems such as pre-simulation, post-simulation, and DC netlist simulation. It corrects port information in instantiated chip design files such as RTL files, PR netlist files, and DC netlist files in the verification system for changes to chip ports, such as port addition, port reduction, port name modification, and port direction modification. The chip port correction device can also be used in other fields that require port information correction.

[0038] like Figure 5As shown, it is a flow chart of the chip port correction method provided by an embodiment of the present application. The parameter parser obtains and parses the parameters input from the outside to obtain the chip design file that needs to be corrected for the chip port, including a first chip design file and a second chip design file, and the second chip design file is a chip design file of the previous version of the first chip design file. The first chip design file includes the chip port information on the latest version of the chip, and the second chip design file includes the chip port information on the previous version of the chip. For example, the chip design file can be an RTL file, a PR netlist file, a DC netlist file, etc.

[0039] For example, Figure 6 As shown, it is a schematic diagram of the first chip design file provided in an embodiment of the present application. The first chip design file includes chip port information under the top-level module name npu_teng_sys. The chip port information includes the port name and port direction corresponding to the chip port. The port types of the chip port include two types: functional port (such as clock port (clk), read and write flag signal port (pwrite)) and test port (such as ptest_scan port, mbist port), and the port direction includes input direction (input) and output direction (output).

[0040] like Figure 7 FIG2 is a schematic diagram of a second chip design file provided in an embodiment of the present application. The second chip design file includes chip port information under the top-level module name npu_teng_sys of the previous version. The chip port information includes the port name, port direction, and port connection identifier corresponding to the chip port. The port connection identifier is used to represent the connection line connected to the chip port.

[0041] The file parser parses the first chip design file and the second chip design file as well as the chip port information in the first chip design file and the chip port information in the second chip design file.

[0042] The port checker compares the chip port information in the first chip design file with the chip port information in the second chip design file to determine whether each chip port is newly added, unchanged, or deleted, thereby obtaining newly added chip port information and / or deleted chip port information.

[0043] Among them, the newly added chip port information is the chip port information of the newly added chip port, that is, the chip port information that exists in the first chip design file and does not exist in the second chip design file. The deleted chip port information is the chip port information of the deleted chip port, that is, the chip port information that does not exist in the first chip design file and exists in the second chip design file. The unchanged chip port information is the chip port information of the unchanged chip port, that is, the chip port information that exists in both the first chip design file and the second chip design file.

[0044] The port corrector corrects the second chip design file based on the results of the port checker. It deletes the deleted chip port information from the second chip design file, adds the newly added chip port information to the second chip design file, and leaves the unchanged chip port information untouched. In other words, the newly added chip port information is added to the second chip design file, and the deleted chip port information is deleted from the second chip design file, thereby completing the chip port correction.

[0045] In some embodiments, in order to manage the changes in chip ports in a more fine-grained manner, queues can be used to store chip port information. A first queue and a second queue can be created according to the port direction and port type. The port direction includes input direction and output direction, and the port type includes functional port and test port. The first queue is used to store the chip port information belonging to the target port direction and target port type in the first chip design file, and the second queue is used to store the chip port information belonging to the target port direction and target port type in the second chip design file. The target port direction is the input direction or the output direction, and the target port type is the functional port or the test port. That is to say, for the chip design file, multiple queues are created, and each queue is used to store chip port information with the same port direction and port type.

[0046] When the chip port is modified, the initialization module may initialize the first queue and the second queue so as to subsequently classify the chip port information in the first chip design file and the chip port information in the second chip design file.

[0047] After initialization, the file parser can parse the first chip design file and the second chip design file, then traverse the chip port information in the first chip design file and add the chip port information that belongs to the target port direction and target port type in the first chip design file to the first queue. Similarly, the file parser can traverse the chip port information in the second chip design file and add the chip port information that belongs to the target port direction and target port type in the second chip design file to the second queue. In other words, the chip port information with the same port direction and port type in the chip design file is stored in the same queue.

[0048] The port checker may compare the first queue and the second queue to obtain newly added chip port information and / or deleted chip port information.

[0049] In some embodiments, for the port direction, the first chip design file is a new version of the chip design file, in which the port direction is declared. The second chip design file is an instantiation of the previous version of the chip design file, and the port direction is in the comments of the file. Therefore, the file parser can read the declared port direction in the declaration information of the first chip design file to obtain the port direction to which the chip port information in the first chip design file belongs. The annotated port direction is read in the comment information of the second chip design file to obtain the port direction to which the port information in the second chip design file belongs.

[0050] For port types, test ports have relatively uniform port names and include a specific test port identifier. For example, the ptest_scan port's name includes the identifier "ptest_scan," and the mbist port's name includes the identifier "mbist." Therefore, you can read the port name of the chip port information. If the port name includes the test port identifier, the chip port information is marked as a test port. If the port name does not include the test port identifier, the chip port information is marked as a functional port.

[0051] In some embodiments, in order to manage changes in chip ports in a more fine-grained manner, queues can be used to store newly added, deleted, and unchanged chip port information separately. That is, a newly added queue, an unchanged queue, and a deleted queue can be created according to the newly added, deleted, and unchanged categories, port directions, and port types. The newly added queue is used to store newly added chip port information belonging to the target port direction and target port type, the deleted queue is used to store deleted chip port information belonging to the target port direction and target port type, and the unchanged queue is used to store unchanged chip port information belonging to the target port direction and target port type. In other words, chip port information with the same port direction and port type is stored separately according to the newly added, deleted, and unchanged categories.

[0052] When modifying a chip port, the initialization module can initialize the newly added queue, unchanged queue, and deleted queue to facilitate subsequent classification of the chip port information. After initialization, the file parser can parse the chip port information in the first chip design file and the chip port information in the second chip design file, storing chip port information with the same port direction and port type in the first chip design file in the first queue, and classifying chip port information with the same port direction and port type in the second chip design file in the second queue.

[0053] The port checker checks the chip port information in the first and second queues, adding chip port information that exists in both the first and second queues to the unchanged queue and deleting chip port information that exists in both the first and second queues from the second queue. Furthermore, the chip port information that exists in the first queue but not in the second queue is added to the newly added queue. Finally, the remaining chip port information in the second queue is added to the deleted queue.

[0054] The port corrector can correct the second chip design file according to the deleted queue, the newly added queue and the unchanged queue, delete the chip port information in the deleted queue in the second chip design file, add the chip port information in the newly added queue in the second chip design file, and do not process the chip port information in the unchanged queue, thereby completing the chip port correction.

[0055] In some embodiments, the deleted chip port information may be directly deleted from the second chip design file. The newly added chip port information may be added to the second chip design file according to a preset format.

[0056] In some embodiments, the chip port information in the second chip design file includes a port name, a port direction, and a port connection identifier. The port connection identifier is used to represent the connection line connected to the chip port corresponding to the chip port information, for example Figure 1-3 The configuration lines, read data lines, write data lines, etc. shown in . When adding new chip port information, the port modifier can set the port connection identifier corresponding to the new chip port information belonging to the functional port to the target identifier, which is used to indicate the connection line connected to the chip port corresponding to the new chip port information. Set the port connection identifier corresponding to the new chip port information belonging to the input direction and test port to the default identifier. Set the port connection identifier corresponding to the new chip port information belonging to the output direction and test port to the floating identifier, which is used to indicate that the chip port corresponding to the new chip port information is not connected to a connection line.

[0057] For example, the preset format may be ".port name (port connection identifier), / / port direction". Taking a newly added clock port (functional port) with a port name of clk_i and a port direction of input as an example, the chip port information may be added to the second chip design file: .clk_i(AAAA), / / input. " / / input" is a comment, and the chip port information indicates that the clk_i port signal is in the input direction, and the clk_i port is connected to the wire AAAA. The port connection identifier may be manually entered by the user, and the chip port information may be added to the second chip design file: .clk_i(), / / input. clk_i() indicates that the clk_i port is floating and may be manually entered by the user.

[0058] For example, a newly added ptest_scan port (test port) with the port name ptest_scan_k and the port direction set to input can be added to the second chip design file: .ptest_scan_k(0), / / input. The ptest_scan_k port is connected to 0 by default and cannot be left floating to avoid X-state propagation problems in subsequent simulations.

[0059] Taking the newly added mbist port (test port) with the port name mbist_k and the port direction as output as an example, the chip port information can be added in the second chip design file: .mbist_k(), / / output. The mbist_k port is left floating and not connected to the connection line.

[0060] In some embodiments, in order to implement chip simulation control, a run control identifier can be set, and the run control identifier includes a first identifier and a second identifier. The first identifier is used to indicate that chip simulation is not performed, and the second identifier is used to indicate that chip simulation is performed. When the chip port is corrected, the initialization module can initialize the run control identifier and initialize the run control identifier to the second identifier. In the subsequent process, the port corrector can set the run control identifier based on the inspection result of the port checker. When there is new chip port information belonging to the functional port, it means that the user needs to manually connect the chip port, and the run control identifier is set to the first identifier to stop the subsequent simulation process. When there is no new chip port information belonging to the functional port, the run control identifier is set to the second identifier to start the subsequent simulation process.

[0061] The port modifier can detect the newly added queue, and if the newly added queue includes chip port information belonging to the functional port, indicating that the newly added chip port information belonging to the functional port exists, the operation control flag is set to the first flag. If the newly added queue does not include chip port information belonging to the functional port, indicating that the newly added chip port information belonging to the functional port does not exist, the operation control flag is set to the second flag.

[0062] Based on the above embodiment, the operation controller determines whether to start subsequent simulation based on the operation control flag. The operation control flag can be read. If the operation control flag is a first flag, the control verification system does not perform chip simulation. If the operation control flag is a second flag, the control verification system performs chip simulation using the chip design file.

[0063] The chip port correction process provided by this application is described below with reference to specific embodiments.

[0064] The parameter parser obtains the latest version of the chip design file, that is, the first chip design file, such as the RTL file, the PR netlist file, the DC netlist file, and the like.

[0065] The parameter parser obtains the previous version of the chip design file instantiated in the verification system, that is, the second chip design file.

[0066] The parameter parser parses and obtains the top-level module name. For example, the top-level module name is npu_teng_sys.

[0067] The initialization module initializes the register need_manu_connect and sets the value of the register need_manu_connect to 0. The value of the register need_manu_connect is used to represent the operation control flag. When it is set to 0, it indicates starting the subsequent simulation, and when it is set to 1, it indicates stopping the subsequent simulation.

[0068] The initialization module creates eight queues within the device. The queue names can be set according to the file version, port direction, and port type. The eight queues are named: new_input_function_port_queue, new_output_function_port_queue, new_input_test_port_queue, new_output_test_port_queue, old_input_function_port_queue, old_output_function_port_queue, old_input_test_port_queue, and old_output_test_port_queue. The first four queues are used to store the chip port information in the first chip design file, and the last four queues are used to store the chip port information in the second chip design file. This allows for categorized storage of the chip port information in the first and second chip design files.

[0069] It is understandable that for the above queue names, "new" represents the new version, "old" represents the old version, "input" represents the input direction, "output" represents the output direction, "function" represents the function port, and "test" represents the test port. The queue named "new_input_function_port_queue" is used to store the chip port information corresponding to the chip port with the port direction as input and the port type as function port in the first chip design file. The chip port information stored in other queues can be inferred based on the above queue names and will not be detailed here.

[0070] The initialization module creates 12 queues within the device. Queue names can be set based on the port change type, port direction, and port type. The 12 queues are named: add_input_function_port_queue, add_output_function_port_queue, add_input_test_port_queue, add_output_test_port_queue, unchanged_input_function_port_queue, unchanged_output_function_port_queue, unchanged_input_test_port_queue, unchanged_output_test_port_queue, deleted_input_function_port_queue, deleted_output_function_port_queue, deleted_input_test_port_queue, and deleted_output_test_port_queue. These 12 queues categorize and store the comparison results of the chip port information between the first and second chip design files.

[0071] It's understandable that "add" indicates a new addition, "unchanged" indicates unchanged, and "deleted" indicates deleted. The queue named "add_input_function_port_queue" is used to store chip port information corresponding to newly added chip ports with input direction and function port type. The chip port information stored in other queues can be inferred based on the above queue names and is not detailed here.

[0072] The file parser searches the first chip design file for the corresponding top-level module and chip port information of all chip ports under the top-level module according to the top-level module name npu_teng_sys.

[0073] The file parser traverses all chip port information under the npu_teng_sys module in the first chip design file, reads the port direction declaration of each chip port in the first chip design file, determines whether the port direction of the chip port is input direction or output direction, and then determines whether the port name of the chip port contains test port identifiers such as ptest_scan and mbist. If it contains, the port type of the chip port is determined to be a test port. If not, the port type of the chip port is determined to be a functional port.

[0074] According to the above detection results, if the port direction of the chip port is input and the port type is test port, the chip port information of the chip port is added to the queue new_input_test_port_queue. If the port direction of the chip port is output and the port type is test port, the chip port information of the chip port is added to the queue new_output_test_port_queue. If the port direction of the chip port is input and the port type is function port, the chip port information of the chip port is added to the queue new_input_function_port_queue. If the port direction of the chip port is output and the port type is function port, the chip port information of the chip port is added to the queue new_output_function_port_queue.

[0075] Based on the above steps, the chip port information of all chip ports under the npu_teng_sys module in the first chip design file is classified and stored.

[0076] Similarly, the file parser traverses the chip port information of all chip ports under the npu_teng_sys module in the second chip design file, reads the port direction annotations of each chip port in the second chip design file, determines whether the port direction of the chip port is input direction or output direction, and then determines whether the port name of the chip port contains test port identifiers such as ptest_scan and mbist. If it contains, the port type of the chip port is determined to be a test port. If not, the port type of the chip port is determined to be a functional port.

[0077] According to the above detection results, if the port direction of the chip port is input and the port type is test port, the chip port information of the chip port is added to the queue old_input_test_port_queue. If the port direction of the chip port is output and the port type is test port, the chip port information of the chip port is added to the queue old_out put_test_port_queue. If the port direction of the chip port is input and the port type is function port, the chip port information of the chip port is added to the queue old_input_function_port_queue. If the port direction of the chip port is output and the port type is function port, the chip port information of the chip port is added to the queue old_out put_function_port_queue.

[0078] Based on the above steps, the chip port information of all chip ports under the npu_teng_sys module in the second chip design file is classified and stored.

[0079] After the chip port information is classified and stored, the file parser can print and record the chip port information in the above 8 queues in the port check log file to facilitate subsequent manual debugging.

[0080] The port checker extracts the chip port information of a chip port from the queue new_input_test_port_queue, assuming it is port_a, and traverses the queue old_input_test_port_queue to find whether the port_a port exists. If so, it means that the port_a port is an unchanged chip port. Then, the chip port information of the port_a port is deleted from the queue old_input_test_port_queue, and the chip port information of the port_a port is added to the queue unchanged_input_test_port_queue.

[0081] If not, it means that port_a is a newly added chip port, so port_a is added to the queue add_input_test_port_queue.

[0082] The port checker loops through the above steps until the queue new_input_test_port_queue is empty.

[0083] The port checker then determines whether the queue old_input_test_port_queue is empty. If it is not empty, it means that the remaining chip ports have been deleted in the new version. Then, the chip port information of the remaining chip ports in the queue is added to the queue deleted_input_test_port_queue.

[0084] Similarly, the port checker extracts the chip port information of a chip port from the queue new_output_test_port_queue, assuming it is port_b, and traverses the queue old_output_test_port_queue to find whether the port_b port exists. If so, it means that port_b is an unchanged chip port. Then, the chip port information of the port_b port is deleted from the queue old_output_test_port_queue and the chip port information of the port_b port is added to the queue unchanged_output_test_port_queue.

[0085] If not, it means that port_b is a newly added chip port, so port_b is added to the queue add_outp ut_test_port_queue.

[0086] The port checker loops through the above steps until the queue new_output_test_port_queue is empty.

[0087] The port checker then determines whether the queue old_output_test_port_queue is empty. If it is not empty, it means that the remaining chip ports have been deleted in the new version, and then the chip port information of the remaining chip ports in the queue is added to the queue deleted_output_test_port_queue.

[0088] Similarly, the port checker extracts the chip port information of a chip port from the queue new_input_function_port_queue, assuming it is port_c, and traverses the queue old_input_function_port_queue to find whether the port_c port exists. If so, it means that the port_c port is an unchanged chip port. Then, the chip port information of the port_c port is deleted from the queue old_input_function_port_queue, and the chip port information of the port_c port is added to the queue unchanged_input_function_port_queue.

[0089] If not, it means that port_c is a newly added chip port, then port_c will be added to the queue add_input_function_port_queue.

[0090] The port checker loops through the above steps until the queue new_input_function_port_queue is empty.

[0091] The port checker then determines whether the queue old_input_function_port_queue is empty. If it is not empty, it means that the remaining chip ports have been deleted in the new version, and then the chip port information of the remaining chip ports in the queue is added to the queue deleted_input_function_port_queue.

[0092] Similarly, the port checker extracts the chip port information of a chip port from the queue new_output_function_port_queue, assuming it is a port_d port, and traverses the queue old_output_function_port_queue to find whether the port_d port exists. If so, it means that the port_d port is an unchanged chip port. Then, the chip port information of the port_d port is deleted from the queue old_output_function_port_queue, and the chip port information of the port_d port is added to the queue unchanged_output_function_port_queue.

[0093] If not, it means that the port_d port is a newly added chip port, then the port_d port will be added to the queue add_outp ut_function_port_queue.

[0094] The port checker loops through the above steps until the queue new_output_function_port_queue is empty.

[0095] The port checker then determines whether the queue old_output_function_port_queue is empty. If it is not empty, it means that the remaining chip ports have been deleted in the new version, and then the chip port information of the remaining chip ports in the queue is added to the queue deleted_output_function_port_queue.

[0096] After the chip port information is classified and stored, the file parser can print and record the chip port information in the above 12 queues in the port check log file to facilitate subsequent manual debugging.

[0097] The port modifier can determine whether the queue add_input_function_port_queue and the queue add_output_function_port_queue are empty. If there is a non-empty queue, it means that a new function port has been added. The new function port will be left hanging, indicating that the user needs to manually connect it later, and the internal register need_manu_connect of the device will be set to 1, indicating that subsequent simulation will be stopped and the user will be prompted to manually connect it later.

[0098] The port corrector performs chip port correction based on the 12 queues described above. For deleted chip ports, the port corrector extracts the chip port information of a deleted chip port from the queue deleted_input_function_port_queue, assuming it is port_e. It then searches for the chip port information of port_e by port name under the npu_teng_sys module in the second chip design file and deletes the chip port information. This step is repeated repeatedly until the queue deleted_input_function_port_queue is empty.

[0099] Similarly, the port modifier extracts the chip port information of a deleted chip port from the queue deleted_output_function_port_queue. Assume it is port_f. It then searches for the chip port information of port_f by port name under the npu_teng_sys module in the second chip design file and deletes the chip port information. This step is repeated repeatedly until the queue deleted_output_function_port_queue is empty.

[0100] Similarly, the port corrector extracts the chip port information of a deleted chip port from the queue deleted_input_test_port_queue, assuming it is port_g. It then searches for the chip port information of port_g by port name under the npu_teng_sys module in the second chip design file and deletes the chip port information. This step is repeated repeatedly until the queue deleted_input_test_port_queue is empty.

[0101] Similarly, the port corrector extracts the chip port information of a deleted chip port from the queue deleted_output_test_port_queue, assuming it is port_h. It then searches for the chip port information of port_h by port name under the npu_teng_sys module in the second chip design file and deletes the chip port information. This step is repeated repeatedly until the queue deleted_output_test_port_queue is empty.

[0102] For the newly added chip port, the port modifier extracts the chip port information of a newly added chip port from the queue add_input_function_port_queue, assuming it is the port_i port, and adds a line of text under the npu_teng_sys module in the second chip design file in the format of ".port_i(), / / input".

[0103] Similarly, the port modifier extracts the chip port information of a newly added chip port from the queue add_output_function_port_queue, assuming it is the port_j port, and adds a line of text under the npu_teng_sys module in the second chip design file, with the format of ".port_j(), / / output".

[0104] Similarly, the port modifier extracts the chip port information for a newly added chip port from the add_input_test_port_queue queue. Assume it is port_k. In the second chip design file, add a line of text below the npu_teng_sys module in the format ".port_k(0), / / input." This ensures that the input test port cannot be left floating to avoid X-propagation issues in subsequent simulations.

[0105] Similarly, the port modifier extracts the chip port information of a newly added chip port from the add_output_test_port_queue queue. Assume it is port_1. In the second chip design file, add a line of text below the npu_teng_sys module in the format ".port_1(), / / output." This means that the output test port must be left unconnected.

[0106] After completing the chip port correction, run the controller to check whether the register need_manu_connect is 1. If it is, print an error message, such as PORT_CHECK_ERROR, to the log, along with need_manu_connect = 1, to indicate an error. Then, stop the subsequent simulation process. If it is 0, print a pass message, such as PORT_CHECK_PASS, to the log, along with need_manu_connect = 0, to indicate that the check and correction passed. Then, start the subsequent simulation process.

[0107] In this embodiment, the chip port correction device can be applied in a variety of scenarios, including pre-simulation RTL stages, post-simulation netlist stages, and DC netlist simulation, demonstrating its broad applicability and versatility. The device can be used independently, manually triggered by a verification engineer, or integrated into a verification system to automatically trigger port checking and correction during the pre-simulation phase, demonstrating strong portability. It also supports a variety of port modification methods, such as adding ports, deleting ports, modifying port names, and changing port directions, ensuring strong compatibility.

[0108] In multiple scenarios such as pre-simulation, post-simulation, and DC netlist simulation, the chip ports of each version may change. If you rely on manual comparison of port modification points and manual modification, it will consume a lot of time and increase the labor cost of chip R&D in scenarios with many scenarios, fast version updates, and a large number of ports. In addition, the solution of manually comparing the port modification points of each version and modifying the differences introduces human factors. Once the number of ports is large or the naming is confusing, manual modification often leads to errors, resulting in port errors being discovered only in the subsequent debugging stage. Based on this chip port correction device, chip ports can be automatically checked and corrected, reducing the probability of errors and improving chip simulation efficiency.

[0109] The chip port correction process provided by this application is described below using three modification scenarios: port addition, port reduction, and port information modification.

[0110] Implementation

[0111] The chip design file is an RTL file, such as Figure 8 As shown in the figure, due to the increase in chip functions, a new pvalid port is added to the new version of the RTL file, and the port direction is input direction.

[0112] The chip port correction device is integrated into the simulation pre-processing process of the verification system. Engineers start the verification system based on the command line. The verification system executes the simulation pre-processing process and the chip port correction device starts running.

[0113] The parameter parser obtains Figure 8 The first chip design file shown and Figure 7 The second chip design file shown has a top-level module name: npu_teng_sys.

[0114] The initialization module performs initialization operations, sets the value of the register need_manu_connect to 0, and initializes the queue.

[0115] The file parser reads the corresponding chip port in the first chip design file according to the top-level module name npu_teng_sys, classifies all chip ports according to port direction and port type, and stores them in 4 queues respectively. The queues after classification and storage are: new_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), new_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), new_input_function_port_queue = (clk, rst_n, penable, pwrite, pwd ata, pvalid (newly added function port)), new_output_function_port_queue = (pready, prdata).

[0116] The file parser reads the corresponding chip ports in the second chip design file according to the top-level module name npu_teng_sys and classifies all chip ports and stores them in four queues respectively. The queues after classification and storage are: old_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), old_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), old_input_function_port_queue = (clk, rst_n, penable, pwrite, pwdata), old_output_function_port_queue = (pready, prdata);

[0117] The port checker checks each chip port in the above 8 queues one by one, and stores them into 12 queues according to port direction, port type, newly added, deleted, and unchanged categories. The queues after inspection are: add_input_function_port_queue = (pvalid), unchanged_input_function_port_queue = (clk, rst_n, penable, pwrite, pwdata), unchanged_output_function_port_queue = (pready, prdata), unchanged_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), unc hanged_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), and the other queues in the 12 queues are all empty.

[0118] Print the inspection results of the above queues in the port inspection log file to facilitate subsequent debugging and analysis.

[0119] If the port modifier detects that the add_input_function_port_queue is not empty, it indicates that a new function port has been added and that engineers need to manually connect it. In this case, the internal register need_manu_connect is set to 1.

[0120] The port corrector performs port correction on the second chip design file, extracts the chip port information of the pvalid port from the queue add_input_function_port_queue, and inserts a line of text, namely .pvalid(), / / input, inside the npu_teng_sys module in the second chip design file.

[0121] The run controller detects register need_manu_connect = 1 and prints an error message in the port check log file, along with need_manu_connect = 1. The subsequent simulation process is then stopped, and the simulation terminates at the pre-processing stage. Therefore, if the verification engineer discovers the simulation has stalled, they can check the port check log file and manually connect the newly added pvalid port. Based on the connection information, they can add the chip port information for the pvalid port, i.e., pvalid(AAAA), / / input.

[0122] After manually connecting the wires, the engineer restarted the verification system using a command line. The verification system performed pre-simulation processing, and the chip port correction device started operating. The initialization module performed initialization operations, setting the value of the need_manu_connect register to 0. The operation controller detected that the register need_manu_connect = 0 and printed a pass message in the port check log file, indicating need_manu_connect = 0. Then, the subsequent simulation process was started, allowing the second chip design file to interact with the verification system and complete the simulation.

[0123] Implementation 2

[0124] The chip design file is a PR netlist file, such as Figure 9 As shown in the figure, due to the reduction of chip functions, one pwrite port is deleted in the new version of the PR netlist file, and the port direction is input direction.

[0125] The chip port correction device is integrated into the simulation pre-processing process of the verification system. Engineers start the verification system based on the command line. The verification system executes the simulation pre-processing process and the chip port correction device starts running.

[0126] The parameter parser obtains Figure 9 The first chip design file shown and Figure 7 The second chip design file shown has a top-level module name: npu_teng_sys.

[0127] The initialization module performs initialization operations, sets the value of the register need_manu_connect to 0, and initializes the queue.

[0128] The file parser reads the corresponding chip port in the first chip design file according to the top-level module name npu_teng_sys, classifies all chip ports according to port direction and port type, and stores them in 4 queues respectively. The queues after classification and storage are: new_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), new_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), new_input_function_port_queue = (clk, rst_n, penable, pwdata), new_output_function_port_queue = (pready, prdata).

[0129] The file parser reads the corresponding chip port in the second chip design file according to the top-level module name npu_teng_sys and classifies all chip ports and stores them in 4 queues respectively. The queues after classification and storage are: old_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), old_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), old_input_function_port_queue = (clk, rst_n, penable, pwrite (deleted function port), pwdata), old_output_function_port_queue = (pready, prdata).

[0130] The port checker checks each chip port in the above 8 queues one by one, and stores them into 12 queues according to port direction, port type, newly added, deleted, and unchanged categories. The queues after inspection are: deleted_input_function_port_queue = (pwrite), unchanged_input_function_port_queue = (clk, rst_n, penable, pw data), unchanged_output_function_port_queue = (pready, prdata), unchanged_input_test_port_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp, npu_teng_mbist_clock), unchanged_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_don e), and the other queues in the 12 queues are empty.

[0131] Print the inspection results of the above queues in the port inspection log file to facilitate subsequent debugging and analysis.

[0132] If the port modifier detects that both the add_input_function_port_queue and add_output_function_port_queue queues are empty, the need_manu_connect register will not be processed.

[0133] The port corrector performs port correction on the second chip design file, extracts the chip port information of the pwrite port from the queue deleted_input_function_port_queu e, searches for the line where the pwrite port is located according to the port name in the npu_teng_sys module of the second chip design file, and deletes the line.

[0134] The operation controller detects that the register need_manu_connect=0, prints the pass information in the port check log file, prints need_manu_connect=0, and then starts the subsequent simulation process to enable the second chip design file and the verification system to interact and realize simulation.

[0135] Implementation Three

[0136] The chip design file is a DC netlist file, such as Figure 10As shown, due to the modification of the chip port naming convention, the port name of the ptest_scan port is renamed from ptest_scan_stream_comp to ai_ptest_scan_stream_comp, with the prefix ai_ added. It can be understood that for changes in chip port information, the device handles the change in principle by deleting the old chip port information and adding the new chip port information.

[0137] The chip port correction device is integrated into the simulation pre-processing process of the verification system. Engineers start the verification system based on the command line. The verification system executes the simulation pre-processing process and the chip port correction device starts running.

[0138] The parameter parser obtains Figure 10 The first chip design file shown and Figure 7 The second chip design file shown has a top-level module name: npu_teng_sys.

[0139] The initialization module performs initialization operations, sets the value of the register need_manu_connect to 0, and initializes the queue.

[0140] The file parser reads the corresponding chip port in the first chip design file according to the top-level module name npu_teng_sys, classifies all chip ports according to port direction and port type, and stores them in 4 queues respectively. The queues after classification and storage are: new_input_test_port_queue = (ptest_scan_spc_disable, ai_ptest_scan_stream_comp (new port name), npu_teng_mbist_clock), new_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), new_input_function_port_queue = (clk, rst_n, pe nable, pwrite, pwdata), new_output_function_port_queue = (pready, prdata).

[0141] The file parser reads the corresponding chip port in the second chip design file according to the top-level module name npu_teng_sys and classifies all chip ports and stores them in 4 queues respectively. The queues after classification and storage are: old_input_test_po rt_queue = (ptest_scan_spc_disable, ptest_scan_stream_comp (old port name), npu_teng_mbist_clock), old_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), old_input_function_port_queue = (clk, rst_n, penable, pwrite, pwdata), old_output_function_port_queue = (pready, prdata).

[0142] The port checker checks each chip port in the above 8 queues one by one, and stores them into 12 queues according to the port direction, port type, newly added, deleted, and unchanged categories. The queues after checking are: add_input_test_port_queue = (ai_ptest_scan_stream_comp (new chip port), deleted_input_test_port_queue = (pte st_scan_stream_comp (chip port deleted), unchanged_input_function_port_queue = (clk, rst_n, penable, pwrite, pwdata), unchanged_output_function_port_queue = (pready, prdata), unchanged_input_test_port_queue = (ptest_scan_spc_disable, npu_teng_mbist_clock), unchanged_output_test_port_queue = (ptest_scan_spc_out, npu_teng_mbist_pass, npu_teng_mbist_done), the other queues in the 12 queues are empty.

[0143] Print the inspection results of the above queues in the port inspection log file to facilitate subsequent debugging and analysis.

[0144] If the port modifier detects that both the add_input_function_port_queue and add_output_function_port_queue queues are empty, the need_manu_connect register will not be processed.

[0145] The port corrector performs port correction on the second chip design file, extracts the chip port information of the ptest_scan_stream_comp port from the queue deleted_input_test_port_queue, searches for the row where the ptest_scan_stream_comp port is located by port name in the npu_teng_sys module of the second chip design file, and deletes the row.

[0146] The port modifier extracts the chip port information of the ptest_scan_stream_comp port from the queue add_input_test_port_queue, and inserts a line of text inside the npu_teng_sys module in the second chip design file, namely .ai_ptest_scan_str eam_comp(0), / / input.

[0147] The operation controller detects that the register need_manu_connect=0, prints the pass information in the port check log file, prints need_manu_connect=0, and then starts the subsequent simulation process to enable the second chip design file and the verification system to interact and realize simulation.

[0148] Based on the above chip port correction device, some embodiments of the present application further provide a chip port correction method, the method comprising the following steps:

[0149] A first chip design file and a second chip design file are obtained, where the second chip design file is a chip design file that is a previous version of the first chip design file.

[0150] Parse chip port information in the first chip design file.

[0151] Parse the chip port information in the second chip design file.

[0152] Compare the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information. Newly added chip port information is chip port information that exists in the first chip design file but not in the second chip design file, and deleted chip port information is chip port information that does not exist in the first chip design file but exists in the second chip design file.

[0153] Add new chip port information to the second chip design file, and / or delete deleted chip port information from the second chip design file.

[0154] The same and similar parts between the various embodiments in this specification can be referenced to each other and will not be repeated here.

[0155] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without expending creative work shall fall within the scope of protection of this application.

Claims

1. A chip port correction method, characterized in that: The method comprises: Obtaining a first chip design file and a second chip design file, where the second chip design file is a chip design file of a previous version of the first chip design file; Parsing chip port information in the first chip design file and chip port information in the second chip design file; Compare the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information; the newly added chip port information is chip port information that exists in the first chip design file but does not exist in the second chip design file, and the deleted chip port information is chip port information that does not exist in the first chip design file but exists in the second chip design file; The newly added chip port information is added to the second chip design file, and / or the deleted chip port information is deleted from the second chip design file.

2. The chip port correction method according to claim 1, characterized in that: The step of comparing the chip port information in the first chip design file with the chip port information in the second chip design file to obtain the newly added chip port information and / or the deleted chip port information includes: Create the first queue and the second queue; Traversing the chip port information in the first chip design file; Add chip port information belonging to a target port direction and a target port type in the first chip design file to the first queue; the target port direction is an input direction or an output direction, and the target port type is a function port or a test port; Traversing the chip port information in the second chip design file; Adding chip port information belonging to target port direction and target port type in the second chip design file to the second queue; The first queue and the second queue are compared to obtain newly added chip port information and / or deleted chip port information.

3. The chip port correction method according to claim 2, characterized in that: The method further comprises: Read the port name of the chip port information; If the port name contains a test port identifier, marking the chip port information as belonging to the test port; If the port name does not contain a test port identifier, the chip port information is marked as belonging to the functional port.

4. The chip port correction method according to claim 2, characterized in that: The step of comparing the first queue and the second queue to obtain newly added chip port information and / or deleted chip port information includes: Create a newly added queue, an unchanged queue and a deleted queue, the newly added queue is used to store the newly added chip port information belonging to the target port direction and the target port type, the deleted queue is used to store the deleted chip port information belonging to the target port direction and the target port type, the unchanged queue is used to store the unchanged chip port information belonging to the target port direction and the target port type, and the unchanged chip port information is the chip port information existing in both the first chip design file and the second chip design file; Add the chip port information existing in both the first queue and the second queue to the unchanged queue, and delete the chip port information existing in both the first queue and the second queue in the second queue; Add chip port information that exists in the first queue but does not exist in the second queue to the newly added queue; The remaining chip port information in the second queue is added to the deletion queue.

5. The chip port correction method according to claim 4, characterized in that: The step of adding the newly added chip port information to the second chip design file includes: Add the chip port information existing in the newly added queue to the second chip design file; The step of deleting the deleted chip port information in the second chip design file includes: The chip port information existing in the deletion queue is deleted in the second chip design file.

6. The chip port correction method according to claim 1, characterized in that: The step of adding the newly added chip port information to the second chip design file also includes: Adding a port connection identifier corresponding to the newly added chip port information to the second chip design file according to a preset format; Setting the port connection identifier corresponding to the newly added chip port information belonging to the functional port as the target identifier, wherein the target identifier is used to represent the connection line connected to the chip port corresponding to the newly added chip port information; Set the port connection identifier corresponding to the newly added chip port information belonging to the input direction and the test port to the default identifier; The port connection mark corresponding to the newly added chip port information belonging to the output direction and the test port is set to a suspended mark, and the suspended mark is used to indicate that the chip port corresponding to the newly added chip port information is not connected to the connection line.

7. The chip port correction method according to claim 4, characterized in that: The method further comprises: Detecting the newly added queue; If the newly added queue includes chip port information belonging to a functional port, the operation control flag is set to a first flag, where the first flag is used to indicate that chip simulation is not performed; If the newly added queue does not include chip port information belonging to the functional port, the operation control flag is set to a second flag, and the second flag is used to indicate that chip simulation is being performed.

8. The chip port correction method according to claim 7, characterized in that: The method further comprises: Reading the operation control identifier; If the operation control identifier is the first identifier, the control verification system does not perform chip simulation; If the operation control identifier is the second identifier, the control verification system uses the chip design file to perform chip simulation.

9. A chip port correction device, characterized in that: It includes parameter parser, file parser, port checker and port corrector; among them: The parameter parser is used to obtain a first chip design file and a second chip design file, where the second chip design file is a chip design file of a previous version of the first chip design file; The file parser is used to parse the chip port information in the first chip design file and the chip port information in the second chip design file; The port checker is used to compare the chip port information in the first chip design file with the chip port information in the second chip design file to obtain newly added chip port information and / or deleted chip port information; the newly added chip port information is the chip port information that exists in the first chip design file and does not exist in the second chip design file, and the deleted chip port information is the chip port information that does not exist in the first chip design file and exists in the second chip design file; The port modifier is used to add the newly added chip port information in the second chip design file, and / or delete the deleted chip port information in the second chip design file.

10. The chip port correction device according to claim 9, characterized in that: Also included is an operation controller; wherein: The port modifier is used to set the operation control flag to a first flag when the newly added chip port information belonging to the functional port exists, and the first flag is used to indicate that chip simulation is not performed; when the newly added chip port information belonging to the functional port does not exist, the operation control flag is set to a second flag, and the second flag is used to indicate that chip simulation is performed; The operation controller is used to read the operation control identifier; If the operation control identifier is the first identifier, the control verification system does not perform chip simulation; If the operation control identifier is the second identifier, the control verification system uses the chip design file to perform chip simulation.

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