Epitaxial process method

Abstract

The invention provides an epitaxial process method, which is characterized in that a doped epitaxial layer is formed by adopting an embedded epitaxial process; a first element in the first element doping gas and a second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form a doped epitaxial layer, so that not only can a hole be formed in the intrinsic epitaxial layer, but also the hole can be formed in the third element deposition gas. The solid solubility of the first element doping gas is higher than that of the second element doping gas in the fourth element deposition gas, and the solid solubility of the second element doping gas is higher than that of the first element doping gas in the fourth element deposition gas, so that mutually compensated doping is formed in the intrinsic epitaxial layer, the carrier concentration of a hole is improved, and the contact resistivity of the doped epitaxial layer is reduced; therefore, the contact resistance between the source electrode and the substrate is reduced, namely, the contact resistance between the source electrode and the drain electrode of the MOSFET device and the substrate is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an epitaxial process method. Background Art

[0002] Currently, the semiconductor manufacturing industry mainly grows devices on wafers with a silicon (Si) substrate. For example, metal-oxide-semiconductor field-effect transistor (MOSFET) devices can be divided into p-type metal-oxide-semiconductor field-effect transistors (PMOS) and n-type metal-oxide-semiconductor field-effect transistors (NMOS) according to different types of ion implantation. For many years, along the path provided by Moore's Law, MOSFETs have been scaled down proportionally to increase device speed. However, as the size of MOSFETs shrinks, conventional proportional scaling methods have encountered a series of problems centered around the short-channel effect. For example, the problem of how to increase the drive current density while proportionally reducing the power supply voltage to reduce dynamic power consumption. Therefore, how to improve carrier mobility has become the key to maintaining the performance of MOSFETs. Since the average mobility of holes in a non-strained silicon substrate is three times lower than that of electrons, improving the hole mobility in the conductive channel of PMOS has become the focus of attention.

[0003] In recent years, strain engineering technology has been considered one of the key technologies to extend Moore's Law. The so-called strain technology is to introduce local unidirectional tensile or compressive stress into the conductive channel of MOSFETs to enhance the carrier mobility in the conductive channel of MOSFETs, so that the drive current can increase significantly when the thickness of the gate dielectric layer becomes thinner or remains unchanged, and finally improve the device performance of MOSFETs. For the conductive channel in a silicon substrate, available structures that can generate local unidirectional strain include boron-doped silicon germanium semiconductor (SiGeB) and boron-doped silicon carbide (SiCB), etc. Structures with local unidirectional strain must be designed separately for PMOS and NMOS. Currently, the strain engineering technologies that have been applied mainly include: depositing a tensile or compressive stress silicon nitride (SiN) capping layer, adding a tensile or compressive stress oxide layer in the shallow trench isolation and pre-metal dielectric structure, and epitaxial layer filling etching or elevated source and drain regions such as SiGeB.

[0004] Using epitaxial layers such as SiGeB to fill and etch the source and drain regions is a widely used strain engineering technique. In this method, the source and drain on both sides of the gate in the PMOS device structure are first partially etched away, and then an epitaxial layer such as SiGeB is grown over the etched source and drain regions by selective epitaxial growth. The compressive stress introduced by the SiGeB epitaxial layer is conducted to the conductive channel of the MOSFET, ultimately increasing the hole mobility in the PMOS. The epitaxial layer such as SiGeB is highly doped with element B during the epitaxial process to reduce the contact resistance of the epitaxial layer such as SiGe. However, it is difficult for the existing epitaxial process to further increase the doping concentration to reduce the contact resistance. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an epitaxial process method to solve the problem that it is difficult for the existing epitaxial process to reduce the contact resistance of the source and drain of MOSFET devices by further increasing the doping concentration.

[0006] To achieve the above purpose and other related purposes, the present invention provides an epitaxial process method, which includes:

[0007] Providing a substrate having a region where a source and / or a drain are to be formed;

[0008] Forming a doped epitaxial layer on the region where the source and / or the drain are to be formed by using an embedded epitaxial process. Among them, the reaction source gas for forming the doped epitaxial layer includes a doping gas and an epitaxial deposition gas. The doping gas includes a first element doping gas and a second element doping gas, and the epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing the constituent elements of the intrinsic epitaxial layer. In the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form the doped epitaxial layer, and in the third element deposition gas, the solubility of the first element doping gas is higher than that of the second element doping gas, and in the fourth element deposition gas, the solubility of the second element doping gas is higher than that of the first element doping gas.

[0009] Optionally, the epitaxial deposition gas includes a high-order silane gas, and the third element included in the third element deposition gas is silicon.

[0010] Further, the higher-order silane gas is disilane gas, and in the embedded epitaxial process, the flow rate of the disilane gas is 3000 sccm to 10000 sccm; or the higher-order silane gas is trisilane gas, and in the embedded epitaxial process, the flow rate of the trisilane gas is 1000 sccm to 6000 sccm; or the higher-order silane gas is tetrasilane gas, and in the embedded epitaxial process, the flow rate of the tetrasilane gas is 700 sccm to 3000 sccm; or the higher-order silane gas is a mixed gas of disilane gas and trisilane gas, and in the embedded epitaxial process, the flow rate of the mixed gas is 500 sccm to 1500 sccm, and the flow rate ratio of the disilane gas to the trisilane gas is the same.

[0011] Further, the pressure parameter adopted in the embedded epitaxial process is 0.1 mTorr to 1 Torr.

[0012] Further, the temperature parameter adopted in the embedded epitaxial process is 400 °C to 500 °C.

[0013] Further, the first element in the first element doping gas and the second element in the second element doping gas are different group III elements.

[0014] Further, the first element doping gas is BH 2 H 6 , the second element doping gas is GaH 4 , the fourth element included in the fourth element deposition gas is P or C, and the formed doped epitaxial layer is Si (1-x) P x :B:Ga layer or Si (1-y) C y :B:Ga layer.

[0015] Further, the first element doping gas is BH 2 H 6 , the second element doping gas is GaH 4 , the fourth element included in the fourth element deposition gas is Ge, and the formed doped epitaxial layer is Si (1-z) Ge z :B:Ga layer, where 0.1 ≤ z ≤ 0.5.

[0016] Further, the average activation concentration of B in the doped epitaxial layer is 1×10 20 cm -3 ~1×10 21 cm -3 , the average activation concentration of Ga is 1×10 20 cm -3 ~1×1022 cm -3 The contact resistivity between the doped epitaxial layer and the substrate is 1×10 -11 Ω·cm 2 ~9×10 -10 Ω·cm 2 。

[0017] Optionally, the substrate is an Si-based substrate, a GaN-based substrate or a diamond-based substrate.

[0018] As described above, in the epitaxial process method of the present invention, a doped epitaxial layer is formed on the region where the source electrode to be formed and / or the drain electrode to be formed by using the embedded epitaxial process. Among them, the reaction source gases for forming the doped epitaxial layer include a doping gas and an epitaxial deposition gas. The doping gas includes a first element doping gas and a second element doping gas. The epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing the composition of the intrinsic epitaxial layer. In the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form a doped epitaxial layer. Not only can holes be formed in the intrinsic epitaxial layer, but also the solubility of the first element doping gas in the third element deposition gas is higher than that of the second element doping gas, and the solubility of the second element doping gas in the fourth element deposition gas is higher than that of the first element doping gas. The characteristics of mutual compensation doping are formed in the intrinsic epitaxial layer, the carrier concentration of holes is increased, the contact resistivity of the doped epitaxial layer is reduced, and thus the contact resistance between it and the substrate is reduced, that is, the contact resistance between the source and drain of the MOSFET device and the substrate is reduced, solving the problem that it is difficult to further reduce the source and drain contact resistance by increasing the doping concentration in the existing epitaxial process. Description of the Drawings

[0019] Figure 1 It shows a schematic flow chart of the epitaxial process method of the present invention. Detailed Embodiments

[0020] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please refer to Figure 1It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0022] This embodiment provides an epitaxial process method. As Figure 1 shown, the epitaxial process method includes:

[0023] S1, providing a substrate, where a region for forming a source electrode to be formed and / or a drain electrode to be formed is provided on the substrate;

[0024] S2, forming a doped epitaxial layer on the region for forming a source electrode to be formed and / or a drain electrode to be formed by using an embedded epitaxial process. Among them, the reaction source gas for forming the doped epitaxial layer includes a doping gas and an epitaxial deposition gas. The doping gas includes a first element doping gas and a second element doping gas. The epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing the composition of the intrinsic epitaxial layer. In the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form the doped epitaxial layer, and in the third element deposition gas, the solubility of the first element doping gas is higher than that of the second element doping gas, and in the fourth element deposition gas, the solubility of the second element doping gas is higher than that of the first element doping gas.

[0025] The epitaxial process method of this embodiment forms a doped epitaxial layer on the region where the source electrode to be formed and / or the drain electrode to be formed by using an embedded epitaxial process. Among them, the reaction source gas for forming the doped epitaxial layer includes a doping gas and an epitaxial deposition gas. The doping gas includes a first element doping gas and a second element doping gas, and the epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing the constituent intrinsic epitaxial layer. In the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form a doped epitaxial layer, which can not only form holes in the intrinsic epitaxial layer, but also utilize the characteristics that the solubility of the first element doping gas is higher than that of the second element doping gas in the third element deposition gas and the solubility of the second element doping gas is higher than that of the first element doping gas in the fourth element deposition gas to form mutually compensated doping in the intrinsic epitaxial layer, improve the carrier concentration of holes, reduce the contact resistivity of the doped epitaxial layer, and further reduce the contact resistance between it and the substrate, that is, reduce the contact resistance between the source electrode and the drain electrode of the MOSFET device and the substrate, and solve the problem that it is difficult to further reduce the source electrode and drain electrode contact resistance by increasing the doping concentration in the existing epitaxial process.

[0026] As an example, the substrate can be a Si-based substrate, a gallium nitride (GaN)-based substrate, or a diamond-based substrate, and the material of the substrate can be selected according to actual needs and will not be overly restricted here.

[0027] As an example, the epitaxial deposition gas includes a high-order silane gas, and the third element included in the third element deposition gas is silicon. It should be noted here that the high-order silane is relative to the commonly used silane (SiH 4 ) in the prior art. Compared with SiH 4 , the high-order silane has a lower decomposition temperature and a faster deposition rate, which can accelerate the growth of the epitaxial layer and improve the utilization rate of the silicon source.

[0028] Furthermore, when using the high-order silane gas as the silicon source for epitaxial growth, in order to improve the film formation quality of the doped epitaxial layer and increase the doping concentration, the high-order silane gas can be, for example, disilane gas (Si 2 H 6 ), and the flow rate of the disilane gas can be set to 3000 sccm to 10000 sccm. For example, the flow rate of the disilane gas can be controlled to be 3000 sccm, 5000 sccm, 8000 sccm, or 10000 sccm.

[0029] The high-order silane gas can also be, for example, trisilane gas (Si 3 H 8) The flow rate of the trisilane gas can be set to 1000 sccm to 6000 sccm. For example, the flow rate of the trisilane gas can be controlled to be 1000 sccm, 2000 sccm, 3000 sccm, 5000 sccm, or 6000 sccm.

[0030] The higher-order silane gas can also be, for example, tetrasilane gas (Si 4 H 10 ). The flow rate of the tetrasilane gas can be set to 700 sccm to 3000 sccm. For example, the flow rate of the tetrasilane gas can be controlled to be 700 sccm, 800 sccm, 1000 sccm, 2000 sccm, 2800 sccm, or 3000 sccm.

[0031] The higher-order silane gas can also be, for example, a mixed gas of disilane gas and trisilane gas. The flow rate of the mixed gas can be set to 500 sccm to 1500 sccm, and the flow rate ratio of the disilane gas to the trisilane gas is the same.

[0032] Furthermore, when using the higher-order silane gas as the silicon source for epitaxial growth, in order to make the higher-order silane gas suitable for epitaxial growth, it needs to be carried out under ultra-low pressure process conditions. The pressure parameter used in the embedded epitaxial process is, for example, 0.1 mTorr to 1 Torr. In order to adapt to the ultra-low pressure process conditions and make the higher-order silane gas easier to decompose, the temperature parameter used in the embedded epitaxial process can be set to 400 °C to 500 °C.

[0033] In the epitaxial reaction, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas. This can not only form holes in the intrinsic epitaxial layer but also utilize the characteristics that the solubility of the first element doping gas is higher than that of the second element doping gas in the third element deposition gas and the solubility of the second element doping gas is higher than that of the first element doping gas in the fourth element deposition gas to form mutually compensating doping in the intrinsic epitaxial layer, increase the concentration of hole carriers, reduce the contact resistivity of the doped epitaxial layer, and thus reduce the contact resistance between it and the substrate. As an example, the third element is the commonly used silicon element, the first element in the first element doping gas and the second element in the second element doping gas are different group III elements. The first element doping gas can be, for example, borane (B 2 H 6 ), and the second element doping gas can be, for example, gallane (GaH 4), the fourth element included in the fourth element deposition gas is phosphorus (P) or carbon (C), and the doped epitaxial layer formed is Si (1-x) P x :B:Ga layer or Si (1-y) C y :B:Ga layer.

[0034] It should be noted here that: Si (1-x) P x :B:Ga, as a chemical representation method, is a boron and gallium co-doped silicon phosphorus (SiP) semiconductor material, where x refers to the molar fraction of P in SiP; Si (1-y) C y :B:Ga is a boron and gallium co-doped silicon carbide (SiC) semiconductor material, where y refers to the molar fraction of C in SiC.

[0035] As another specific example, the first element doping gas is B 2 H 6 , the second element doping gas is GaH 4 , the fourth element included in the fourth element deposition gas is Ge, and the doped epitaxial layer formed is Si (1-z) Ge z :B:Ga layer, where 0.1 ≤ z ≤ 0.5. It should be noted here that Si (1-z) Ge z :B:Ga represents a boron and gallium co-doped silicon germanium (SiGe) semiconductor material, where z refers to the molar fraction of Ge in SiGe.

[0036] As an example, when the disilane gas (Si 2 H 6 ) is selected as the third element deposition gas and germane (GeH 4 ) is selected as the fourth element deposition gas, the epitaxial reaction formula of the embedded epitaxial process is:

[0037] Si 2 H 6 +GeH 4 +B 2 H 6 +GaH 4 →Si (1-z) Ge z :B:Ga↓+H 2 ↑

[0038] And when performing the embedded epitaxial process, the pressure parameter is set to 0.1 mTorr to 1 Torr, and the temperature parameter is set to 400 °C to 500 °C. As an example, the formed Si (1-z) Gez : In the B:Ga layer, the average activation concentration of B is 1×10 20 cm -3 ~1×10 21 cm -3 , and the average activation concentration of Ga is 1×10 20 cm -3 ~1×10 22 cm -3 , and the contact resistivity between the Si (1-z) Ge z :B:Ga layer and the substrate is, for example, 1×10 -11 Ω·cm 2 ~9×10 -10 Ω·cm 2 .

[0039] Preferably, in this embodiment, by controlling the flow rate of the reaction gas, z is equal to 0.5, that is, doping is carried out on the basis of a higher molar concentration of Ge, and the formed Si 0.5 Ge 0.5 : In the B:Ga layer, the average activation concentration of B is 9×10 20 cm -3 , the average activation concentration of Ga is 3×10 20 cm -3 , and the contact resistivity between the formed Si 0.5 Ge 0.5 :B:Ga layer and the substrate is 3.2×10 -10 Ω·cm 2 .

[0040] When the embedded epitaxial process is carried out, by using the solubility of the first element doping gas (B 2 H 6 ) in the third element deposition gas (Si 2 H 6 ) being higher than that of the second element doping gas (GaH 4 ), therefore, during the deposition of the third element (Si) included in the third element deposition gas, the first element (B) in the first element doping gas is more likely to dissolve and be doped into the intrinsic epitaxial layer (SiGe); in the fourth element deposition gas (GeH 4 ), the solubility of the second element doping gas (GaH 4 ) is higher than that of the first element doping gas (B 2 H 6), therefore, during the deposition of the fourth element (Ge) included in the fourth element deposition gas, the second element (Ga) in the second element doping gas is more likely to dissolve and dope into the intrinsic epitaxial layer (SiGe). Therefore, through the doping method of mutual compensation of the first element (B) in the first element doping gas and the second element (Ga) in the second element doping gas, the doping concentration of acceptor co-doping can be maximally increased, thereby increasing the concentration of hole carriers and reducing the 0.5 Ge 0.5 contact resistivity of the :B:Ga layer, and further reducing the contact resistance between it and the substrate.

[0041] In summary, in the epitaxial process method of the present invention, a doped epitaxial layer is formed on the region where the source electrode to be formed and / or the drain electrode to be formed by using an embedded epitaxial process. Among them, the reaction source gas for forming the doped epitaxial layer includes a doping gas and an epitaxial deposition gas. The doping gas includes a first element doping gas and a second element doping gas, and the epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing the components of the intrinsic epitaxial layer. In the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form a doped epitaxial layer. It can not only form holes in the intrinsic epitaxial layer, but also utilize the characteristics that the solubility of the first element doping gas is higher than that of the second element doping gas in the third element deposition gas, and the solubility of the second element doping gas is higher than that of the first element doping gas in the fourth element deposition gas to form mutually compensated doping in the intrinsic epitaxial layer, increase the carrier concentration of holes, reduce the contact resistivity of the doped epitaxial layer, and further reduce the contact resistance between it and the substrate, that is, reduce the contact resistance between the source electrode and the drain electrode of the MOSFET device and the substrate, and solve the problem that it is difficult to further reduce the source electrode and drain electrode contact resistance by increasing the doping concentration in the existing epitaxial process. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0042] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An epitaxial process method, characterized in that: The epitaxial process method comprises: Providing a substrate having a region where a source electrode and / or a drain electrode is to be formed; An embedded epitaxial process is used to form a doped epitaxial layer on the region where a source and / or a drain is to be formed, wherein the reaction source gas for forming the doped epitaxial layer includes a doping gas and an epitaxial deposition gas, the doping gas includes a first element doping gas and a second element doping gas, the epitaxial deposition gas includes a third element deposition gas and a fourth element deposition gas for introducing an intrinsic epitaxial layer, and in the embedded epitaxial process, the first element in the first element doping gas and the second element in the second element doping gas perform acceptor co-doping on the third element deposition gas and the fourth element deposition gas to form the doped epitaxial layer, and in the third element deposition gas, the solid solubility of the first element doping gas is higher than that of the second element doping gas, and in the fourth element deposition gas, the solid solubility of the second element doping gas is higher than that of the first element doping gas.

2. The epitaxial process method according to claim 1, characterized in that: The epitaxial deposition gas includes a high-order silane gas, and the third element included in the third element deposition gas is silicon.

3. The epitaxial process method according to claim 2, characterized in that: The high-order silane gas is disilane gas, and in the embedded epitaxial process, the flow rate of the disilane gas is 3000sccm~10000sccm; or the high-order silane gas is trisilane gas, and in the embedded epitaxial process, the flow rate of the trisilane gas is 1000sccm~6000sccm; or the high-order silane gas is butasilane gas, and in the embedded epitaxial process, the flow rate of the butasilane gas is 700sccm~3000sccm; or the high-order silane gas is a mixed gas of disilane gas and trisilane gas, and in the embedded epitaxial process, the flow rate of the mixed gas is 500sccm~1500sccm, and the flow ratio of the disilane gas and the trisilane gas is the same.

4. The epitaxial process method according to claim 2, characterized in that: The pressure parameter adopted by the embedded epitaxial process is 0.1 mTorr to 1 Torr.

5. The epitaxial process method according to claim 2, characterized in that: The temperature parameter adopted by the embedded epitaxial process is 400°C to 500°C.

6. The epitaxial process method according to claim 2, characterized in that: The first element in the first element doping gas and the second element in the second element doping gas are different Group III elements.

7. The epitaxial process method according to claim 6, characterized in that: The first element doping gas is B2H6, the second element doping gas is GaH4, the fourth element included in the fourth element deposition gas is P or C, and the formed doped epitaxial layer is Si (1-x) P x :B:Ga layer or Si (1-y) C y :B:Ga layer.

8. The epitaxial process method according to claim 6, characterized in that: The first element doping gas is B2H6, the second element doping gas is GaH4, the fourth element included in the fourth element deposition gas is Ge, and the formed doped epitaxial layer is Si (1-z) Ge z :B:Ga layer, where 0.1≤z≤0.

5.

9. The epitaxial process method according to claim 8, characterized in that: The average activation concentration of B in the doped epitaxial layer is 1×10 20 cm -3 ~1×10 21 cm -3 The average activation concentration of Ga is 1×10 20 cm -3 ~1×10 22 cm -3 The contact resistivity between the doped epitaxial layer and the substrate is 1×10 -11 Ω·cm 2 ~9×10 -10 Ω·cm 2 .

10. The epitaxial process method according to claim 1, characterized in that: The substrate is a Si-based substrate, a GaN-based substrate or a diamond-based substrate.

Images