Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: forming a first metal wire and a second metal wire located at one side of the first metal wire in a first interlayer dielectric layer, and then carrying out the back etching to remove a part of thickness of the second metal wire, the top surface of the second metal wire is lower than the top surface of the first metal wire; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer; an opening is formed in the second interlayer dielectric layer, the opening crosses over part of the first metal wire and part of the second metal wire, and part of the bottom of the opening is exposed out of part of the top surface of the first metal wire; and forming a third metal wire filling the opening. According to the method, the difficulty of the forming process of the opening is reduced, and the difficulty of filling metal in the opening is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the manufacturing process of very large scale integrated circuits (VLSIs), more than one layer of metal wiring is usually formed to realize the interconnection between devices.

[0003] With the continuous development of semiconductor process technology and the continuous reduction of device sizes, the process of ultra-large scale integrated circuits (ULSIs) has become increasingly complex, the sizes of the back-end metal wirings have also been continuously reduced, and metal growth filling has become increasingly difficult. Generally, the filling ability of metals is improved by continuously improving the filling ability of equipment. However, as the size continues to decrease, when the metal line width is less than 20 nm, traditional solutions become increasingly difficult, and improvement solutions need to be proposed from the overall process flow. Summary of the Invention

[0004] Based on this, this application provides a semiconductor structure and a method for manufacturing the same to reduce the formation difficulty and filling difficulty of openings.

[0005] In a first aspect, an embodiment of this application provides a method for manufacturing a semiconductor structure, including.

[0006] Providing a first interlayer dielectric layer, in which a first metal wire and a second metal wire located on one side of the first metal wire are formed, and the top surface of the second metal wire is lower than the top surface of the first metal wire, and the top surface of the first interlayer dielectric layer exposes at least the top surface of the first metal wire;

[0007] Forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer;

[0008] Forming an opening in the second interlayer dielectric layer, the opening spanning directly above a part of the first metal wire and a part of the second metal wire, and a part of the bottom surface of the opening exposes a part of the top surface of the first metal wire;

[0009] Forming a third metal wire that fills the opening.

[0010] In some embodiments of the present application, the formation process of the first metal wire and the second metal wire includes: providing a substrate; forming a first interlayer dielectric layer on the substrate; forming a first trench and a second trench located on one side of the first trench in the first interlayer dielectric layer; filling the first trench and the second trench with metal to form a first metal wire and a second initial metal wire; and back-etching to remove a part of the thickness of the second initial metal wire, and the remaining second initial metal wire is the second metal wire.

[0011] In some embodiments of the present application, a groove is formed at a corresponding position after back-etching to remove a part of the thickness of the second initial metal wire, and the second interlayer dielectric layer also fills the groove.

[0012] In some embodiments of the present application, the vertical distance between the top surface of the second metal wire and the top surface of the first metal wire is 1 / 3 - 2 / 3 of the height of the first metal wire.

[0013] In some embodiments of the present application, the opening is a single damascene opening or a dual damascene opening.

[0014] In some embodiments of the present application, the single damascene opening is a through hole or a trench.

[0015] In some embodiments of the present application, the dual damascene opening includes a trench and a through hole located below the trench and communicating with the trench.

[0016] In some embodiments of the present application, an anti-diffusion barrier layer is further formed between the third metal wire and the inner wall of the opening.

[0017] In some embodiments of the present application, the anti-diffusion barrier layer is formed by a sputtering process; the third metal wire layer is formed by an electroplating process.

[0018] Second, embodiments of the present application further provide a semiconductor structure, including:

[0019] A first interlayer dielectric layer having a first metal wire and a second metal wire located on one side of the first metal wire therein, and the top surface of the second metal wire is lower than the top surface of the first metal wire, and at least the top surface of the first metal wire is exposed on the top surface of the first interlayer dielectric layer;

[0020] A second interlayer dielectric layer located on the top surface of the first interlayer dielectric layer;

[0021] An opening located in the second interlayer dielectric layer, the opening straddles directly above a part of the first metal wire and a part of the second metal wire, and a part of the bottom of the opening exposes a part of the top surface of the first metal wire;

[0022] A third metal wire located within the opening and filling the opening.

[0023] The embodiments of the present application can / at least have the following advantages:

[0024] In the semiconductor structure and its forming method according to the embodiments of the present application, after forming a first metal wire and a second metal wire located on one side of the first metal wire in the first interlayer dielectric layer, a part of the second metal wire is removed by back-etching to make the top surface of the second metal wire lower than the top surface of the first metal wire; then a second interlayer dielectric layer is formed on the top surface of the first interlayer dielectric layer; an opening is formed in the second interlayer dielectric layer, the opening straddles directly above a part of the first metal wire and a part of the second metal wire, and a part of the top surface of the first metal wire is exposed at a part of the bottom of the opening; a third metal wire filling the opening is formed. Since the top surface of the second metal wire in the first interlayer dielectric layer is lower than the top surface of the first metal wire, when forming the third metal wire connected to the first metal wire in the first interlayer dielectric layer in the second interlayer dielectric layer, in the direction perpendicular to the top surface of the first interlayer dielectric layer, there is a certain distance between the bottom surface of the third metal wire and the top surface of the second metal wire, thereby making it not easy for a short circuit to occur between the bottom surface of the third metal wire and the top surface of the second metal wire and the parasitic capacitance between the third metal wire and the second metal wire can be relatively small. Therefore, when forming an opening corresponding to the third metal wire in the second interlayer dielectric layer, the opening can straddle directly above a part of the first metal wire and a part of the second metal wire, that is, under the same line width requirement (the size of the upper part of the opening), the size of the bottom of the opening can be larger than the size of the through hole in the existing damascene opening, thereby reducing the difficulty of the forming process of the opening and reducing the difficulty of filling the metal in the opening.

[0025] Details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0027] Figures 1-2 It is a schematic cross-sectional structure diagram of each stage in the preparation process of a semiconductor structure provided by the present application;

[0028] Figures 3-7 This is a schematic cross-sectional structure diagram of each stage in the preparation process of the semiconductor structure provided in some embodiments of the present application. Detailed implementation manners

[0029] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0031] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be referred to as the second element, component, region, layer or part.

[0032] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientations shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the drawing is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device may also have other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0033] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that terms such as "comprises / include" or "has" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0034] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations caused by, for example, manufacturing techniques.

[0035] It can be understood that in the drawings of the specification of this application, adjacent film layers with the same processed film layer material are drawn as connected to make it close to the actual structure.

[0036] Conventional back-end metal interconnections all adopt the method of vias plus trenches. When the line width is less than or equal to 90 nm, copper wire interconnections usually adopt the dual damascene structure of vias plus trenches. This solution can avoid short circuits between adjacent metal trenches and effectively reduce parasitic capacitance. However, this solution has high requirements for etching and metal filling manufacturing processes. Especially when the line width is continuously reduced, the situation becomes particularly severe. As the line width is reduced, it is difficult to etch the vias in the dual damascene structure, and it is also difficult to fill the vias with metal, and the challenges increase. Figures 1-2 It is a schematic cross-sectional structure diagram of each stage during the formation process of a semiconductor structure with a dual damascene structure for this application. Specifically, refer to Figure 1, a substrate 101 is provided; a first etch stop layer 102 and a first interlayer dielectric layer 106 are sequentially formed on the top surface of the substrate 101; a first metal wire 103 and a second metal wire 104 located on one side of the first metal wire 103 are formed in the first interlayer dielectric layer 106, and a first anti-diffusion barrier layer 105 is further formed between the first metal wire 103 and the first interlayer dielectric layer 106 and between the second metal wire 104 and the first interlayer dielectric layer 106; continue to refer to Figure 1 , a second etch stop layer 107 covering the first interlayer dielectric layer 106, the first metal wire 103 and the second metal wire 104 is formed; a second interlayer dielectric layer 108 is formed on the top surface of the second etch stop layer 107; the second interlayer dielectric layer 108 is etched to form a damascene opening 111 in the second interlayer dielectric layer 108, and the opening of the damascene opening 111 includes a trench 110 and a via 109 communicating with the bottom of the trench 110, and the via 109 exposes a part of the top surface of the first metal wire 103; refer to Figure 2 , the damascene opening 111 is filled with metal to form a third metal wire 112, and a second anti-diffusion barrier layer 113 may further be formed between the third metal wire 112 and the inner wall of the damascene opening 111. Since the distance between the formed first metal wire 103 and the second metal wire 104 is continuously decreasing, and since the line widths of the formed first metal wire 103 and the third metal wire are continuously decreasing, in order to avoid short circuit between the third metal wire 112 and the second metal wire 104 and effectively reduce the parasitic capacitance between the third metal wire 112 and the second metal wire 104, the size of the via 109 in the damascene opening 111 also needs to be continuously decreased, which makes the process difficulty of etching the via 109 increase, and when the size of the via 109 is small, the difficulty of filling the via 109 with metal will also increase.

[0037] To this end, the embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. After forming a first metal wire and a second metal wire located on one side of the first metal wire in a first interlayer dielectric layer, a part of the second metal wire with a certain thickness is removed by back etching, so that the top surface of the second metal wire is lower than the top surface of the first metal wire; then a second interlayer dielectric layer is formed on the top surface of the first interlayer dielectric layer; an opening is formed in the second interlayer dielectric layer, the opening straddles directly above a part of the first metal wire and a part of the second metal wire, and a part of the top surface of the first metal wire is exposed at a part of the bottom of the opening; a third metal wire is formed to fill the opening. Since the top surface of the second metal wire in the first interlayer dielectric layer is lower than the top surface of the first metal wire, when forming a third metal wire connected to the first metal wire in the first interlayer dielectric layer in the second interlayer dielectric layer, in the direction perpendicular to the top surface of the first interlayer dielectric layer, there is a certain distance between the bottom surface of the third metal wire and the top surface of the second metal wire, so that it is not easy for a short circuit to occur between the bottom surface of the third metal wire and the top surface of the second metal wire and the parasitic capacitance between the third metal wire and the second metal wire can be relatively small. Therefore, when forming an opening corresponding to the third metal wire in the second interlayer dielectric layer, the opening can straddle directly above a part of the first metal wire and a part of the second metal wire, that is, under the same line width requirement (the size of the upper part of the opening), the size of the bottom of the opening can be larger than the size of the through hole in the existing damascene opening, thereby reducing the difficulty of the opening forming process and reducing the difficulty of filling the metal in the opening.

[0038] The following describes in detail the specific process of the manufacturing method of the foregoing semiconductor structure with reference to the accompanying drawings. Figures 3-7 FIGS. are cross-sectional structure diagrams of each stage in the manufacturing process of a semiconductor structure provided by some embodiments of the present application.

[0039] Refer to Figure 3 and Figure 4 to provide a first interlayer dielectric layer 206, a first metal wire 203 and a second metal wire 204 located on one side of the first metal wire 203 are formed in the first interlayer dielectric layer 206, and the top surface of the second metal wire 204 is lower than the top surface of the first metal wire 203, and the top surface of the first interlayer dielectric layer 206 at least exposes the top surface of the first metal wire 203.

[0040] The first metal wire 203 and the second metal wire 204 are both part of the back-end metal wiring in integrated circuit fabrication. The second metal wire 204 is adjacent to the first metal wire 203. Specifically, the second metal wire 204 is located on one side of the first metal wire 203. In some embodiments, the second metal wire 204 and the first metal wire 203 may have a small spacing. In a specific example, the spacing between the second metal wire 204 and the first metal wire 203 is less than or equal to 90 nm, and the line width or feature size of the second metal wire 204 and the first metal wire 203 is also less than or equal to 90 nm. The first metal wire 203 and the second metal wire 204 can be electrically connected to different objects. In some embodiments, the first metal wire 203 and / or the second metal wire 204 can be electrically connected to other metal wires. In other embodiments, the first metal wire 203 and / or the second metal wire 204 can be electrically connected to semiconductor devices formed on the substrate. The second metal wire 204 and the first metal wire 203 can each be one or more. In this application, only one second metal wire 204 and one first metal wire 203 are used as examples for illustration.

[0041] In some embodiments, the formation process of the first metal wire 203 and the second metal wire 204 includes: referring to Figure 3 , providing a substrate 201; forming a first interlayer dielectric layer 206 on the substrate 201; forming a first trench (not labeled in the figure) and a second trench (not labeled in the figure) located on one side of the first trench in the first interlayer dielectric layer 206; filling the first trench and the second trench with metal to form the first metal wire 203 and the second initial metal wire 204a; referring to Figure 4 , performing a re-etching to remove a part of the thickness of the second initial metal wire 204a (referring to Figure 3 ), and the remaining second initial metal wire is the second metal wire 204. After performing a re-etching to remove a part of the thickness of the second initial metal wire 204a, a groove located in the first interlayer dielectric layer 206 is formed at the corresponding position.

[0042] In some embodiments, the substrate 201 includes a substrate. In other embodiments, the substrate 201 may include a substrate and an underlying dielectric layer on the top surface of the substrate. A plurality of semiconductor devices may be formed in the substrate, and an underlying metal interconnect structure may be formed in the underlying dielectric layer. In a specific example, the material of the substrate may include silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or it may also include other materials, such as group III-V compounds such as gallium arsenide. The substrate may also be implanted with certain doping ions according to design requirements to change electrical parameters. A shallow trench isolation structure (not shown in the figure) is also formed in the substrate, and the shallow trench isolation structure is used to isolate different semiconductor devices and prevent electrical connection between different semiconductor devices. The material of the shallow trench isolation structure may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In a specific example, the semiconductor devices include active devices and / or passive devices. The active devices include metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), field effect transistors (FETs), fin field-effect transistors (FinFETs), insulated-gate bipolar transistors (IGBTs), nanowire transistors, memory devices, or combinations thereof. The passive devices include diodes, resistors, capacitors, inductors, or combinations thereof.

[0043] The first interlayer dielectric layer 206 is used for electrical isolation between the first metal wire 203 and the second metal wire 204. In some embodiments, the first interlayer dielectric layer 206 includes a single layer or a multi-layer stacked structure. In some embodiments, the material of the first interlayer dielectric layer 206 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant (K less than 2.5) materials, or a combination thereof. The process for forming the first interlayer dielectric layer 206 includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDPCVD). In some embodiments, before forming the first interlayer dielectric layer 206, a first etch stop layer 102 is formed on the top surface of the substrate 101. The first etch stop layer 102 serves as a stop layer when etching the first interlayer dielectric layer 106 to form the first trench and the second trench, so as to improve the accuracy of etching. The material of the first etch stop layer 102 is different from the material of the first interlayer dielectric layer 106. The material of the first etch stop layer 102 includes one or several of silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbide.

[0044] In some embodiments, an anisotropic dry etching process is used to etch the first interlayer dielectric layer, and a first trench (not labeled in the figure) and a second trench (not labeled in the figure) located on one side of the first trench are formed in the first interlayer dielectric layer 206. The anisotropic dry etching process includes a plasma etching process. The plasma etching process uses an etching gas including a fluorine-containing gas, such as using CF 4 、CHF 3 、C 4 F 8 or C 4 F 6 or a combination of several of them, or using a mixed gas of any one of CF 4 、CHF 3 、C4F 8 and C 4 F 6 and any one of O 2 、Ar、CO and He.

[0045] The materials of the first metal wire 203 and the second metal wire 204 are metals, and the metals include one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni. Electroplating can be used to fill the first trench and the second trench with metal to form the first metal wire 203 and the second initial metal wire 204a. In some embodiments, a first anti-diffusion barrier layer 205 is further formed between the first metal wire 203 and the inner wall of the first trench and between the second initial metal wire 204a and the inner wall of the second trench. The first anti-diffusion barrier layer 205 is used to prevent the metal in the first metal wire 203 and the second metal wire 204 from diffusing into the dielectric layer (such as the first interlayer dielectric layer 206), thereby affecting the isolation performance of the dielectric layer. In a specific example, the material of the first anti-diffusion barrier layer 205 includes one or more of Ti, Ta, TiN, TaN, TaC, and WN, and the formation process of the first anti-diffusion barrier layer 205 includes sputtering.

[0046] In some embodiments, anisotropic dry etching is used to etch back a part of the thickness of the second initial metal wire 204a. The anisotropic dry etching process includes a plasma etching process, and the plasma etching process uses an etching gas including a chlorine-containing gas, such as Cl 2 or BCl 3 .

[0047] In this application, a part of the thickness of the second initial metal wire 204a is etched back to form the second metal wire 204, so that the top surface of the second metal wire 204 is lower than the top surface of the first metal wire 203. Therefore, when a third metal wire 210 (refer to Figure 7 ) connected to the first metal wire 203 in the first interlayer dielectric layer 206 is formed in the second interlayer dielectric layer 208 later, in the direction perpendicular to the top surface of the first interlayer dielectric layer 206, there is a certain distance between the bottom surface of the third metal wire 210 and the top surface of the second metal wire 204 formed in the first interlayer dielectric layer 206. Furthermore, it is not easy for a short circuit to occur between the bottom of the third metal wire 210 and the top surface of the second metal wire 204, and the parasitic capacitance between the third metal wire 210 and the second metal wire 204 can be relatively small. Therefore, when an opening 209 (refer to Figure 6When (), the opening 209 can span directly above a part of the first metal wire 203 and a part of the second metal wire 204. That is, under the same line width requirement (the size D1 of the upper part of the opening 209), the size D2 of the bottom of the opening 209 (D2 is less than or equal to D1) can be larger than the size of the through hole in the existing damascene opening, thereby reducing the difficulty of the process for forming the opening 209 and reducing the difficulty of filling the metal in the opening 209.

[0048] In one embodiment, the vertical distance from the top surface of the second metal wire 204 to the top surface of the first metal wire 203 is 1 / 3 - 2 / 3 of the height of the first metal wire 203.

[0049] Reference Figure 5 , a second interlayer dielectric layer 208 is formed on the top surface of the first interlayer dielectric layer 206.

[0050] Electrical isolation between the third metal wires formed subsequently in the second interlayer dielectric layer 208 and between the third metal wires and the first metal wire 203 and the second metal wire 204. The second interlayer dielectric layer 208 fills the groove formed after the second initial metal wire is etched back. In some embodiments, the second interlayer dielectric layer 208 includes a single layer or a multi-layer stacked structure. In some embodiments, the material of the second interlayer dielectric layer 208 includes silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), a low dielectric constant (K less than 2.5) material or a combination thereof. The process for forming the second interlayer dielectric layer 208 includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD). In some embodiments, before forming the second interlayer dielectric layer 208, a second etch stop layer 207 is formed on the top surface of the first interlayer dielectric layer 206. The second etch stop layer 207 serves as a stop layer when etching the second interlayer dielectric layer 208 to form the opening subsequently, so as to improve the accuracy of etching. The material of the second etch stop layer 207 is different from the material of the second interlayer dielectric layer 208. The material of the second etch stop layer 207 includes one or several of silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride.

[0051] Reference Figure 6, an opening 209 is formed in the second interlayer dielectric layer 208, the opening 209 straddles directly above a part of the first metal wire 203 and a part of the second metal wire 204, and a part of the top surface of the first metal wire 203 is exposed at a part of the bottom of the opening 209.

[0052] A third metal wire is subsequently formed in the opening 209.

[0053] The opening 209 can be a single damascene opening or a dual damascene opening. In some embodiments, the single damascene opening is a via or a trench. In some embodiments, the dual damascene opening 209 includes a trench and a via located below the trench and communicating with the trench.

[0054] In some embodiments, the second interlayer dielectric layer 208 is etched using an anisotropic dry etching process to form the opening 209 in the second interlayer dielectric layer 208. The anisotropic dry etching process includes a plasma etching process, and the plasma etching process uses an etching gas including a fluorine-containing gas, such as using CF 4 , CHF 3 , C 4 F 8 or C 4 F 6 or a combination of one or more of them, or using a mixed gas of any one of CF 4 , CHF 3 , C4F 8 and C 4 F 6 and any one gas of O 2 , Ar, CO, and He.

[0055] Reference Figure 7 , a third metal wire 210 that fills the opening 209 (reference Figure 6 ) is formed.

[0056] The material of the third metal wire 210 is metal, and the metal includes one or more of Cu, W, Al, Ti, Ag, Au, Pt, and Ni. Electroplating can be used to fill the opening 209 with metal to form the third metal wire 210. In some embodiments, a second anti-diffusion barrier layer 211 is further formed between the third metal wire 210 and the inner wall of the opening 209. The second anti-diffusion barrier layer 211 is used to prevent the metal in the third metal wire 210 from diffusing into the dielectric layer (such as the second interlayer dielectric layer 208), thereby affecting the isolation performance of the dielectric layer. In a specific example, the material of the second anti-diffusion barrier layer 211 includes one or more of Ti, Ta, TiN, TaN, TaC, and WN, and the formation process of the second anti-diffusion barrier layer 211 includes sputtering.

[0057] The embodiment of the present application also provides a semiconductor structure. Referring to Figure 7 , it includes:

[0058] The first interlayer dielectric layer 206, in which there are a first metal wire 203 and a second metal wire 204 located on one side of the first metal wire 203, and the top surface of the second metal wire 204 is lower than the top surface of the first metal wire 203, and the top surface of the first interlayer dielectric layer 206 at least exposes the top surface of the first metal wire 203;

[0059] The second interlayer dielectric layer 208 located on the top surface of the first interlayer dielectric layer 206;

[0060] An opening 209 located in the second interlayer dielectric layer 208, the opening 209 straddles directly above a part of the first metal wire 203 and a part of the second metal wire 204, and a part of the bottom of the opening 209 exposes a part of the top surface of the first metal wire 203;

[0061] A third metal wire 210 located in the opening 209 and filling the opening 209.

[0062] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0063] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0064] The above embodiments only represent several implementation manners of the present application. The descriptions are relatively specific and detailed, but they should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a first interlayer dielectric layer, wherein a first metal wire and a second metal wire located on one side of the first metal wire are formed in the first interlayer dielectric layer, and a top surface of the second metal wire is lower than a top surface of the first metal wire, and a top surface of the first interlayer dielectric layer at least exposes a top surface of the first metal wire; forming a second interlayer dielectric layer on the top surface of the first interlayer dielectric layer; forming an opening in the second interlayer dielectric layer, the opening spanning directly above a portion of the first metal wire and a portion of the second metal wire, and a portion of the bottom of the opening exposing a portion of the top surface of the first metal wire; A third metal conductive line is formed to fill the opening.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The formation process of the first metal wire and the second metal wire includes: providing a substrate; forming a first interlayer dielectric layer on the substrate; forming a first groove and a second groove located on one side of the first groove in the first interlayer dielectric layer; filling the first groove and the second groove with metal to form a first metal wire and a second initial metal wire; etching back to remove a portion of the thickness of the second initial metal wire, and the remaining second initial metal wire is the second metal wire.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: A groove is formed at a corresponding position after a portion of the thickness of the second initial metal wire is removed by etching back, and the second interlayer dielectric layer also fills the groove.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The vertical distance that the top surface of the second metal wire is lower than the top surface of the first metal wire is 1 / 3-2 / 3 of the height of the first metal wire.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The opening is a single damask opening or a double damask opening.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The single damask opening is a through hole or a groove.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that: The dual damascene opening includes a groove and a through hole located below the groove and communicating with the groove.

8. The method for preparing a semiconductor structure according to claim 1 or 5, characterized in that: An anti-diffusion barrier layer is also formed between the third metal wire and the inner wall of the opening.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The anti-diffusion barrier layer is formed by a sputtering process; and the third metal wire layer is formed by an electroplating process.

10. A semiconductor structure, characterized in that: include: A first interlayer dielectric layer, wherein the first interlayer dielectric layer has a first metal wire and a second metal wire located on one side of the first metal wire, wherein a top surface of the second metal wire is lower than a top surface of the first metal wire, and a top surface of the first interlayer dielectric layer at least exposes a top surface of the first metal wire; a second interlayer dielectric layer located on a top surface of the first interlayer dielectric layer; an opening in the second interlayer dielectric layer, the opening spanning directly above a portion of the first metal wire and a portion of the second metal wire, and a portion of the bottom of the opening exposing a portion of the top surface of the first metal wire; A third metal conductive line is located in the opening and completely fills the opening.

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