Chip package transition structure, integrated antenna module, and communication device

Abstract

The application relates to a chip packaging transition structure, an integrated antenna module and a communication device. The chip packaging transition structure comprises a chip, a rewiring layer, a fan-out packaging structure of a first solder ball and a plurality of second solder balls, a first end of a first signal line of the rewiring layer is connected with a signal lead-out end of the chip, a first ground part is connected with a ground lead-out end of the chip, a first interval is arranged between the first signal line and the first ground part, and the first ground part is arranged around the first signal line; a first printed circuit board comprising a feed line layer, a second end of the first signal line is connected with a first end of a second signal line of the feed line layer through the first solder ball, the first ground part is connected with a second ground part of the feed line layer through the plurality of second solder balls, a second interval is arranged between the second signal line and the second ground part, and the second ground part is arranged around the second signal line; and the plurality of second solder balls are distributed around the second signal line and are provided with openings at positions corresponding to the first solder ball. Low transmission loss can be achieved by adopting the structure.

Description

Technical Field

[0001] This application relates to the field of microelectronic packaging interconnect technology, and in particular to a chip packaging transition structure, an integrated antenna module, and a communication device. Background Technology

[0002] With the significant increase in communication system frequencies, the integration of radio frequency antennas and radio frequency chips has become a technological trend. Fan-out wafer-level packaging (FOWLP) technology can integrate chips and antennas into the same package, enabling mass production through wafer-level packaging.

[0003] When a fan-out wafer-level package structure interconnects with an external structure, the chip's pads are directly connected to external signal transmission lines via metallized vias, or directly connected to external signal transmission lines via solder balls on the chip package structure.

[0004] However, the above interconnection methods suffer from high transmission loss. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip packaging transition structure, integrated antenna module, and communication device that can reduce transmission loss in order to address the above-mentioned technical problems.

[0006] In a first aspect, a chip packaging transition structure is provided, comprising: a fan-out packaging structure and a first printed circuit board, wherein...

[0007] The fan-out package structure includes a chip, a redistribution layer, a first solder ball, and a plurality of second solder balls. The first end of the first signal line of the redistribution layer is connected to the signal lead of the chip, and the first ground part of the redistribution layer is connected to the ground lead of the chip. A first gap is provided between the first signal line and the first ground part, and the first ground part is arranged around the first signal line.

[0008] The first printed circuit board includes a feed line layer, the second end of the first signal line is connected to the first end of the second signal line of the feed line layer through the first solder ball, the first ground part is connected to the second ground part of the feed line layer through a plurality of second solder balls, a second interval is provided between the second signal line and the second ground part, and the second ground part is arranged around the second signal line;

[0009] Multiple second solder balls are distributed around the second signal line and have openings at the positions corresponding to the first solder balls.

[0010] In one embodiment, the first printed circuit board further includes a first dielectric layer and a first ground layer;

[0011] The first dielectric layer is disposed on the side of the feeder layer away from the rewiring layer, and the first ground layer is disposed on the side of the first dielectric layer away from the feeder layer; a plurality of first metallized vias are disposed in the area of ​​the first dielectric layer corresponding to the second ground portion, and the first metallized vias are used to provide a conductive path between the feeder layer and the first ground layer.

[0012] In one embodiment, the chip package transition structure further includes a second printed circuit board and a rectangular waveguide, wherein,

[0013] The feeder layer is provided with a first transmission window, which is set around the second end of the second signal line, and the first transmission window and the second interval form a connected region;

[0014] The first ground plane of the first printed circuit board is provided with a second transmission window;

[0015] The second printed circuit board is provided with a third transmission window that runs through the second printed circuit board, and the sidewalls of the third transmission window are made of metal.

[0016] The second transmission window, the third transmission window, and the rectangular waveguide form a waveguide interconnection structure.

[0017] In one embodiment, the chip packaging transition structure further includes a cured wafer layer;

[0018] One side of the cured sheet is connected to the first printed circuit board, and the other side of the cured sheet is connected to the second printed circuit board; the cured sheet is provided with a fourth transmission window, which, together with the second transmission window, the third transmission window, and the rectangular waveguide, forms a waveguide interconnection structure.

[0019] In one embodiment, the fourth transmission window is the same size and shape as the third transmission window, and the sidewalls of the fourth transmission window are made of metal.

[0020] In one embodiment, the second end of the second signal line tapers from a first width to a second width; the first width is the main width of the second signal line, and the second width is smaller than the first width.

[0021] In one embodiment, the first and second transmission windows are rectangular in shape, and the third transmission window is oblong in shape.

[0022] In one embodiment, the orthographic projections of the first transmission window and the second transmission window on the first printed circuit board fall within the orthographic projection of the third transmission window on the first printed circuit board.

[0023] The orthographic projection of the third transmission window onto the first printed circuit board falls within the orthographic projection of the rectangular waveguide onto the first printed circuit board.

[0024] Secondly, this application provides an integrated antenna module. The integrated antenna module includes a radio frequency antenna, a radio frequency chip, and the chip packaging transition structure provided in the first aspect.

[0025] The radio frequency antenna and radio frequency chip are connected for communication through a chip package transition structure.

[0026] Thirdly, this application provides a communication device. This communication device includes the integrated antenna module provided in the second aspect.

[0027] The aforementioned chip packaging transition structure, integrated antenna module, and communication device include a fan-out packaging structure and a first printed circuit board. The fan-out packaging structure includes a chip, a redistribution layer, a first solder ball, and multiple second solder balls. A first end of a first signal line of the redistribution layer is connected to a signal output terminal of the chip, and a first ground portion of the redistribution layer is connected to a ground output terminal of the chip. A first gap is provided between the first signal line and the first ground portion, and the first ground portion surrounds the first signal line. The first printed circuit board includes a feed layer. A second end of the first signal line is connected to a first end of a second signal line of the feed layer via a first solder ball. A first ground portion is connected to a second ground portion of the feed layer via multiple second solder balls. A second gap is provided between the second signal line and the second ground portion, and the second ground portion surrounds the second signal line. Multiple second solder balls are distributed around the second signal line and have openings at positions corresponding to the first solder balls. Thus, a first gap exists between the first signal line and the first ground portion in the redistribution layer, and the first ground portion is arranged around the first signal line, making the redistribution layer form a coplanar waveguide structure; a second gap exists between the second signal line and the second ground portion in the feed layer of the first printed circuit board, and the second ground portion is arranged around the second signal line, making the feed layer form a coplanar waveguide structure; the first signal line and the second signal line are connected by first solder balls of the fan-out package structure, and the first ground portion and the second ground portion are connected by multiple second solder balls of the fan-out package structure; the redistribution layer of the fan-out package structure and the first printed circuit board... A waveguide transition structure is formed between the feed layers. This waveguide transition structure results in low signal transmission loss between the fan-out package structure and the feed layer of the first printed circuit board. At the same time, multiple second solder balls are distributed around the second signal line in directions other than those of the first solder balls. The first solder balls, multiple second solder balls, the redistribution layer, and the feed layer together form a signal reflection cavity, which can confine electromagnetic field energy, reduce electromagnetic field energy leakage, and reduce signal transmission loss from the fan-out package structure to the first printed circuit board. Therefore, the above-mentioned chip package transition structure can achieve low transmission loss interconnection between the fan-out wafer package structure and the external environment. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 An exploded perspective view of a chip packaging transition structure provided in one embodiment;

[0030] Figure 2 for Figure 1 Top view of the rewiring layer in the chip package transition structure shown;

[0031] Figure 3 for Figure 1 The front view of the rewiring layer and chip connection portion in the chip package transition structure shown;

[0032] Figure 4 for Figure 1 The illustrated embodiment shows a top view of the passivation layer, the first solder ball, and the second solder ball portion in the chip packaging transition structure.

[0033] Figure 5 for Figure 1 The embodiment shown is a perspective view of the chip packaging transition structure including multiple first metallized vias, second signal lines, and a second spacing.

[0034] Figure 6 for Figure 1 Top view of the substrate and chip in the chip packaging transition structure shown;

[0035] Figure 7 for Figure 1 Cross-sectional view of the substrate, chip, passivation layer and redistribution layer in the chip packaging transition structure shown;

[0036] Figure 8 This is a three-dimensional exploded view of the chip packaging transition structure in another embodiment;

[0037] Figure 9 for Figure 8 The diagram shown is an exploded view of the chip packaging transition structure.

[0038] Figure 10 for Figure 8 The chip packaging transition structure shown includes multiple first metallized vias, second signal lines, and a second spacing in a 3D view.

[0039] Figure 11 for Figure 8A top view of the passivation layer, the first solder ball, and the second solder ball portions in the chip package transition structure shown;

[0040] Figure 12 for Figure 8 A perspective view of the second signal layer, first solder ball, second solder ball, and redistribution layer in the chip package transition structure shown.

[0041] Figure 13 This is a schematic diagram showing the relative positions of the second and third transmission windows in one embodiment;

[0042] Figure 14 This is a schematic diagram showing the relative positions of the third transmission window and the rectangular waveguide in one embodiment.

[0043] Figure label:

[0044] 100. Fan-out package structure; 110. Chip; 111. Signal lead; 112. Ground lead; 120. Rerouting layer; 121. First signal line; 121a. First end of the first signal line; 121b. Second end of the first signal line; 122. First ground portion; 123. First gap; 124. Second metallized via; 131. First solder ball; 132. Second solder ball; 140. Substrate layer; 150. Passivation layer; 200. First printed circuit board; 210. Feed layer; 211, Second signal line; 211a, First end of the second signal line; 211b, Second end of the second signal line; 212, Second ground portion; 213, Second gap; 214, First transmission window; 220, First dielectric layer; 221, First metallized via; 230, First ground layer; 231, Second transmission window; 300, Second printed circuit board; 310, Third transmission window; 320, Second dielectric layer; 330, Second ground layer; 400, Rectangular waveguide; 500, Cured film layer. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0047] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0048] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0049] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0050] In one exemplary embodiment, please refer to Figure 1 A chip packaging transition structure is provided, including a fan-out packaging structure 100 and a first printed circuit board 200.

[0051] Please refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 ,and Figure 5The fan-out package structure 100 includes a chip 110 and a redistribution layer 120. Layer (RDL), first solder ball 131 and second solder ball 132, wherein, the first end 121a of the first signal line of the redistribution layer 120 is connected to the signal lead-out terminal 111 of the chip 110, the first ground portion 122 of the redistribution layer 120 is connected to the ground lead-out terminal 112 of the chip 110, a first interval 123 is provided between the first signal line 121 and the first ground portion 122, and the first ground portion 122 is arranged around the first signal line 121; the first printed circuit board 200 includes a feed line layer 210, the second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feed line 210 through the first solder ball 131, the first ground portion 122 is connected to the second ground portion 212 of the feed line 210 through multiple second solder balls 132, a second interval 213 is provided between the second signal line 211 and the second ground portion 212, and the second ground portion 212 is arranged around the second signal line 211. Multiple second solder balls 132 are distributed around the second signal line 211, and an opening is provided at the position corresponding to the first solder ball 131.

[0052] Please refer to the following: Figure 1 , Figure 4 , Figure 5 , Figure 6 and Figure 7 The fan-out package structure 100 also includes a substrate layer 140 and a passivation layer 150. The substrate layer 140 has a chip slot for accommodating the chip 110; the passivation layer 150 encapsulates the redistribution layer 120, providing protection for the redistribution layer 120. Figure 1 For ease of demonstration, the redistribution layer 120 and passivation layer 150 are shown as two separate layers. First solder balls 131 and multiple second solder balls 132 are disposed on the side of the passivation layer 150 facing the first printed circuit board 200. In one possible embodiment, metallized vias are provided at positions on the passivation layer 150 corresponding to the first solder balls 131 and second solder balls 132 to connect the redistribution layer 120 and the fan-out first solder balls 131 and second solder balls 132. The substrate layer 140, in fan-out wafer packaging technology, is formed from the material used to fill the gaps between chips, essentially acting as a protective shell for the chip and simultaneously increasing the area of ​​the redistribution layer 120 corresponding to the chip.

[0053] In one possible embodiment, the substrate layer 140 is made of epoxy molding compounds (EMC). In another possible embodiment, the passivation layer 150 is made of polyimide (PI).

[0054] Please refer to Figure 3 and Figure 6 The signal output terminal 111 of chip 110 can be an input / output (I / O) pad of chip 110, and the ground output terminal 112 can be a ground pin or a ground pad of chip 110. There are two ground output terminals 112; the two ground output terminals 112 are respectively located on both sides of the signal output terminal 111, and there is a certain gap between the ground output terminals 112 and the signal output terminal 111, and they are not connected to each other.

[0055] For example, please refer to Figure 2 and Figure 3 The position of the first signal line 121 in the redistribution layer 120 is designed based on the position of the signal lead 111 of the chip 110. The length and width of the first signal line 121 and the width of the first interval 123 are determined based on the signal frequency corresponding to the chip 110.

[0056] In one possible implementation, please refer to Figure 3 and Figure 7 The redistribution layer 120 provides a second metallized via 124 at the corresponding positions of the signal lead 111 and ground lead 112 of the chip 110, wherein... Figure 3 The second metallized via between the signal lead 111 and the first signal line 121 is obscured and is not shown. The first ground portion 122 is not shown to demonstrate the second metallized via 124. The first signal line 121 and the signal lead 111 are connected via the second metallized via 124, and the first ground portion 122 is connected to the ground lead 112 via the second metallized via 124.

[0057] For example, such as Figure 3 and 7 As shown, the number of second metallized vias 124 corresponding to the ground lead 112 is 2. One second metallized via 124 is located directly above the ground lead 112, and the other second metallized via 124 is located away from the ground lead 112 relative to the aforementioned second metallized via 124. The aforementioned other second metallized via 124 is connected to the first ground portion 122. In this way, by connecting the ground lead 112 and the first ground portion 122 through two second metallized vias 124, the width of the first gap 123 between the first ground portion 122 and the first signal line 121 can be designed according to actual needs, and is not limited to the gap between the signal lead 111 and the ground lead 112 of the chip.

[0058] Figure 3 This is a front view diagram of the connection between the rewiring layer 120 and the chip 110, in which... Figure 3The redistribution layer in the diagram only shows portions of the first signal line 121 and the second metallized via 124. Figure 7 This is a cross-sectional structural diagram of the connection between the redistribution layer 120 and the chip 110, wherein the passivation layer 150 and the substrate layer 140 are respectively processed with perspective.

[0059] Metallized vias, in this context, refer to pathways formed in multilayer circuit boards or multilayer chip packages by drilling holes and coating the holes with a layer of metal material, creating electrical connections between different layers. Metallized vias can be used for signal transmission, power connections, or grounding connections. The second metallized via 124 can be part of the redistribution layer 120, formed by drilling holes in the passivation layer 150 and coating the holes with metal material; its location differs from the first metallized via 221 in the first printed circuit board 200 described in other embodiments of this application.

[0060] In one possible implementation, the redistribution layer 120 can also be connected to the signal leads 111 and ground leads 112 of the chip 110 in other ways, for example, by using microbumps, conductive adhesive, through-silicon vias, or copper pillars.

[0061] Please refer to Figure 2 The rewiring layer 120 provided in this embodiment includes two parts: a first signal line 121 and a first ground part 122. A first interval 123 is provided between the first signal line 121 and the first ground part 122, that is, the first signal line 121 and the first ground part 122 are not connected to each other, and the first ground part 122 is arranged around the first signal line 121.

[0062] In this embodiment, by setting a redistribution layer 120 in the fan-out package structure 100, high-density and accurate wiring operations can be performed, improving the integration and accuracy of the package, reducing the loss of chip radio frequency signals, and improving reliability.

[0063] Please refer to Figure 4 In this embodiment, the first solder ball 131 and the second solder ball 132 are fan-out solder balls of the fan-out package structure 100. The first solder ball 131 refers to the fan-out solder ball used to connect the first signal line 121 and the second signal line 211, and the second solder ball 132 refers to the fan-out solder ball used to connect the first ground part 122 and the second ground part 212. The difference between the first solder ball 131 and the second solder ball 132 is that they are set in different positions, but their shape, material and manufacturing process can be the same. Figure 4 Only one second solder ball 132 is marked as an illustration, in which Figure 4 All fan-out solder balls not marked are the second solder ball 132, only the fan-out solder ball marked "131" is the first solder ball.

[0064] The first solder ball 131 serves as the connection point between the second signal line 211 and the first signal line 121, and is located at the position corresponding to the first end 211a of the second signal line and the position corresponding to the second end 121b of the first signal line; a plurality of second solder balls 132 are distributed around the second signal line 211, and an opening is provided at the position corresponding to the first solder ball 131.

[0065] For example, the first printed circuit board 200 can be a printed circuit board (PCB) based on an insulating material (such as epoxy resin) and a copper foil layer, or it can be a silicon substrate or a ceramic substrate, etc.

[0066] The chip packaging transition structure provided in the above embodiment includes a fan-out packaging structure 100 and a first printed circuit board 200. The fan-out packaging structure 100 includes a chip 110, a redistribution layer 120, first solder balls 131, and a plurality of second solder balls 132. A first end 121a of the first signal line of the redistribution layer 120 is connected to a signal output end 111 of the chip 110. A first ground portion 122 of the redistribution layer 120 is connected to a ground output end 112 of the chip 110. A first gap 123 is provided between the first signal line 121 and the first ground portion 122, and the first ground portion 122 surrounds the first... Signal line 121 is provided; the first printed circuit board 200 includes a feeder layer 210, the second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feeder layer 210 through a first solder ball 131, the first ground part 122 is connected to the second ground part 212 of the feeder layer 210 through a plurality of second solder balls 132, a second interval 213 is provided between the second signal line 211 and the second ground part 212, and the second ground part 212 is provided around the second signal line 211; the plurality of second solder balls 132 are distributed around the second signal line 211 and have openings at positions corresponding to the first solder balls 131. Thus, a first gap 123 exists between the first signal line 121 and the first ground portion 122 in the redistribution layer 120, and the first ground portion 122 is arranged around the first signal line 121, making the redistribution layer 120 form a coplanar waveguide structure; a second gap 213 exists between the second signal line 211 and the second ground portion 212 in the feed layer 210 of the first printed circuit board 200, and the second ground portion 212 is arranged around the second signal line, making the feed layer 210 form a coplanar waveguide structure; the first signal line 121 and the second signal line are connected by the first solder ball 131 of the fan-out package structure 100, and the first ground portion 122 and the second ground portion 212 are connected by a plurality of second solder balls 132 of the fan-out package structure 100, and the redistribution layer 120 of the fan-out package structure 100 and the feed layer of the first printed circuit board 200 are connected by a first solder ball 131 of the fan-out package structure 100. A waveguide transition structure is formed between layers 210. Through this waveguide transition structure, the signal transmission between the fan-out package structure 100 and the feed layer 210 of the first printed circuit board 200 has low signal loss, achieving low-loss transmission of chip signals from the fan-out package structure 100 to the signal line on the first printed circuit board 200. At the same time, multiple second solder balls 132 are distributed around the second signal line 211 in directions other than the first solder ball 131. The first solder ball 131, multiple second solder balls 132, redistribution layer 120 and feed layer 210 together form a signal reflection cavity, which can confine electromagnetic field energy, reduce electromagnetic field energy leakage, and reduce the transmission loss of signals from the fan-out package structure 100 to the first printed circuit board 200. Therefore, the above-mentioned chip package transition structure can achieve low-loss interconnection between the fan-out wafer package structure and the external structure.

[0067] By using the chip packaging transition structure provided in the above embodiments, the transmission impedance of the chip packaging transition structure can be adjusted by adjusting the length and width of the first signal line 121 and the second signal line 211, as well as the spacing between the first interval 123 and the second interval 213, to match different signal frequencies and improve transmission performance.

[0068] In one exemplary embodiment, please refer to Figure 1 The first printed circuit board 200 further includes a first dielectric layer 220 and a first ground layer 230; wherein, the first dielectric layer 220 is disposed on the side of the feed layer 210 away from the redistribution layer 120, and the first ground layer 230 is disposed on the side of the first dielectric layer 220 away from the feed layer 210; a plurality of first metallized vias 221 are disposed in the area of ​​the first dielectric layer 220 corresponding to the second ground portion 212, and the first metallized vias 221 are used to provide a conductive path between the feed layer 210 and the first ground layer 230.

[0069] The first dielectric layer 220 is a non-conductive material layer in the first printed circuit board 200, and can be made of materials such as epoxy glass cloth, for example.

[0070] In one possible implementation, a plurality of uniformly distributed first metallized vias 221 are provided in the region of the first dielectric layer 220 corresponding to the second ground portion 212.

[0071] Please refer to the following: Figure 5 To facilitate illustrating the relative positional relationship between the multiple first metallized vias 221 and the second signal lines 211 and the second spacing 213, the first metallized vias 221 are shown as cylinders, independent of the first dielectric layer 220. For example... Figure 5 As shown, in addition to the positions corresponding to the second signal line 211 and the second interval 213, a plurality of first metallized vias 221 penetrating the first dielectric layer 220 are provided to provide a conductive path between the feed layer 210 and the first ground layer 230.

[0072] In this embodiment, the first printed circuit board 200 provides a conductive path between the first ground layer 230 and the feeder layer 210 through a plurality of first metallized vias 221, which can prevent signal leakage and reduce signal transmission loss.

[0073] In one exemplary embodiment, please refer to Figure 8 and 9 The provided chip packaging transition structure also includes a second printed circuit board 300 and a rectangular waveguide 400.

[0074] Please refer to Figure 10In this embodiment, the feed layer 210 of the first printed circuit board 200 is provided with a first transmission window 214. The first transmission window 214 is disposed around the second end 211b of the second signal line, and the first transmission window 214 and the second interval 213 form a connected region. Please refer to Figure 8 The first ground layer 230 of the first printed circuit board 200 is provided with a second transmission window 231. Please refer to... Figure 9 The second printed circuit board 300 is provided with a third transmission window 310 that penetrates the second printed circuit board 300, and the sidewall of the third transmission window 310 is made of metal; the second transmission window 231, the third transmission window 310 and the rectangular waveguide 400 form a waveguide interconnection structure. The second printed circuit board 300 includes a second dielectric layer 320 and a second ground layer 330.

[0075] exist Figure 9 In the exploded front view of the chip packaging transition structure provided in this embodiment, the third transmission window 310 is shown separately from the second printed circuit board 300 in order to facilitate the display of the third transmission window 310.

[0076] The first transmission window 214 confines the electromagnetic field energy transmitted by the second signal line within the first transmission window 214. Through the waveguide interconnection structure formed by the second transmission window 231 and the third transmission window 310, the electromagnetic field energy is coupled to the rectangular waveguide 400 and transmitted out through the external structure connected to the rectangular waveguide 400.

[0077] Please refer to Figure 11 and Figure 12 This is an exemplary schematic diagram illustrating the distribution of a first solder ball 131 and multiple second solder balls 132 around a second signal line in this embodiment. The multiple second solder balls 132 are connected to the second ground portion 212 of the feed layer 210 and the first ground portion 122 of the redistribution layer 120. In this embodiment, the second ground portion 212 is the area of ​​the feed layer 210 that does not include the area mapped to the feed layer 210 by the first signal line 121 and the first interval 123, as well as the portion of the first transmission window 214. Therefore, the distribution of the second solder balls 132 does not include the positions corresponding to the first signal line 121, the first interval 123, and the first transmission window 214. Figure 12 To clearly show the relative positional relationship between the first solder ball 131, the second solder ball 132, the first signal line 121, and the second signal line 211, the passivation layer 150 is not shown.

[0078] In this embodiment, the second printed circuit board 300 and the rectangular waveguide 400 provide a signal transmission line in the form of a rectangular waveguide 400 for the chip packaging transition structure; in this way, the chip packaging transition structure can be compatible with both printed circuit board traces and rectangular waveguide signal transmission line forms, improving the application flexibility of the chip packaging transition structure.

[0079] By adopting the chip packaging transition structure provided in the above embodiments, the transmission impedance of the chip packaging transition structure can be adjusted by adjusting the length and width of the first signal line 121 and the second signal line 211, the spacing between the first interval 123 and the second interval 213, and the length and width of the first transmission window 214, the second transmission window 231, the third transmission window 310 and the rectangular waveguide 400, so as to match different signal frequencies and achieve better signal transmission performance.

[0080] In one exemplary embodiment, please refer to Figure 8 and Figure 9 The chip packaging transition structure also includes a curing layer 500, wherein one side of the curing layer 500 is connected to the first printed circuit board 200, and the other side of the curing layer 500 is connected to the second printed circuit board 300. The curing layer 500 is made of a non-conductive material.

[0081] In this embodiment, the cured sheet 500 is used to press the first printed circuit board 200 and the second printed circuit board 300 together, playing the roles of adhesion, insulation and mechanical support, so that the first printed circuit board 200 and the second printed circuit board 300 can be stably combined into a whole.

[0082] The cured sheet 500 has a fourth transmission window, which, together with the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400, forms a waveguide interconnection structure. The sidewall of the fourth transmission window is made of metal.

[0083] In one possible implementation, the fourth transmission window is the same size and shape as the second transmission window 231, and the sidewalls of the fourth transmission window are made of metal.

[0084] In one possible implementation, the fourth transmission window is the same size and shape as the third transmission window 310, and the sidewalls of the fourth transmission window are made of metal. For example, as shown... Figure 9 As shown, the sidewalls of the third transmission window 310 and the fourth transmission window are metallized together to form a metal transition wall, which can better confine the electromagnetic field energy transmitted through the metal transition wall and reduce transmission loss.

[0085] In an exemplary embodiment, unlike the fixed connection method using the cured wafer 500, the chip packaging transition structure also includes a fixed connector for connecting the first printed circuit board 200 and the second printed circuit board 300 together.

[0086] In one exemplary embodiment, please refer to Figure 10 and Figure 12The second end 211b of the second signal line gradually narrows from a first width to a second width; the first width is the main width of the second signal line, and the second width is smaller than the first width. The gradual tapering of the second end 211b improves the smoothness of the impedance transition between the signal and the other end of the signal line, reducing signal reflection and power loss.

[0087] In an exemplary embodiment, the first transmission window 214, the second transmission window 231, the third transmission window 310, and the rectangular waveguide 400 have the same shape and size in the provided chip package transition structure.

[0088] In one exemplary embodiment, please refer to Figure 10 , Figure 13 and Figure 14 In the provided chip packaging transition structure, the first transmission window 214 and the second transmission window 231 are rectangular in shape; the third transmission window 310 is oblong in shape. For example, the first transmission window 214 and the second transmission window 231 are the same size.

[0089] In this embodiment, considering the fabrication process corresponding to the layer where the different windows are located, the different windows are set into different shapes to facilitate fabrication. The first transmission window 214 and the second transmission window 231 can be implemented using printed circuits, so they are set into rectangles. The third transmission window 310 penetrates the second printed circuit board 300, and the third transmission window 310 is set into an waist shape including straight line segments and semi-circular arc segments to facilitate fabrication.

[0090] In one implementation of this method, please refer to Figure 13 and Figure 14 The orthographic projections of the first transmission window 214 and the second transmission window 231 on the first printed circuit board 200 fall within the orthographic projection of the third transmission window 310 on the first printed circuit board 200, and the orthographic projection of the third transmission window 310 on the first printed circuit board 200 falls within the orthographic projection of the rectangular waveguide 400 on the first printed circuit board 200. Along the direction of signal transmission outward from the chip 110, the electromagnetic field energy transmitted by the first transmission window 214 and the second transmission window 231 is confined within the third transmission window 310, and the electromagnetic field energy transmitted by the third transmission window 310 is confined within the rectangular waveguide 400, reducing signal transmission loss.

[0091] In one exemplary embodiment, please refer to Figure 8 and Figure 9 The provided chip packaging transition structure includes: a fan-out packaging structure 100, a first printed circuit board 200, a curing layer 500, a second printed circuit board 300, and a rectangular waveguide 400, wherein...

[0092] The fan-out package structure 100 includes a chip 110, a redistribution layer 120, a first solder ball 131, and a plurality of second solder balls 132. The first end 121a of the first signal line of the redistribution layer 120 is connected to the signal lead-out end 111 of the chip 110, and the first ground part 122 of the redistribution layer 120 is connected to the ground lead-out end 112 of the chip 110. A first gap 123 is provided between the first signal line 121 and the first ground part 122, and the first ground part 122 is arranged around the first signal line 121.

[0093] The first printed circuit board 200 includes a feed line layer 210, a first dielectric layer 220, and a first ground layer. The second end 121b of the first signal line is connected to the first end 211a of the second signal line of the feed line layer through a first solder ball 131. The first ground portion 122 is connected to the second ground portion 212 of the feed line 210 through multiple second solder balls 132. A second interval 213 is provided between the second signal line 211 and the second ground portion 212, and the second ground portion 212 is arranged around the second signal line 211. The feed line 210 is provided with a first transmission window 214, which is arranged around the second end 211b of the second signal line. The first transmission window 214 and the second interval 213 form a connected area. The second end 211b of the second signal line gradually narrows from a first width to a second width. The first width is the main width of the second signal line 211, and the second width is smaller than the first width. A first dielectric layer 220 is disposed on the side of the feed layer 210 away from the redistribution layer 120, and a first ground layer 230 is disposed on the side of the first dielectric layer away from the feed layer. Multiple first metallized vias 221 are disposed in the area of ​​the first dielectric layer 220 corresponding to the second ground portion 212, and the first metallized vias 221 provide a conductive path between the feed layer 210 and the first ground layer 230. Multiple second solder balls 132 are distributed around the second signal line 211, and openings are provided at positions corresponding to the first solder balls 131. The first ground layer 230 of the first printed circuit board 200 is provided with a second transmission window 231.

[0094] One side of the cured sheet 500 is connected to the first printed circuit board 200, and the other side of the cured sheet 500 is connected to the second printed circuit board 300; the cured sheet 500 is provided with a fourth transmission window.

[0095] The second printed circuit board 300 is provided with a third transmission window 310 that penetrates the second printed circuit board 300. The sidewalls of the third transmission window 310 and the fourth transmission window are both made of metal. The third transmission window 310 and the fourth transmission window are the same size and shape.

[0096] The second transmission window 231, the fourth transmission window, the third transmission window 310, and the rectangular waveguide 400 form a waveguide interconnection structure; the first transmission window 214 and the second transmission window 231 are rectangular in shape, and the third transmission window 310 is waist-shaped; the orthographic projections of the first transmission window 214 and the second transmission window 231 on the first printed circuit board 200 fall within the orthographic projection of the third transmission window 310 on the first printed circuit board 200; the orthographic projection of the third transmission window 310 on the first printed circuit board 200 falls within the orthographic projection of the rectangular waveguide 400 on the first printed circuit board 200.

[0097] This application also provides an integrated antenna module. The integrated antenna module includes a radio frequency (RF) antenna, an RF chip, and the chip packaging transition structure provided in the above embodiments; the RF antenna and the RF chip are communicatively connected through the chip packaging transition structure.

[0098] This application also provides a communication device. This communication device includes the integrated antenna module provided in the above embodiments.

[0099] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip packaging transition structure, characterized in that, The chip packaging transition structure includes: a fan-out packaging structure and a first printed circuit board, wherein... The fan-out package structure includes a chip, a redistribution layer, a first solder ball, and a plurality of second solder balls. The first end of the first signal line of the redistribution layer is connected to the signal lead-out terminal of the chip, and the first ground portion of the redistribution layer is connected to the ground lead-out terminal of the chip. A first gap is provided between the first signal line and the first ground portion, and the first ground portion is arranged around the first signal line. The first printed circuit board includes a feed line layer, a first dielectric layer, and a first ground layer. The second end of the first signal line is connected to the first end of the second signal line in the feed line layer via a first solder ball. The first ground portion is connected to the second ground portion of the feed line layer via multiple second solder balls. A second gap is provided between the second signal line and the second ground portion, and the second ground portion is disposed around the second signal line. The first dielectric layer is disposed on the side of the feed line layer away from the redistribution layer, and the first ground layer is disposed on the side of the first dielectric layer away from the feed line layer. Multiple first metallized vias are disposed in the area of ​​the first dielectric layer corresponding to the second ground portion. The first metallized vias provide a conductive path between the feed line layer and the first ground layer. The plurality of second solder balls are distributed around the second signal line and have openings at positions corresponding to the first solder balls; the chip, the redistribution layer, and the feed layer are stacked in sequence, and the first solder balls, the plurality of second solder balls, the redistribution layer, and the feed layer together form a signal reflection cavity.

2. The chip packaging transition structure according to claim 1, characterized in that, Multiple uniformly distributed first metallized vias are provided in the area corresponding to the second grounding portion in the first dielectric layer.

3. The chip packaging transition structure according to claim 1, characterized in that, The chip packaging transition structure also includes a second printed circuit board and a rectangular waveguide, wherein... The feeder layer is provided with a first transmission window, which is arranged around the second end of the second signal line, and the first transmission window and the second interval form a connected region. The first ground layer of the first printed circuit board is provided with a second transmission window; The second printed circuit board is provided with a third transmission window that extends through the second printed circuit board, and the sidewall of the third transmission window is made of metal. The second transmission window, the third transmission window, and the rectangular waveguide form a waveguide interconnection structure.

4. The chip packaging transition structure according to claim 3, characterized in that, The chip packaging transition structure also includes a cured wafer layer; One side of the cured sheet is connected to the first printed circuit board, and the other side of the cured sheet is connected to the second printed circuit board; The cured sheet is provided with a fourth transmission window, which, together with the second transmission window, the third transmission window, and the rectangular waveguide, forms a waveguide interconnection structure.

5. The chip packaging transition structure according to claim 4, characterized in that, The fourth transmission window is the same size and shape as the third transmission window, and the sidewalls of the fourth transmission window are made of metal.

6. The chip packaging transition structure according to claim 3, characterized in that, The second end of the second signal line gradually narrows from a first width to a second width; the first width is the main width of the second signal line, and the second width is smaller than the first width.

7. The chip packaging transition structure according to claim 3, characterized in that, The first and second transmission windows are rectangular in shape, and the third transmission window is oblong in shape.

8. The chip packaging transition structure according to claim 3, characterized in that, The orthographic projections of the first transmission window and the second transmission window on the first printed circuit board fall within the orthographic projection of the third transmission window on the first printed circuit board; The orthographic projection of the third transmission window on the first printed circuit board falls within the orthographic projection of the rectangular waveguide on the first printed circuit board.

9. An integrated antenna module, characterized in that, The integrated antenna module includes a radio frequency antenna, a radio frequency chip, and a chip packaging transition structure as described in any one of claims 1-8; The radio frequency antenna and the radio frequency chip are communicatively connected through the chip package transition structure.

10. A communication device, characterized in that, The communication device includes the integrated antenna module as described in claim 9.

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