MOS tube chip with electrostatic protection structure

By designing the electrostatic protection layer and multi-layer electrostatic dispersion channels in the MOS tube chip, the problem of traditional MOS tube chips lacking the electrostatic protection structure is solved, efficient electrostatic protection and multi-layer electrostatic discharge paths are achieved, and the reliability and anti-interference ability of the chip are enhanced.

CN120048824AActive Publication Date: 2025-05-27SHENZHEN YOUJING MICROELECTRONICS TECH CO LTD
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Patent Information

Application Number
CN202510187066.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-20
Publication Date
2025-05-27
Estimated Expiration
2045-02-20

AI Technical Summary

Technical Problem

Traditional MOS tube chips lack electrostatic protection structures and cannot effectively absorb and disperse electrostatic discharges, which can easily cause static electricity to directly impact the internal circuit of the chip, increasing the risk of short circuit or current overload, and may damage the chip function.

Method used

A MOS tube chip with an electrostatic protection structure is designed, including a packaging box, a packaging cover, a packaging chip substrate, an insulating layer and an electrostatic protection layer. The electrostatic protective layer consists of a copper conductive layer and a nickel shielding layer. The conductive layer is used to quickly guide static electricity, and the shielding layer is used to prevent damage to the conductive layer. The conductive strips and shield strips are arranged in an interlaced fit to form multiple electrostatic discharge paths, forming a multi-layer electrostatic dispersion channel around the grooves and dispersion grooves, and the current limiting ring is used to dissipate the static electricity entering the pin.

Benefits of technology

Through the design of the electrostatic protective layer, it provides efficient and long-term stable electrostatic protection, reducing the potential damage of electrostatic discharge to the chip, and enhancing the overall reliability and anti-interference ability of the chip. The multi-layer electrostatic dispersion channel and the interlaced conductive strip and shield strip structure optimize the electrostatic discharge path, ensuring the continuous release of electrostatic energy in various environments, and improving stability and reliability.

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Abstract

The invention relates to the technical field of MOS tube chips, in particular to an MOS tube chip with an electrostatic protection structure, which comprises a packaging box and a packaging cover packaged on the packaging box, a mounting groove is formed in the packaging box, a plurality of pins are arranged on the periphery of the packaging box, and a packaging chip substrate is arranged in the packaging box; an insulating layer is arranged on the face, away from the packaging cover, of the packaging chip substrate, an electrostatic protection layer is arranged on the face, away from the packaging chip substrate, of the insulating layer, and the electrostatic protection layer is used for guiding electrostatic protection. Compared with the prior art, the static protection layer is arranged, so that the static protection layer has the capability of quickly discharging static electricity, long-term stable use performance can be provided in a severe environment, the reliability and adaptability of static protection are improved, and the safety of the chip in various complex environments is ensured.
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Citation Information

Patent Citations

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