Gate driver circuit, method of detecting short circuit, and computer readable medium

Abstract

The invention discloses a gate driver circuit, a method of detecting a short circuit, and a computer readable medium. The gate driver circuit includes: a high side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive the power switch between an on state and an off state; at least one capacitor cross-coupled to the high side region and the low side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensed value representative of a voltage transient of the power switch; a comparator circuit configured to compare the sensing value with a threshold value, and further configured to generate a comparison result based on whether the sensing value satisfies the threshold value; and a short circuit detector configured to detect a short circuit event based on the detection of the conduction state of the power switch and based on the comparison result indicating that the sensing value satisfies a threshold value.

Description

Technical Field

[0001] The present disclosure generally relates to the field of electronics, and more particularly, to a gate driver integrated with self-short circuit detection and protection. Background Art

[0002] Many functions of modern devices in motor vehicle applications, consumer applications, and industrial applications (such as driving motors or electromechanical machines) rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0003] A transistor typically includes a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures of the transistor. Additionally, the load current can be controlled by a control electrode (sometimes referred to as a gate electrode) of the transistor. For example, upon receiving a corresponding control signal from a gate driver, the control electrode can set its transistor to one of a conducting state or a blocking state. Thus, the semiconductor structure behaves like a switch having an on state and an off state (i.e., a conducting state and a blocking state, respectively).

[0004] Typically, a power converter includes two complementary transistors (e.g., a high-side transistor and a low-side transistor) for each motor phase, where the two complementary transistors form a half-bridge to drive an output pad connected to a motor winding. The gate driver for driving the two complementary transistors can be supplied with a fixed positive voltage from a positive power supply rail and a fixed negative voltage from a negative power supply rail. The positive power supply rail can be connected to the output pad via the high-side transistor of the two complementary transistors to supply a load current to the motor winding, and the negative power supply rail can be connected to the output pad via the low-side transistor of the two complementary transistors to absorb the load current from the motor winding. The two complementary transistors can be turned on and off complementarily to avoid cross-conduction.

[0005] Therefore, the load current (also referred to as the motor phase current) can be controlled by driving the two complementary transistors. The amplitude of the control signal received from the gate driver of each transistor can vary to drive the two complementary transistors between switching states. This in turn drives the motor. For example, the gate-source voltage Vgs of a MOSFET is typically driven to approximately zero to turn off the MOSFET, and is typically driven to a maximum value to fully turn on the MOSFET. For this reason, the gate-source voltage Vgs can be referred to as a control voltage.

[0006] During operation, the motor can be driven according to a motor control algorithm to achieve a desired motor speed corresponding to the electrical frequency of the control signal. SUMMARY OF THE INVENTION

[0007] In some implementations, a gate driver circuit includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sense voltage representative of a voltage transient of the power switch; a comparator circuit configured to compare the sense voltage with a threshold and further configured to generate a comparison result based on whether the sense voltage meets the threshold; and a short-circuit detector configured to detect a short-circuit event based on the on state of the power switch being detected and based on the comparison result indicating that the sense voltage meets the threshold.

[0008] In some implementations, a half-bridge gate driver circuit includes: a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a first gate driver disposed in the high-side region and configured to drive a high-side power switch between an on state and an off state; a second gate driver disposed in the low-side region and configured to drive a low-side power switch between an on state and an off state; a phase-node terminal coupled to or configured to be coupled to a phase node to which the high-side power switch and the low-side power switch are coupled; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit disposed in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and configured to provide a first sense value representative of a voltage transient of a phase voltage present at the phase node; a second sensing circuit disposed in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and configured to provide a second sense value representative of the voltage transient; a first comparator circuit configured to compare the first sense value with a first threshold and further configured to generate a first comparison result based on whether the first sense value meets the first threshold; a second comparator circuit configured to compare the second sense value with a second threshold and further configured to generate a second comparison result based on whether the second sense value meets the second threshold; a first short-circuit detector configured to detect a first short-circuit event based on the on state of the high-side power switch being detected and based on the first comparison result indicating that the first sense value meets the first threshold; and a second short-circuit detector configured to detect a second short-circuit event based on the on state of the low-side power switch being detected and based on the second comparison result indicating that the second sense value meets the second threshold, wherein the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.

[0009] In some implementations, a method for detecting a short circuit includes: generating, by a gate driver of a gate driver circuit, a drive signal configured to drive a power switch between an on state and an off state; sensing, by a capacitor, a voltage transient of a voltage across the power switch, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to a slope of the voltage transient; generating, at a sense node coupled to the capacitor, a sense value based on the capacitor current, wherein the sense value is proportional to the slope of the voltage transient; generating, by a state detector circuit, a state signal indicating whether the power switch is set to be in the on state or the off state by the gate driver; comparing, by a comparator circuit, the sense value with a threshold to generate a comparison result indicating whether the sense value meets the threshold; and detecting, by a short circuit detector, a short circuit based on the state signal indicating that the power switch is set to be in the on state and based on the comparison result indicating that the sense value meets the threshold.

[0010] In some implementations, a gate driver circuit includes: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region such that the at least one capacitor is configured to sense a voltage transient of a voltage across the power switch and provide a capacitor current proportional to a slope of the voltage transient; a sense circuit configured to receive the capacitor current and provide a sense current corresponding to the capacitor current; a comparator circuit configured to compare the sense current with a threshold and generate a comparison result based on whether the sense current meets the threshold; and a short circuit detector configured to detect a short circuit event based on detecting the on state of the power switch and based on the comparison result indicating that the sense current meets the threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Implementations are described herein with reference to the drawings.

[0012] Figure 1 A schematic block diagram showing a motor control system according to one or more implementations is shown.

[0013] Figure 2 A schematic block diagram showing a gate driver system according to one or more implementations is shown.

[0014] Figure 3A A circuit system according to one or more implementations is shown.

[0015] Figure 3B A circuit system according to one or more implementations is shown.

[0016] Figure 4 A signal diagram showing normal operating conditions according to one or more implementations.

[0017] Figure 5A An example of a short - circuit condition according to one or more implementations is shown.

[0018] Figure 5B A signal diagram showing a short - circuit condition according to one or more implementations.

[0019] Figure 6A An example of a short - circuit condition according to one or more implementations is shown.

[0020] Figure 6B A signal diagram showing a short - circuit condition according to one or more implementations.

[0021] Figure 7 Is a schematic block diagram of a dV / dt sensing and gate - driving system according to one or more embodiments.

[0022] Figure 8 Is a schematic block diagram of a dV / dt sensing and gate - driving system according to one or more embodiments. Detailed implementation

[0023] In the following, details are set forth to provide a more comprehensive description of example implementations. However, it will be apparent to those skilled in the art that these implementations can be practiced without these specific details. In other cases, well - known structures and devices are shown in block diagram form or in schematic form rather than in detail to avoid obscuring the implementations. Additionally, unless otherwise specifically stated, the features of different implementations described below can be combined with each other.

[0024] Furthermore, in the following description, equivalent or similar elements or elements having equivalent or similar functions are denoted by equivalent or similar reference numerals. Since the same elements or elements with equivalent functions are given the same reference numerals in the drawings, the repeated description of the elements provided with the same reference numerals can be omitted. Therefore, the descriptions provided for elements with the same or similar reference numerals can be interchanged with each other.

[0025] The orientations of the various elements in the figures are shown as examples, and the examples shown may be rotated relative to the orientation in which they are drawn. The description provided herein and the appended claims relate to any structure having the relationships described between the various features, regardless of whether the structure is in a particular orientation in the drawings or rotated relative to such an orientation. Similarly, for ease of description, spatial relative terms such as "top", "bottom", "beneath", "below", "lower", "above", "upper", "middle", "left", and "right" are used herein to describe the relationship of one element shown in the figures to one or more other elements. The spatial relative terms are intended to encompass different orientations of the elements, structures, and / or components in use or operation, in addition to the orientation in which they are drawn in the figures. The structure and / or components may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In addition, to simplify the drawings, sectional views in the figures show only the features in the plane of the section and do not show the material behind the plane of the section, unless otherwise indicated.

[0026] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in the same way (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0027] In the implementations described herein or shown in the figures, any direct electrical connection or coupling (e.g., any connection or coupling without additional intervening elements) may also be achieved by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intervening elements, or vice versa), provided that the general purpose of the connection or coupling (e.g., for conveying a certain signal or transmitting a certain information) is substantially maintained. Features in different implementations may be combined to form additional implementations. For example, unless otherwise stated to the contrary, variations or modifications described with respect to one implementation in an implementation may also apply to other implementations.

[0028] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, without departing from aspects of the implementations described herein, the terms "substantially" and "approximately" may be used herein to account for small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of that approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0029] In the present disclosure, expressions including ordinal numbers such as "first," "second," etc. may modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of the elements. Instead, such expressions are only for the purpose of distinguishing one element from another. For example, a first box and a second box indicate different boxes, although both are boxes. As another example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element.

[0030] A transistor may be referred to as a power switch, a logic switch, or a transistor switch and may be used to drive a current, such as a load current. In particular, a power transistor is a power semiconductor device that may be used to drive a load current. The power transistor includes a first load terminal (e.g., source or emitter) and a second load terminal (e.g., drain or collector). Additionally, the load current path of the power transistor may be controlled by a control electrode (sometimes referred to as a gate) connected to the control terminal of the power transistor. The load current path of the power transistor is a gate-controlled conduction channel whose conductivity may be controlled by a control voltage applied to the control electrode of the power transistor. For example, a power transistor may be turned on or off by enabling and disabling the control electrode of the power transistor. For example, applying a positive voltage between the gate and the source of a MOSFET will keep the MOSFET in the "on" state, while applying an approximately zero or slightly negative voltage between the gate and the source of the MOSFET will turn the MOSFET "off."

[0031] There are a turn-on process for turning on a transistor and a turn-off process for turning off a transistor. During the turn-on process of an n-channel transistor, a gate driver can be used to supply (provide) gate current (e.g., turn-on current) to the gate of the n-channel transistor to charge the gate voltage to a voltage sufficient to turn on the n-channel transistor. In contrast, during the turn-off process of the n-channel transistor, the gate driver is used to sink (absorb) gate current (e.g., turn-off current) from the gate of the n-channel transistor to discharge the gate voltage to a voltage sufficient to turn off the n-channel transistor. According to a pulse width modulation (PWM) scheme, voltage pulses can be output from the gate driver as control signals. Thus, during a PWM period for controlling the n-channel transistor, the control signal can switch between a turn-on voltage level and a turn-off voltage level. This in turn charges and discharges the gate capacitance to correspondingly modulate the gate voltage to turn on and turn off the n-channel transistor, respectively.

[0032] The situation is reversed for a p-channel transistor. The gate driver can be used to sink (absorb) gate current (e.g., turn-on current) from the gate of the p-channel transistor to discharge the gate voltage to a voltage sufficient to turn on the p-channel transistor. In contrast, during the turn-off process of the p-channel transistor, the gate driver is used to supply (provide) gate current (e.g., turn-off current) to the gate of the p-channel transistor to charge the gate voltage of the p-channel transistor to a voltage sufficient to turn off the p-channel transistor. During a PWM period for controlling the p-channel transistor, the control signal applied to the gate of the p-channel transistor can switch between a turn-on voltage level and a turn-off voltage level. This in turn charges and discharges the gate voltage to turn on and turn off the p-channel transistor, respectively.

[0033] For both n-channel and p-channel transistors, the n-channel and p-channel transistors are turned off when the gate-source voltage Vgs is approximately zero or below the threshold voltage, and the n-channel and p-channel transistors are turned on when the gate-source voltage Vgs is equal to or greater than the threshold voltage.

[0034] To drive a load in this way, two transistors are typically arranged in a half-bridge configuration and can form a converter leg of a power converter. The two transistors can include a high-side transistor and a low-side transistor coupled together at a phase node, and a phase voltage (e.g., phase node voltage) is generated at the phase node based on the switching states of the two transistors. The phase voltage is used to generate a phase current. The high-side transistor can be a p-channel transistor connected to a high-side supply potential, and the low-side transistor can be an n-channel transistor connected to a low-side supply potential. In some implementations, the high-side transistor and the low-side transistor can be of the same transistor type (e.g., both n-channel type or both p-channel type).

[0035] When the load current flows from the half-bridge to the load (e.g., from the phase node to the load), the load current (e.g., phase current) is referred to as a positive load current, and when the load current flows from the load to the half-bridge (e.g., from the load towards the phase node), the load current is referred to as a negative load current. The high-side transistor is responsible for conducting the positive load current when turned on so as to supply the load current to the load when its complementary low-side transistor is turned off (e.g., the low-side transistor is in a blocking or high-impedance mode). To absorb the load current from the load, the roles of the high-side transistor and the low-side transistor are reversed. Here, the low-side transistor is responsible for conducting the negative load current when turned on so as to absorb the load current from the load when its complementary high-side transistor is turned off (e.g., the high-side transistor is in a blocking or high-impedance mode). The two complementary transistors are typically switched such that the two are not turned on simultaneously.

[0036] The transistor can include IGBTs and MOSFETs (e.g., Si MOSFETs or SiC MOSFETs), etc. It will be understood that one type of transistor can replace another type of transistor. In this context, when replacing an IGBT with a MOSFET, in any one of the examples described herein, the drain of the MOSFET can replace the collector of the IGBT, the source of the MOSFET can replace the emitter of the IGBT, the drain-source voltage Vds of the MOSFET can replace the collector-emitter voltage Vce of the IGBT, and the gate-source voltage Vgs of the MOSFET can replace the gate-emitter voltage Vge of the IGBT, and vice versa.

[0037] Some implementations described in this disclosure relate to, but are not limited to, half-bridges for driving an electric motor. For example, as a power converter, a multiphase converter is configured to provide multiphase power by supplying power to a multiphase load (e.g., a three-phase motor). For example, three-phase power involves three symmetric sine waves that are out of phase with each other by 120 electrical degrees. In a symmetric three-phase power supply system, each of the three conductors carries an alternating current (AC) having the same frequency and voltage amplitude with respect to a common reference but with a phase difference of one-third of the drive period. Due to the phase difference, the voltage on any one of the three conductors reaches its voltage peak at one-third of the drive period, where the voltage peaks of the three conductors are distributed with a substantially equal phase delay from each other within the drive period. This phase delay provides a constant power transfer for a balanced linear load. This also makes it possible to generate a rotating magnetic field in an electric motor.

[0038] The three-phase converter includes three converter legs, one converter leg for each of the three phases, and each converter leg is connected in parallel with the other converter legs to a direct current (DC) voltage source. As described above, each converter leg includes a pair of transistors arranged in a half-bridge configuration for converting DC to AC to drive a phase load. However, a multiphase converter is not limited to three phases and may include two phases or more than three phases, with a converter leg for each phase. In some cases, two half-bridges may be connected as an H-bridge circuit, where a load (e.g., a motor) is connected as a crossbar between the two half-bridges as a single-phase load.

[0039] The short-circuit withstand time of a power switch is related to the gain and thermal capacity of the die of the power switch. The short-circuit withstand time is the amount of time that a power switch can tolerate a short-circuit condition before damage. Power switches made of wide-bandgap (WBG) materials such as gallium nitride (GaN) or silicon carbide (SiC) are thinner and have lower on-state resistance than silicon power switches. Due to the lower on-resistance, power switches made of WBG materials have lower on-state conduction losses and higher converter efficiency. Additionally, due to the smaller die size compared to silicon power switches, the switching losses are optimized, so WBG power switches can operate at higher frequencies than silicon power switches. However, the lower on-state conduction losses are related to higher gain, which results in a higher short-circuit current level and a shorter short-circuit withstand time within the power switch. Additionally, the smaller die has a reduced size related to lower thermal capacity, which results in a shorter short-circuit withstand time. Additionally, the short-circuit withstand time can vary widely depending on the device. Therefore, additional margin is typically required to account for variations in the short-circuit withstand time due to process variations and manufacturing tolerances.

[0040] Short-circuit detection is an important safety feature of a power converter, and as new generations of power switches are made of WBG materials, short-circuit detection becomes increasingly important. A WBG power switch may only be able to sustain a short-circuit condition for a very limited time (e.g., 1 μs or less). Therefore, to protect the power switch, short-circuit protection needs to be faster than the short-circuit withstand time of the power switch. For a WBG power switch, the short-circuit protection should be faster than 1 μs.

[0041] Some implementations disclosed herein are directed to short-circuit detection circuits and methods that detect a short circuit only when a voltage transient dV / dt exceeding a threshold is generated during a short circuit when the power switch is turned on. The voltage transient dV / dt can correspond to the voltage across the power switch or the voltage at a phase node (e.g., the phase voltage). For example, the voltage transient dV / dt can be the drain-source voltage V of the power switch DSTransients. A voltage transient dV / dt measurement can be obtained and compared to a threshold. Thus, the short-circuit detection circuit can include dV / dt sensing for quickly detecting short-circuit events. The short-circuit detection circuit can be configured to detect short-circuit events corresponding to a power switch being turned on directly under a pre-existing inductive short-circuit condition and / or short-circuit events corresponding to a short-circuit occurring during the conduction state of the power switch. The short-circuit detection circuit can implement a low-cost design. Additionally, the short-circuit detection circuit can detect short-circuit events less than 150 ns. Thus, the short-circuit detection circuit can detect short-circuit events faster than the short-circuit withstand time of a WBG power switch.

[0042] Figure 1 FIG. shows a schematic block diagram of a motor control system 100 in accordance with one or more implementations. In particular, the motor control system 100 includes a power converter 102, a controller 104, and a gate driver system 106. The controller 104 and the gate driver system 106 can operate together as a motor control unit. In some implementations, the motor control unit can be a monolithic integrated circuit (IC) in which the controller 104 and the gate driver system 106 are disposed on a single IC. "Monolithic" refers to an IC or semiconductor device fabricated on a single chip of a single material (typically silicon). The IC is called "monolithic" because the active and passive components of the circuit (such as transistors, resistors, capacitors, and interconnects) are all integrated onto a single piece or substrate of a material. In some implementations, the motor control unit can be divided into two or more ICs. For example, the controller 104 can be disposed on a first IC, and the gate driver system 106 can be disposed on one or more second ICs. Thus, the gate driver system 106 can be a monolithic gate driver. It will be understood that although the implementations described herein are directed to driving a motor, the concepts described herein can be extended to other types of inductive loads and are not limited to motors.

[0043] The motor control system 100 is further coupled to a motor M (e.g., a permanent magnet synchronous motor (PMSM) as an AC motor), and the motor M includes three phases U, V, and W. In this example, the power converter 102 is a three-phase voltage generator configured to provide three-phase power to drive the motor M by supplying three-phase voltages.

[0044] Deviations in both amplitude and phase can result in power and torque losses in the motor M. Thus, the controller 104 can be configured to monitor and control in real time the amplitude and phase of the voltage supplied to the motor M to ensure an appropriate current balance is maintained based on a feedback control loop.

[0045] The power converter 102 for the electric machine M includes a switch array of six transistors 108u, 108v, 108w, 109u, 109v, and 109w arranged in complementary pairs. Each complementary pair forms a half-bridge circuit and constitutes one converter leg for supplying a phase voltage to the electric machine M. Thus, each converter leg includes a high-side transistor 108u, 108v, or 108w and a low-side transistor 109u, 109v, or 109w. Additionally, the transistors 108u, 108v, 108w, 109u, 109v, and 109w can be connected anti-parallel to corresponding freewheeling diodes D1 to D6. The freewheeling diodes D1 to D6 provide an alternative current path for the load current during the turn-off of the respective transistors 108u, 108v, 108w, 109u, 109v, and 109w for current commutation. For example, the freewheeling diode D1 provides an alternative current path with respect to the low-side transistor 109u during the turn-off of the low-side transistor 109u. Similarly, the freewheeling diode D2 provides an alternative current path with respect to the high-side transistor 108u during the turn-off of the high-side transistor 108u.

[0046] Load current paths U, V, and W extend from the output disks Uout, Vout, or Wout of respective converter legs (e.g., the output terminals of each half-bridge circuit) located between complementary transistors and are configured to be coupled to a load, such as the electric machine M. Each load current path U, V, and W carries a corresponding phase current Iu, Iv, and Iw. Each phase current Iu, Iv, and Iw has an AC electrical frequency that directly corresponds to the actual motor speed of the electric machine M.

[0047] The power converter 102 is coupled to a DC power supply (e.g., a battery or a diode bridge rectifier) and is coupled to a gate driver system 106.

[0048] The controller 104 can be a microcontroller or another hardware-based controller that performs the motor control functions of the motor control system 100 in real time (or near real time) and sends PWM control signals to the gate driver system 106. The controller 104 can adopt a PWM scheme to control the state of each transistor and ultimately control each phase current provided on the corresponding load current paths U, V, and W. The gate driver system 106 generates drive signals based on the PWM control signals to control the switching states (e.g., on and off states) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. Thus, the load current paths U, V, and W can be controlled by the controller 104 and the gate driver system 106 by controlling the control electrodes (e.g., gate electrodes) of the transistors 108u, 108v, 108w, 109u, 109v, and 109w. For example, when receiving the PWM control signal from the controller 104, the gate driver system 106 can set the corresponding transistor 108u, 108v, 108w, 109u, 109v, or 109w to one of a conducting state (e.g., on state) or a blocking state (e.g., off state).

[0049] The gate driver system 106 can include one or more gate drivers for driving the transistors 108u, 108v, 108w, 109u, 109v, and 109w between switching states. For example, the gate driver system 106 can include gate drivers for each half-bridge circuit. The gate driver system 106 can be configured to receive instructions including PWM control signals from the controller 104 and turn on or off the transistors 108u, 108v, 108w, 109u, 109v, and 109w according to the received instructions and control signals respectively. For example, during the turn-on process of the transistors 108u, 108v, 108w, 109u, 109v, or 109w, the gate driver system 106 can be used to provide (supply) gate current to the gates of the transistors 108u, 108v, 108w, 109u, 109v, or 109w to charge the gates. Conversely, during the turn-off process, the gate driver system 106 can be used to draw (absorb) gate current from the gates of the transistors 108u, 108v, 108w, 109u, 109v, or 109w to discharge the gates.

[0050] In addition, the transistors 108u, 108v, 108w, 109u, 109v, and 109w of the power converter 102 are controlled such that the high-side and low-side transistors in the same converter leg are not turned on simultaneously at any time; otherwise, the DC power supply would be short-circuited. According to the motor control algorithm, this requirement can be met by the complementary operation of the transistors 108u, 108v, 108w, 109u, 109v, and 109w within the converter leg. For example, during operation, the motor M can be driven according to the motor control algorithm to achieve a desired motor speed corresponding to the electrical frequency of the control signal. A dead time can be imposed by the controller 104 during which both the high-side and low-side transistors of the same converter leg are turned off simultaneously.

[0051] As described above, Figure 1 is provided only as an example. Other examples can be different from the example regarding Figure 1 described. For example, in some implementations, the multiple motor phases can be different, or the two half-bridges can be connected as an H-bridge circuit. In some implementations, additional circuit components can be added without departing from the disclosure provided above.

[0052] Figure 2 FIG. shows a schematic block diagram of a gate driver system 200 according to one or more implementations. The gate driver system 200 can correspond to the Figure 1 gate driver system 106. As Figure 2 shown, the gate driver system 200 includes a single-phase motor drive stage 201 (e.g., a converter leg or a half-bridge circuit) and a gate driver 206 electrically coupled to the single-phase motor drive stage 201. The gate driver system 200 can be a half-bridge gate driver circuit and can be replicated for each converter leg in the gate driver system 200.

[0053] The single-phase motor drive stage 201 includes a high-side transistor 208u and a low-side transistor 209u, which are controlled to supply a load current I LOAD to the motor M. In other words, the single-phase motor drive stage 201 in this example corresponds to the U-phase converter leg of the motor M described with respect to Figure 1 However, the single-phase motor drive stage 201 can correspond to any converter leg in the motor control system 100.

[0054] The gate driver 206 is a monolithic gate driver that includes a low-side gate driver 210 for driving the low-side transistor 209u and a high-side gate driver 220 for driving the high-side transistor 208u. Both the low-side gate driver 210 and the high-side gate driver 220 gate-drive their respective low-side transistor 209u and high-side transistor 208u based on the PWM control signals LIN and HIN received from a controller such as the controller 104.

[0055] The PWM control signals from the controller 104 are received at the PWM logic unit 225 of the gate driver 206. The PWM logic unit 225 receives the PWM control signals LIN and HIN from the controller 104 and ensures the implementation of a minimum dead time during which both the high-side transistor 208u and the low-side transistor 209u are turned off simultaneously. Finally, the PWM control signals LIN and HIN are passed to the corresponding low-side gate driver 210 and high-side gate driver 220. In some implementations, the PWM control signal HIN provided to the high-side gate driver 220 may be passed through a level shifter 230. The level shifter 230 is used to convert (e.g., level shift) the PWM control signal HIN so as to transfer control information from the low-voltage or power domain of the gate driver 206 to the high-voltage or power domain. Thereafter, the low-side gate driver 210 and the high-side gate driver 220 perform gate driving.

[0056] The low-side gate driver 210 and the high-side gate driver 220 respectively include separate pre-driver circuitry 240 and 250 and buffers 245 and 255. The pre-driver circuitry 240 and 250 are configured to receive the PWM control signals LIN and HIN and, based thereon, control the on / off states of the respective first current sources (such as source FETs) for generating the current Io+. Additionally, the pre-driver circuitry 240 and 250 are configured to receive the PWM control signals LIN and HIN and, based thereon, control the on / off states of the respective second current sources (such as sink FETs) for generating the current Io-. The respective current sources are provided in the buffers 245 and 255. Thus, the buffers 245 and 255 may each include a pair of complementary FETs for generating the on-current Io+ and the off-current Io- for the respective low-side transistor 209u and high-side transistor 208u.

[0057] The front - end driver circuitry systems 240 and 250 may each further include a regulator configured to control the magnitudes of the turn - on current Io+ and the turn - off current Io− by controlling the current sources in the buffers 245 and 255. In other words, each regulator commands its respective buffer 245 or 255 to use a certain current capacity.

[0058] The gate driver 206 may be configured to receive a PWM control signal from the controller 104 and turn on or off the corresponding high - side transistor 208u and low - side transistor 209u according to the received PWM control signal. For example, during the turn - on process of the high - side transistor 208u and the low - side transistor 209u, the gate driver 206 may be used to supply (provide) gate current Io+ to the gate of one of the high - side transistor 208u or the low - side transistor 209u to charge the gate. Conversely, during the turn - off process, the gate driver 206 may be used to draw (absorb) gate current Io− from the gate of one of the high - side transistor 208u or the low - side transistor 209u to discharge the gate.

[0059] Thus, the controller 104 is electrically coupled to the gate driver 206 for transmitting information and control signals therebetween, and the gate driver 206 is electrically coupled to the single - phase motor drive stage 201 for driving the high - side transistor 208u and the low - side transistor 209u.

[0060] The gate driver 206 may include a high - side circuitry arranged in a high - voltage power domain and configured to monitor and detect a short - circuit event corresponding to the high - side transistor 208u. The high - side circuitry may be used to trigger the high - side transistor 208u to turn off based on detecting a short - circuit event corresponding to the high - side transistor 208u. Additionally, the gate driver 206 may include a low - side circuitry arranged in a low - voltage power domain and configured to monitor and detect a short - circuit event corresponding to the low - side transistor 209u. The low - side circuitry may be used to trigger the low - side transistor 209u to turn off based on detecting a short - circuit event corresponding to the low - side transistor 209u.

[0061] The gate driver system 200 further includes a bootstrap diode 260 for charging the voltage charging device 270. In this case, the voltage charging device 270 is a bootstrap capacitor. However, the voltage charging device 270 may be a rechargeable battery or other types of voltage charging devices.

[0062] Additionally, in Figure 2Here, VB refers to the high-side floating supply voltage; VS refers to the high-side floating ground voltage, which can also be referred to as the phase voltage or phase node voltage; VCC refers to the low-side fixed supply voltage; VSS refers to the low-side ground voltage; HO refers to the output terminal of the high-side floating output voltage; LO refers to the output terminal of the low-side output voltage; DC+ refers to the positive power supply of the DC link; DC- refers to the negative power supply of the DC link; and HIN and LIN refer to the PWM control signals (e.g., logic input voltages) received from the controller 104. The low-side fixed supply voltage VCC also supplies power to certain logic components in the gate driver 206 that operate using the fixed supply voltage, and can be used to charge the voltage charging device 270 when the bootstrap diode 260 is forward-biased.

[0063] Typically, VB = VCC - VS - VD, where VD is the forward bias voltage drop across the bootstrap diode 260. As an example implementation, when the low-side fixed supply voltage VCC is equal to 15V, the high-side floating ground voltage VS is equal to 0V, and the bootstrap diode 260 is forward-biased with a forward bias voltage drop VD = 0.5V, then VB = 15V - 0V - 0.5V = 14.5V. That is, during normal operation, since the voltage charging device 270 supplies power to the high side of the gate driver 206, the high-side floating supply voltage VB is approximately 15V higher than the high-side floating ground voltage VS. For example, the positive power rail providing the DC link positive power supply DC+ can be in the range of 200V to 1200V, but is not limited thereto. Additionally, when the low-side transistor 209u is conducting (and the high-side transistor 208u is off), the high-side floating ground voltage VS is equal to DC- (e.g., VSS or 0V). The negative power rail provides the DC link negative power supply DC-, and can be shorted to VSS as shown, but does not have to be. In this case, the high-side floating supply voltage VB is close to 15V, and the low-side fixed supply voltage VCC charges the voltage charging device 270 through the bootstrap diode 260. In other cases, when the high-side transistor 208u is conducting (and the low-side transistor 209u is off), and the bootstrap diode 260 is reverse-biased and not conducting, the high-side floating ground voltage VS is equal to the DC link positive power supply DC+. In the case where the bootstrap diode 260 is reverse-biased, the high-side floating supply voltage VB is 15V higher than the DC link positive power supply DC+, and the voltage charging device 270 discharges slowly. It will be understood that certain circuit values and device parameters used herein are used as examples to illustrate one or more possible implementations among many possible implementations, and should not be considered in any way as restrictive or required unless explicitly stated.

[0064] The above voltage is set such that the high-side voltage domain of the gate driver 206 operates in a voltage or power domain higher than that of the low-side voltage domain of the gate driver 206. For example, the low-side fixed supply voltage VCC can be set to 15V, and when the DC link positive power supply DC+ is 1200V, the high-side floating supply voltage VB can operate at a maximum voltage of 1215V.

[0065] The gate driver 206 is configured to receive instructions from the controller 104 to drive a motor phase (e.g., single-phase motor drive stage 201) connected to the high-side floating ground voltage VS using PWM control signals. These PWM control signals, depicted as PWM control signals HIN and LIN, are received by the gate driver 206 and passed to the high-side gate driver 220 and the low-side gate driver 210 via appropriate logic (e.g., PWM logic unit 225 for the low-side gate driver 210 and level shifter 230 for the high-side gate driver 220). The low-side gate driver 210 is configured to receive the PWM control signal LIN, the high-side gate driver 220 is configured to receive the PWM control signal HIN, and the low-side gate driver 210 and the high-side gate driver 220 drive the low-side transistor 209u and the high-side transistor 208u respectively using the output terminals LO and HO of the gate driver 206.

[0066] As described above, Figure 2 is provided only as an example. Other examples may be different from the example described with respect to Figure 2 For example, in some implementations, the high-side gate driver 220 can receive the PWM control signal directly from the controller 104. In some implementations, the bootstrap diode 260 can be located outside the gate driver 206. In some implementations, the low-side ground voltage VSS can be connected to a supply potential different from the ground potential. In some implementations, additional circuit components can be added without departing from the disclosure provided above.

[0067] Figure 3A A circuit system 300A according to one or more implementations is shown. The circuit system 300A can be integrated in a half-bridge gate driver circuit. For example, the circuit system 300A can be integrated into a half-bridge gate driver circuit similar to the gate driver system 200 described in connection with Figure 2 In Figure 3A a high-side circuit system and a low-side circuit system for detecting short-circuit events are shown in more detail.

[0068] Circuit system 300A may include: a phase node terminal 302, which is coupled or configured to be coupled to a phase node (e.g., output disk Uout) coupled to high-side transistor 208u and low-side transistor 209u. A phase voltage VS may be generated at the phase node according to the switching operations of high-side transistor 208u and low-side transistor 209u. When high-side transistor 208u is turned on by high-side gate driver 220, phase node terminal 302 may be connected to the high-side supply potential (e.g., DC+) through high-side transistor 208u, and when low-side transistor 209u is turned on by low-side gate driver 210, phase node terminal 302 may be connected to the low-side supply potential (e.g., DC-) through low-side transistor 209u.

[0069] Circuit system 300A may include: a capacitor HVC, which is cross-coupled to the high-side region and the low-side region of circuit system 300A. This capacitor may be a high-voltage capacitor. In some implementations, more than one capacitor may be cross-coupled to the high-side region and the low-side region. Thus, at least one capacitor cross-coupled to the high-side region and the low-side region is provided. Capacitor HVC may provide a capacitor current Icap that is proportional to the magnitude of the voltage slope of phase voltage VS. In other words, capacitor current Icap is proportional to the steepness or rate of change of the voltage transient dV / dt of phase voltage VS. Since the DC link voltages DC+ and DC- are fixed, the voltage transient dV / dt of the phase voltage also corresponds to the voltage transients of high-side transistor 208u and low-side transistor 209u respectively. For example, the voltage transient across high-side transistor 208u DS is proportional to or equal to the voltage transient dV / dt of phase voltage VS. Additionally, the voltage transient across low-side transistor 209u DS is proportional to or equal to the voltage transient dV / dt of phase voltage VS.

[0070] As a result, capacitor current Icap may be based on the rate of change of the voltage across high-side transistor 208u DS and / or may be based on the rate of change of the voltage across low-side transistor 209u DS For example, capacitor current Icap may be proportional to the magnitude of the voltage slope of the voltage across high-side transistor 208u DS and may be proportional to the magnitude of the voltage slope of the voltage across low-side transistor 209u DS Thus, capacitor HVC can be used to sense and measure the voltage transient of phase voltage VS, the voltage transient of the voltage across high-side transistor 208u DS and / or the voltage transient of the voltage across low-side transistor 209u DS ​

[0071] Circuit system 300A may include a first sensing circuit 304 disposed in the high-side region of circuit system 300A and a second sensing circuit 306 disposed in the low-side region of circuit system 300A. The first sensing circuit 304 is coupled to a first corresponding capacitor among at least one capacitor and is configured to provide a first sensed value representing a voltage transient of the phase voltage VS present at the phase node. Alternatively, the first sensed value may represent the voltage V of the high-side transistor 208u DS of the voltage transient. In this example, the first corresponding capacitor is capacitor HVC. The first sensed value may be a first sensed voltage HVsense provided at the first sensing node 308. Alternatively, the first sensed value may be a first sensed current corresponding (e.g., proportional) to the capacitor current Icap. In some implementations, the first sensed current may be the same current as the capacitor current Icap.

[0072] The second sensing circuit 306 is coupled to a second corresponding capacitor among at least one capacitor and is configured to provide a second sensed value representing a voltage transient of the phase voltage VS present at the phase node. Alternatively, the second sensed value may represent the voltage V of the low-side transistor 209u DS of the voltage transient. In this example, the second corresponding capacitor is capacitor HVC. The second sensed value may be a second sensed voltage LVsense provided at the second sensing node 310. Alternatively, the second sensed value may be a second sensed current corresponding (e.g., proportional) to the capacitor current Icap. In some implementations, the second sensed current may be the same current as the capacitor current Icap. Although the first corresponding capacitor and the second corresponding capacitor are shown as the same capacitor (e.g., capacitor HVC) in this example, the first corresponding capacitor and the second corresponding capacitor may be different capacitors connected in series or coupled to different sensing paths. The first sensing circuit 304 may include a first Zener diode 312 and a first sensing resistor 314 connected in parallel between the first internal positive supply voltage Vdd_HS (e.g., provided by a first local voltage source) and the first sensing node 308. The first sensing resistor 314 may be configured to receive at least a portion of the capacitor current Icap and generate a first sensed voltage HVsense at the first sensing node 308 based on the portion of the capacitor current Icap flowing through the first sensing resistor 314. The first sensing resistor 314 may be a single resistor or multiple resistors arranged in different ways (including series, parallel, or a combination of both series and parallel).

[0073] The high-side gate driver 220 can be configured to be coupled to a first internal positive supply voltage Vdd_HS and a first internal ground voltage. For example, the high-side gate driver 220 can use the first internal positive supply voltage Vdd_HS and the first internal ground voltage to drive the high-side transistor 208u between an on state and an off state. In some implementations, the first internal positive supply voltage Vdd_HS can be derived from the high-side floating supply voltage VB, and the first internal ground voltage can be derived from the phase voltage VS (e.g., the high-side floating ground voltage).

[0074] The first sensing circuit 304 may further include a first additional power supply 316 and a first comparator circuit 318 (e.g., a voltage comparator or a current comparator). The first additional power supply 316 can add an additional predetermined voltage to the first internal positive supply voltage Vdd_HS to generate a first threshold Th1 as a threshold voltage. In other words, the sum of the additional predetermined voltage and the first internal positive supply voltage Vdd_HS can be used to generate the first threshold Th1. Therefore, the first threshold Th1 is greater than the internal positive supply voltage Vdd_HS. In an implementation where the first comparator circuit 318 is a current comparator, the first additional power supply 316 can be a current source for providing the first threshold Th1 as a threshold current to the first comparator circuit 318.

[0075] The first comparator circuit 318 can compare the first sensed value (e.g., the first sensed voltage HVsense or the first sensed current) with the first threshold Th1, and can generate a first comparison result based on whether the first sensed value meets the first threshold Th1. For example, the first comparator circuit 318 can generate a logic high output when the first sensed value is greater than or equal to the first threshold Th1, and can generate a logic low output when the first sensed value is not greater than or equal to the first threshold Th1.

[0076] The first sensing circuit 304 may further include a first state detector circuit 320 and a first short-circuit detector 322. Thus, the first sensing circuit 304 is a sensing circuit configured to detect a short circuit based on sensed information. The first state detector circuit 320 can be configured to detect the switching state of the high-side transistor 208u, and to indicate to the first short-circuit detector 322 that the high-side transistor 208u is in an on state or to indicate that the high-side transistor 208u is in an off state. For example, the first state detector circuit 320 can monitor the gate voltage of the high-side transistor 208u, the PWM control signal HIN, or the output terminal HO of the high-side transistor 208u to determine the switching state of the high-side transistor 208u. The first state detector circuit 320 can generate a logic high output when the high-side transistor 208u is in an on state, and can generate a logic low output when the high-side transistor 208u is in an off state.

[0077] The first short - circuit detector 322 can receive the first comparison result from the first comparator circuit 318 and an indication of the switch state from the first state detector circuit 320. The first short - circuit detector 322 can detect a first short - circuit event based on the first state detector circuit 320 detecting the on - state of the high - side transistor 208u and based on the first comparison result indicating that the first sensed value satisfies the first threshold Th1. Thus, the first short - circuit detector 322 can be a logic decision block. In some implementations, the first short - circuit detector 322 can be a logic circuit including one or more logic gates. For example, in some implementations, the first short - circuit detector 322 can be an AND gate. Thus, the first short - circuit detector 322 can detect the first short - circuit event when both inputs of the first short - circuit detector 322 have a logic high value. Thus, the first short - circuit detector 322 can detect the first short - circuit event based on the first state detector circuit 320 indicating that the high - side transistor 208u is in the on - state and based on the first comparator circuit 318 indicating that the first sensed value is greater than the first threshold Th1. When both inputs of the first short - circuit detector 322 have a logic high value, the first short - circuit detector 322 can generate a logic high output (e.g., a fault signal) at the detector output Out1.

[0078] When the first short - circuit event occurs, the first short - circuit event induces a voltage transient of the phase voltage VS at the phase node and causes the first sensed value to satisfy the first threshold Th1 by making the first sensed value greater than the first threshold Th1. The first short - circuit detector 322 can trigger the high - side transistor 208u to be set to the off - state in response to detecting the first short - circuit event so as to protect the high - side transistor 208u. For example, the first short - circuit detector 322 can send the first fault signal to the high - side gate driver 220 or the controller 104, and then the high - side gate driver 220 or the controller 104 can turn off the high - side transistor 208u.

[0079] For the low - side transistor 209u, the second sensing circuit 306 can operate similarly to the first sensing circuit 304. The second sensing circuit 306 can include a second Zener diode 324 and a second sense resistor 326 coupled in parallel between the second internal positive supply voltage Vdd_LS (e.g., provided by a second local voltage source) and the second sense node 310. The second sense resistor 326 can be configured to receive at least a portion of the capacitor current Icap and generate a second sense voltage LVsense at the second sense node 310 based on the portion of the capacitor current Icap flowing through the second sense resistor 326. The second sense resistor 326 can be a single resistor or multiple resistors arranged in different ways (including in series, in parallel, or a combination of both series and parallel).

[0080] The low-side gate driver 210 can be configured to be coupled to a second internal positive supply voltage Vdd_LS and a second internal ground voltage. For example, the low-side gate driver 210 can use the second internal positive supply voltage Vdd_LS and the second internal ground voltage to drive the low-side transistor 209u between an on state and an off state. In some implementations, the second internal positive supply voltage Vdd_LS can be derived from the low-side fixed supply voltage VCC, and the second internal ground voltage can be derived from ground (e.g., the low-side fixed ground voltage).

[0081] The second sensing circuit 306 can further include a second additional power supply 328 and a second comparator circuit 330 (e.g., a voltage comparator or a current comparator). The second additional power supply 328 can add an additional predetermined voltage to the second internal positive supply voltage Vdd_LS to generate a second threshold Th2 as a threshold voltage. In other words, the sum of the additional predetermined voltage and the second internal positive supply voltage Vdd_LS can be used to generate the second threshold Th2. Thus, the second threshold Th2 is greater than the internal positive supply voltage Vdd_LS. In an implementation where the second comparator circuit 330 is a current comparator, the second additional power supply 328 can be a current source for providing the second threshold Th2 as a threshold current to the second comparator circuit 330.

[0082] The second comparator circuit 330 can compare the second sensed value (e.g., the second sensed voltage LVsense or the second sensed current) with the second threshold Th2, and can generate a second comparison result based on whether the second sensed value meets the second threshold Th2. For example, the second comparator circuit 330 can generate a logic high output when the second sensed value is greater than or equal to the second threshold Th2, and can generate a logic low output when the second sensed value is not greater than or equal to the second threshold Th2.

[0083] The second sensing circuit 306 can further include a second state detector circuit 332 and a second short-circuit detector 334. Thus, the second sensing circuit 306 is a sensing circuit configured to detect a short circuit based on the sensed information. The second state detector circuit 332 can be configured to detect the switching state of the low-side transistor 209u, and to indicate to the second short-circuit detector 334 that the low-side transistor 209u is in an on state or to indicate that the low-side transistor 209u is in an off state. For example, the second state detector circuit 332 can monitor the gate voltage of the low-side transistor 209u, the PWM control signal LIN, or the output terminal LO of the low-side transistor 209u to determine the switching state of the low-side transistor 209u. The second state detector circuit 332 can generate a logic high output when the low-side transistor 209u is in an on state, and can generate a logic low output when the low-side transistor 209u is in an off state.

[0084] The second short-circuit detector 334 can receive a second comparison result from the second comparator circuit 330 and an indication of the switch state from the second state detector circuit 332. The second short-circuit detector 334 can detect a second short-circuit event based on the second state detector circuit 332 detecting the on-state of the low-side transistor 209u and based on the second comparison result indicating that the second sensed value satisfies a second threshold Th2. Thus, the second short-circuit detector 334 can be a logic decision block. In some implementations, the second short-circuit detector 334 can be a logic circuit including one or more logic gates. For example, in some implementations, the second short-circuit detector 334 can be an AND gate. Thus, the second short-circuit detector 334 can detect the second short-circuit event when both inputs of the second short-circuit detector 334 have a logic high value. Thus, the second short-circuit detector 334 can detect the second short-circuit event based on the second state detector circuit 332 indicating that the low-side transistor 209u is in the on-state and based on the second comparator circuit 330 indicating that the second sensed value is greater than the second threshold Th2. When both inputs of the second short-circuit detector 334 have a logic high value, the second short-circuit detector 334 can generate a logic high output (e.g., a fault signal) at the detector output Out2.

[0085] When the second short-circuit event occurs, the second short-circuit event induces a voltage transient of the phase voltage VS at the phase node and causes the second sensed value to satisfy the second threshold Th2 by making the second sensed value greater than the second threshold Th2. The second short-circuit detector 334 can trigger the low-side transistor 209u to be set to the off-state in response to detecting the second short-circuit event in order to protect the low-side transistor 209u. For example, the second short-circuit detector 334 can send a second fault signal to the low-side gate driver 210 or the controller 104, and then the low-side gate driver 210 or the controller 104 can turn off the low-side transistor 209u.

[0086] Thus, both the first sensing circuit 304 and the second sensing circuit 306 are capable of detecting the position of the phase voltage VS relative to DC+ and DC-, and can be used for short-circuit detection and protection. The short-circuit event can be detected only when the corresponding transistor is turned on. Otherwise, in the case where the corresponding transistor is turned off, the comparison results of the first comparator circuit 318 or the second comparator circuit 330 can be ignored respectively.

[0087] As described above, Figure 3A is provided only as an example. Other examples can be different from the example regarding Figure 3A described. Figure 3A The number and arrangement of the components shown in Figure 3A are provided as an example. In practice, compared with the components shown inFigure 3A Two or more components shown in may be implemented within a single component, or Figure 3A a single component shown in may be implemented as multiple distributed components. Additionally or alternatively, a set of components (e.g., one or more components) of circuit system 300A may perform one or more functions described as being performed by another set of components of circuit system 300A.

[0088] Figure 3B Circuit system 300B is shown in accordance with one or more implementations. Circuit system 300B may be similar to circuit system 300A described in connection with Figure 3A , except that first comparator circuit 318 and second comparator circuit 330 are current comparators. Accordingly, current sources 336 and 338 are provided to provide reference currents as thresholds Th1 and Th2, respectively. Additionally, first comparator circuit 318 and second comparator circuit 330 are configured to receive a sense current Isense corresponding to capacitor current Icap.

[0089] When a short circuit event occurs, the short circuit event is configured to induce a voltage transient of phase voltage VS at the phase node and cause sense current Isense to satisfy first threshold Th1 or second threshold Th2 by making sense current Isense greater than first threshold Th1 or second threshold Th2. Since only one of transistors 208u or 209u is intended to be turned on at a time, only the sense circuit that detects the conduction state of the corresponding transistor detects the short circuit event.

[0090] As described above, Figure 3B is provided only as an example. Other examples may be different from the examples described with respect to Figure 3B . Figure 3B The number and arrangement of components shown in are provided as an example. In practice, circuit system 300B may include additional components, fewer components, different components, or components with a different arrangement compared to the components shown in Figure 3B . Figure 3B Two or more components shown in may be implemented within a single component, or Figure 3B a single component shown in may be implemented as multiple distributed components. Additionally or alternatively, a set of components (e.g., one or more components) of circuit system 300B may perform one or more functions described as being performed by another set of components of circuit system 300B.

[0091] Figure 4A signal diagram 400 showing normal operating conditions according to one or more implementations is shown. The signal diagram 400 shows signals for the phase voltage VS, the high-side floating output voltage at the output terminal HO, the low-side output voltage at the output terminal LO, the first sensed voltage HVsense, the second sensed voltage LVsense, the detector output Out1, and the second detector output Out2. Sensing of a short-circuit event can occur within 1 μs (such as on the order of 100 ns).

[0092] In addition, when the high-side transistor 208u is turned on, the high-side floating output voltage at the output terminal HO is high, and when the high-side transistor 208u is turned off, the high-side floating output voltage at the output terminal HO is low. When the low-side transistor 209u is turned on, the low-side output voltage at the output terminal LO is high, and when the low-side transistor 209u is turned off, the low-side output voltage at the output terminal LO is low. Both the detector output Out1 and the second detector output Out2 remain low, which means that no short-circuit event is detected. For example, when the high-side floating output voltage at the output terminal HO is high (e.g., when the high-side transistor 208u is in the on state), the first sensed voltage HVsense does not exceed the first threshold Th1 at the same time. Therefore, when the high-side transistor 208u is in the on state, there is no short-circuit event, and the detector output Out1 remains low. Similarly, when the low-side output voltage at the output terminal LO is high (e.g., when the low-side transistor 209u is in the on state), the second sensed voltage LVsense does not exceed the second threshold Th2 at the same time. Therefore, when the low-side transistor 209u is in the on state, there is no short-circuit event, and the detector output Out2 remains low.

[0093] Window 401 shows a magnified view of a part of signal diagram 400. For example, the normal operation of the second sense voltage LVsense is shown. The steady state of the second sense voltage LVsense can be equal to the second internal positive supply voltage Vdd_LS. Therefore, since the second threshold Th2 is greater than the second internal positive supply voltage Vdd_LS, the second threshold Th2 can be used to detect a short - circuit event corresponding to the low - side transistor 209u. When a short - circuit event occurs, the second sense voltage LVsense may exceed the second threshold Th2. A short - circuit event corresponding to the low - side transistor 209u can be detected when two conditions are met, which include: when the second sense voltage LVsense exceeds the second threshold Th2; and when the low - side transistor 209u is in the on - state based on the PWM control signal LIN, which can include that the gate voltage of the low - side transistor 209 or the output terminal LO of the low - side transistor 209 indicates that the low - side transistor 209u is in the on - state. The detection of the short - circuit event can occur within 1 μs (such as on the order of 100 ns). In other words, the first short - circuit detector 322 and the second short - circuit detector 334 are configured to detect a short - circuit event within 1 μs after the corresponding short - circuit event occurs.

[0094] The steady state of the first sense voltage HVsense can be equal to the first internal positive supply voltage Vdd_HS. Therefore, since the first threshold Th1 is greater than the first internal positive supply voltage Vdd_HS, the first threshold Th1 can be used to detect a short - circuit event corresponding to the high - side transistor 208u. When a short - circuit event occurs, the first sense voltage HVsense may exceed the first threshold Th1. A short - circuit event corresponding to the high - side transistor 208u can be detected when two conditions are met, which include: when the first sense voltage HVsense exceeds the first threshold Th1; and when the high - side transistor 208u is in the on - state based on the PWM control signal HIN, which can include that the gate voltage of the high - side transistor 208u or the output terminal HO of the high - side transistor 208u indicates that the high - side transistor 208u is in the on - state.

[0095] As described above, Figure 4 is provided only as an example. Other examples may be different from the example regarding Figure 4 described.

[0096] Figure 5AShows an example 500A of a short - circuit condition according to one or more implementations. The short - circuit condition may occur across the high - side transistor 208u of the circuit system 300A. For example, the short - circuit condition may be caused by a converter breakdown, which can be detected by sensing a voltage spike of the voltage transient dV / dt of the phase voltage VS. The converter breakdown may occur when the phase voltage VS moves towards the positive DC - link power supply DC+ (e.g., increases towards the positive DC - link power supply DC+). In some cases, the short - circuit condition may cause the two load terminals of the transistor to be short - circuited together. Other short - circuit conditions may cause the voltage transient dV / dt of the phase voltage VS to occur at a time when the voltage transient dV / dt of the phase voltage VS would not occur during the normal operation of the circuit system 300A (e.g., when a short - circuit occurs at the load).

[0097] As described above, Figure 5A is provided only as an example. Other examples may be different from the example regarding Figure 5A described.

[0098] Figure 5B Shows a signal diagram 500B of a short - circuit condition according to one or more implementations. The short - circuit condition may correspond to the converter breakdown shown in example 500A. The signal diagram 500B shows signals for the phase voltage VS, the high - side floating output voltage at the output terminal HO, the low - side output voltage at the output terminal LO, the first sensed voltage HVsense, the second sensed voltage LVsense, the detector output Out1, and the second detector output Out2. Sensing of the short - circuit event can occur within 1 μs (such as on the order of 100 ns).

[0099] Although the short - circuit condition occurs across the high - side transistor 208u, the short - circuit condition can also be detected when the low - side transistor 209u is in the on state. For example, when the low - side transistor 209u is turned on, the phase voltage VS is pulled to the DC - link negative power supply DC - (e.g., ground). However, due to the short - circuit condition across the high - side transistor 208u, the phase voltage VS is pulled back up to the DC - link positive power supply DC+ because of the short - circuit condition, rather than being continuously pulled down to the DC - link negative power supply DC -. When the low - side transistor 209u is in the on state, an unexpected voltage transient dV / dt occurs at the phase voltage VS towards the DC - link positive power supply DC+. This unexpected voltage transient dV / dt causes the second sensed voltage LVsense to exceed the second threshold Th2 when the low - side transistor 209u is in the on state, and the second short - circuit detector 334 can detect this as a short - circuit event. In some implementations, the second sensing circuit 306 can include a debounce filter that filters out short transients of the second detector output Out2 based on a time threshold. For example, the second short - circuit detector 334 can include a debounce filter. The detection of the short - circuit event can occur within 1 μs (such as on the order of 100 ns). In other words, the first short - circuit detector 322 and the second short - circuit detector 334 are configured to detect a short - circuit event within 1 μs after the corresponding short - circuit event occurs.

[0100] In some cases, the short - circuit condition can be detected when the high - side transistor 208u is in a stable on state or when the low - side transistor 209u is in a stable on state.

[0101] Window 501 shows an enlarged view of a portion of the signal graph 500B. For example, since the second sensed voltage LVsense exceeds the second threshold Th2 when the low - side transistor 209u is in the on state, the second detector output Out2 indicates that a short - circuit condition has occurred.

[0102] As described above, Figure 5B is provided only as an example. Other examples may be different from the example regarding Figure 5B described.

[0103] Figure 6AShows an example 600 of a short - circuit condition according to one or more implementations. The short - circuit condition may occur across the low - side transistor 209u of the circuit system 300A. For example, the short - circuit condition may be caused by a phase - to - ground condition, which can be detected by sensing a voltage spike of the voltage transient dV / dt of the phase voltage VS. The phase - to - ground condition may occur when the phase voltage VS moves towards the DC - link negative power supply DC - (e.g., decreases towards the DC - link negative power supply DC -). In some cases, the short - circuit condition may cause the two load terminals of the transistor to be short - circuited together. Other short - circuit conditions may cause the voltage transient dV / dt of the phase voltage VS to occur at a time when the voltage transient dV / dt of the phase voltage VS would not occur during the normal operation of the circuit system 300A (e.g., when a short - circuit occurs at the load).

[0104] As described above, Figure 6A is provided only as an example. Other examples may be different from the example regarding Figure 6A described.

[0105] Figure 6B Shows a signal diagram 600B of a short - circuit condition according to one or more implementations. The short - circuit condition may correspond to the phase - to - ground condition shown in example 600A. The signal diagram 600B shows signals for the phase voltage VS, the high - side floating output voltage at the output terminal HO, the low - side output voltage at the output terminal LO, the first sensed voltage HVsense, the second sensed voltage LVsense, the detector output Out1, and the second detector output Out2. Sensing of the short - circuit event can occur within 1 μs (such as on the order of 100 ns).

[0106] Although the short - circuit condition occurs across the low - side transistor 209u, the short - circuit condition can also be detected when the high - side transistor 208u is in the on state. For example, when the high - side transistor 208u is turned on, the phase voltage VS is pulled to the positive DC - link power supply DC+. However, due to the short - circuit condition across the low - side transistor 209u, the phase voltage VS is pulled back down to the negative DC - link power supply DC - due to the short - circuit condition, rather than being further pulled towards the positive DC - link power supply DC+. When the high - side transistor 208u is in the on state, an unexpected voltage transient dV / dt occurs at the phase voltage VS towards the negative DC - link power supply DC -. This unexpected voltage transient dV / dt causes the first sensed voltage HVsense to exceed the first threshold Th1 when the high - side transistor 208u is in the on state, and the first short - circuit detector 322 can detect this as a short - circuit event. In some implementations, the first sensing circuit 304 can include a debounce filter that filters out short transients of the first detector output Out1 based on a time threshold. For example, the first short - circuit detector 322 can include a debounce filter. The detection of the short - circuit event can occur within 1 μs (such as on the order of 100 ns). In other words, the first short - circuit detector 322 and the second short - circuit detector 334 are configured to detect a short - circuit event within 1 μs after the corresponding short - circuit event occurs.

[0107] In some cases, the short - circuit condition can be detected when the high - side transistor 208u is in a stable on state or when the low - side transistor 209u is in a stable on state.

[0108] As described above, Figure 6B is provided only as an example. Other examples may be different from the example regarding Figure 6B described.

[0109] Figure 7 is a schematic block diagram of a dV / dt sensing and gate - drive system 700 according to one or more embodiments. The dV / dt sensing and gate - drive system 700 can include a monolithic gate - driver IC 702 having two independent voltage islands corresponding to two isolated voltage domains. The dV / dt sensing and gate - drive system 700 can be similar to the gate - driver system 200 described in connection with Figure 2 but can also include circuitry configured to monitor the voltage transient dV / dt at the phase - node terminal and detect short - circuit events in more detail. For example, the first sensing circuit 304 can be disposed in the high - side gate driver 220, and the second sensing circuit 306 can be disposed in the low - side gate driver 210. Additionally, a sensing capacitor 704 can be connected between the first sensing circuit 304 and the second sensing circuit 306 such that the sensing capacitor 704 is cross - coupled to the high - side and low - side regions of the monolithic gate - driver IC 702. The sensing capacitor 704 can correspond to theFigure 3A the capacitor HVC in the described circuit system 300A or in combination with Figure 3B the capacitor HVC in the described circuit system 300B. In some implementations, an optional sense capacitor 706 may be arranged in series with the sense capacitor 704. Accordingly, the monolithic gate driver IC 702 includes at least one of the sense capacitors 704 and / or 706 coupled to an input node (e.g., a first sense node 308) of the first sense circuit 304 and an input node (e.g., a second sense node 310) of the second sense circuit 306.

[0110] The first sense circuit 304 and the second sense circuit 306 may be configured to sense a voltage transient dV / dt of the phase voltage VS at the phase node terminal 302 for detecting a short circuit event.

[0111] Specifically, the first sense circuit 304 and the second sense circuit 306 may use the sense capacitor 704 to measure the slope of dV / dt in an analog manner. Then the measured slope may be used to detect a short circuit event.

[0112] The dV / dt sensing and gate drive system 700 may further include a DC link power supply 708 (VDC), a low-side gate driver power supply 710 (VL), a high-side gate driver power supply 712 (VH), a decoupling capacitor 714 (e.g., a bootstrap capacitor) coupled in parallel to the low-side gate driver power supply 710, a decoupling capacitor 716 (e.g., a bootstrap capacitor) coupled in parallel to the high-side gate driver power supply 712, and a resistor R providing a path for current flow. The voltage VH may be equal to VB - VS, and the voltage VL may be equal to VCC - VSS (e.g., VCC - GND).

[0113] The monolithic gate driver IC 702 may include a PWM logic unit 225 that includes circuitry for processing signals HIN and LIN received from a microcontroller via pins and also forwarding PWM control signals from the microcontroller to the low-side gate driver 210 and the high-side gate driver 220. The PWM control signal going to the high-side gate driver 220 may be passed through a level shifter 230 above an isolation region isolating the high-side region and the low-side region.

[0114] The sense capacitor 704 and the optional sense capacitor 706 are substantially linear such that the voltage is proportional to the charge stored therein. The sense capacitor 704 and the optional sense capacitor 706 may be placed across two voltage domains and may be external to the monolithic gate driver IC 702 or may be integrated in the monolithic gate driver IC 702 to measure the voltage slope of the voltage transient dV / dt.

[0115] Both the first sensing circuit 304 and the second sensing circuit 306 can use the sensing capacitor 704 to measure the slope of dV / dt, and can use the measured slope to detect a short circuit event that causes an unexpected voltage transient dV / dt. The sensing capacitor 704 can be arranged in two sensing paths (including the first sensing path and the second sensing path). The first sensing path can include a first end and a second end. The first sensing path can be coupled to the collector or drain of the high-side transistor 208u at the first end, and coupled to the emitter or source of the high-side transistor 208u at the second end. The first sensing path can enable the sensing capacitor 704 to sense the voltage transient of the high-side transistor 208u (e.g., V DS ) of the high-side transistor 208u, which is proportional to the phase voltage VS.

[0116] The first sensing path from the source to the drain of the high-side transistor 208u can include: starting at the source of the high-side transistor 208u (e.g., at the phase node), continuing through the high-side gate driver power supply 712 or the decoupling capacitor 716 to VB, continuing from VB to the first sensing node 308, and continuing through the sensing capacitor 704 to the second sensing node 310. Starting from the second sensing node 310, the first sensing path continues through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VSS, and continues through the DC link power supply 708 to DC+, and DC+ is equivalent to the drain of the high-side transistor 208u.

[0117] The second sensing path can include a third end and a fourth end. The third end can be coupled to the collector or drain of the low-side transistor 209u, and the fourth end can be coupled to the emitter or source of the low-side transistor 209u. The second sensing path can enable the sensing capacitor 704 to sense the voltage transient of the low-side transistor 209u (e.g., V DS ) of the low-side transistor 209u, which is proportional to the phase voltage VS. The second sensing path from the source to the drain of the low-side transistor 209u can include: starting at the source (DC- or VSS) of the low-side transistor 209u, continuing through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VCC, continuing from VCC to the second sensing node 310, and continuing through the sensing capacitor 704 to the first sensing node 308. Starting from the first sensing node 308, the second sensing path continues through the high-side gate driver power supply 712 or the decoupling capacitor 716 to VS, and VS is equivalent to the drain of the low-side transistor 209u. Therefore, the sensing capacitor 704 can be indirectly coupled to the collector or drain and the emitter or source of the high-side transistor 208u, and can be indirectly coupled to the collector or drain and the emitter or source of the low-side transistor 209u.

[0118] As described above, Figure 7 is provided only as an example. Other examples may be different from the example Figure 7 described.

[0119] Figure 8 is a schematic block diagram of a dV / dt sensing and gate drive system 800 according to one or more embodiments. The dV / dt sensing and gate drive system 800 may include a monolithic gate driver IC 802 having two independent voltage islands corresponding to two isolated voltage domains. The dV / dt sensing and gate drive system 800 may be similar to the dV / dt sensing and gate drive system 700 described in connection with Figure 7 except that the sense capacitors 704 and 706 are arranged in different paths. For example, the sense capacitor 704 may correspond to the first sensing circuit 304, and the sense capacitor 706 may correspond to the second sensing circuit 306. The sense capacitor 704 may be coupled to the input node (e.g., the first sense node 308) of the first sensing circuit 304 and the reference node (e.g., VSS) of the low-side region. The sense capacitor 706 may be coupled to the input node (e.g., the second sense node 310) of the second sensing circuit 306 and the floating reference node (e.g., VS) of the high-side region.

[0120] The sense capacitor 704 may be arranged in the first sensing path, and the sense capacitor 706 may be arranged in the second sensing path. The first sensing path may include a first end and a second end. The first sensing path may be coupled to the collector or drain of the high-side transistor 208u at the first end and to the emitter or source of the high-side transistor 208u at the second end. The first sensing path may enable the sense capacitor 704 to sense the voltage transient (e.g., the V DS ) of the high-side transistor 208u, which is proportional to the phase voltage VS. The first sensing path from the source to the drain of the high-side transistor 208u may include: starting at the source of the high-side transistor 208u (e.g., at the phase node), continuing through the high-side gate driver power supply 712 or the decoupling capacitor 716 to VB, continuing from VB to the first sense node 308, continuing through the sense capacitor 704 to VSS, and continuing through the DC link power supply 708 to DC+, where DC+ is equivalent to the drain of the high-side transistor 208u. Thus, the sense capacitor 704 may be indirectly coupled to the collector or drain and the emitter or source of the high-side transistor 208u.

[0121] The second sensing path may include a third terminal and a fourth terminal. The third terminal may be coupled to the collector or drain of the low-side transistor 209u, and the fourth terminal may be coupled to the emitter or source of the low-side transistor 209u. The second sensing path may enable the sensing capacitor 706 to sense a voltage transient of the low-side transistor 209u (e.g., V DS ) of the low-side transistor 209u, which is proportional to the phase voltage VS. The second sensing path from the source to the drain of the low-side transistor 209u may include: starting at the source of the low-side transistor 209u (DC- or VSS), continuing through the low-side gate driver power supply 710 or the decoupling capacitor 714 to VCC, continuing from VCC to the second sensing node 310, continuing through the sensing capacitor 706 to VS, where VS is equivalent to the drain of the low-side transistor 209u. Thus, the sensing capacitor 706 may be indirectly coupled to the collector or drain and the emitter or source of the low-side transistor 209u.

[0122] As described above, Figure 8 is provided only as an example. Other examples may be different from the example described with respect to Figure 8 the example described.

[0123] An overview of some aspects of the present disclosure is provided below:

[0124] Aspect 1: A gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensing voltage representative of a voltage transient of the power switch; a comparator circuit configured to compare the sensing voltage with a threshold and further configured to generate a comparison result based on whether the sensing voltage meets the threshold; and a short-circuit detector configured to detect a short-circuit event based on the on state of the power switch being detected and based on the comparison result indicating that the sensing voltage meets the threshold.

[0125] Aspect 2: The gate driver circuit according to aspect 1, further comprising: a state detector circuit configured to detect the switching state of the power switch and indicate to the short-circuit detector that the power switch is in the on state or indicate that the power switch is in the off state, wherein the short-circuit detector is configured to detect a short-circuit event based on the state detector circuit indicating that the power switch is in the on state.

[0126] Aspect 3: The gate driver circuit according to any one of aspects 1 to 2, wherein the short-circuit event induces a voltage transient, and the sensing voltage meets the threshold by making the sensing voltage greater than the threshold.

[0127] Aspect 4: The gate driver circuit according to any one of Aspects 1 to 3, wherein the gate driver is configured to be coupled to an internal positive supply voltage and an internal ground voltage, wherein the gate driver is configured to drive a power switch between an on state and an off state using the internal positive supply voltage and the internal ground voltage, and wherein the threshold is greater than the internal positive supply voltage.

[0128] Aspect 5: The gate driver circuit according to any one of Aspects 1 to 4, wherein the short - circuit detector is configured to: in response to detecting a short - circuit event, trigger the power switch to be set to the off state.

[0129] Aspect 6: The gate driver circuit according to any one of Aspects 1 to 5, wherein at least one capacitor is configured to sense a voltage transient and provide a capacitor current proportional to the slope of the voltage transient, and wherein the capacitor current is configured to generate a sense voltage at a sense node of the sensing circuit.

[0130] Aspect 7: The gate driver circuit according to Aspect 6, wherein the voltage transient corresponds to the voltage across the power switch, wherein the voltage across the power switch is a drain - source voltage or a collector - emitter voltage, and wherein the capacitor current is based on the rate of change of the voltage across the power switch.

[0131] Aspect 8: The gate driver circuit according to any one of Aspects 1 to 7, wherein: the power switch is a high - side power switch, the gate driver and the sensing circuit are disposed in the high - side region, and at least one capacitor is coupled to an input node of the sensing circuit and a reference node of the low - side region.

[0132] Aspect 9: The gate driver circuit according to any one of Aspects 1 to 8, further comprising: a sensing path having a first end and a second end, wherein the sensing path is coupled to the collector or drain of the power switch at the first end and to the emitter or source of the power switch at the second end, and wherein at least one capacitor is disposed in the sensing path.

[0133] Aspect 10: The gate driver circuit according to Aspect 9, wherein at least one capacitor is indirectly coupled to the collector or drain of the power switch.

[0134] Aspect 11: The gate driver circuit according to any one of Aspects 1 to 10, wherein: the power switch is a low - side power switch, the gate driver and the sensing circuit are disposed in the low - side region, and at least one capacitor is coupled to an input node of the sensing circuit and a floating reference node of the high - side region.

[0135] Aspect 12: A half-bridge gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a first gate driver arranged in the high-side region and configured to drive a high-side power switch between an on state and an off state; a second gate driver arranged in the low-side region and configured to drive a low-side power switch between an on state and an off state; a phase node terminal coupled to or configured to be coupled to a phase node coupled to the high-side power switch and the low-side power switch; at least one capacitor cross-coupled between the high-side region and the low-side region; a first sensing circuit arranged in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and configured to provide a first sensed value representing a voltage transient of a phase voltage present at the phase node; a second sensing circuit arranged in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and configured to provide a second sensed value representing the voltage transient; a first comparator circuit configured to compare the first sensed value with a first threshold and further configured to generate a first comparison result based on whether the first sensed value meets the first threshold; a second comparator circuit configured to compare the second sensed value with a second threshold and further configured to generate a second comparison result based on whether the second sensed value meets the second threshold; a first short-circuit detector configured to detect a first short-circuit event based on the on state of the high-side power switch being detected and based on the first comparison result indicating that the first sensed value meets the first threshold; and a second short-circuit detector configured to detect a second short-circuit event based on the on state of the low-side power switch being detected and based on the second comparison result indicating that the second sensed value meets the second threshold, wherein the first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.

[0136] Aspect 13: The half-bridge gate driver circuit according to aspect 12, wherein in the case where the high-side power switch is turned on by the first gate driver, the phase node terminal is configured to be connected to a high-side supply potential through the high-side power switch, and wherein in the case where the low-side power switch is turned on by the second gate driver, the phase node terminal is configured to be connected to a low-side supply potential through the low-side power switch.

[0137] Aspect 14: The half-bridge gate driver circuit according to any one of aspects 12 to 13, wherein the first short-circuit event induces a voltage transient, and the first sensed value meets the first threshold by making the first sensed value greater than the first threshold, and wherein the second short-circuit event induces a voltage transient, and the second sensed value meets the second threshold by making the second sensed value greater than the second threshold.

[0138] Aspect 15: The half-bridge gate driver circuit according to any one of Aspects 12 to 14, wherein the first gate driver is configured to be coupled to a first internal positive supply voltage and a first internal ground voltage, wherein the second gate driver is configured to be coupled to a second internal positive supply voltage and a second internal ground voltage, wherein the first gate driver is configured to drive the high-side power switch between an on state and an off state using the first internal positive supply voltage and the first internal ground voltage, wherein the second gate driver is configured to drive the low-side power switch between an on state and an off state using the second internal positive supply voltage and the second internal ground voltage, wherein the first threshold is greater than the first internal positive supply voltage, and wherein the second threshold is greater than the second internal positive supply voltage.

[0139] Aspect 16: The half-bridge gate driver circuit according to any one of Aspects 12 to 15, wherein the first short-circuit detector is configured to: in response to detecting a first short-circuit event, trigger the high-side power switch to be set to an off state, and wherein the second short-circuit detector is configured to: in response to detecting a second short-circuit event, trigger the low-side power switch to be set to an off state.

[0140] Aspect 17: The half-bridge gate driver circuit according to any one of Aspects 12 to 16, wherein: a first corresponding capacitor is coupled to the input node of the first sensing circuit and the reference node of the low-side region, and a second corresponding capacitor is coupled to the input node of the second sensing circuit and the floating reference node of the high-side region.

[0141] Aspect 18: The half-bridge gate driver circuit according to any one of Aspects 12 to 17, further comprising: a first sensing path including a first end and a second end, wherein the first sensing path is coupled to the collector or drain of the high-side power switch at the first end and to the emitter or source of the high-side power switch at the second end, wherein the first corresponding capacitor is arranged in the first sensing path, and a second sensing path including a third end and a fourth end, wherein the second sensing path is coupled to the collector or drain of the low-side power switch at the third end and to the emitter or source of the low-side power switch at the fourth end, wherein the second corresponding capacitor is arranged in the second sensing path.

[0142] Aspect 19: The half-bridge gate driver circuit according to any one of Aspects 12 to 18, wherein at least one capacitor is coupled to the input node of the first sensing circuit and the input node of the second sensing circuit.

[0143] Aspect 20: A method for detecting a short circuit, comprising: generating, by a gate driver in a gate driver circuit, a drive signal configured to drive a power switch between an on state and an off state; sensing, by a capacitor, a voltage transient across the power switch, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to the slope of the voltage transient; generating, at a sense node coupled to the capacitor, a sensed value based on the capacitor current, wherein the sensed value is proportional to the slope of the voltage transient; generating, by a state detector circuit, a state signal indicating whether the power switch is set to the on state or the off state by the gate driver; comparing, by a comparator circuit, the sensed value with a threshold to generate a comparison result indicating whether the sensed value meets the threshold; and detecting, by a short circuit detector, a short circuit based on the state signal indicating that the power switch is set to the on state and based on the comparison result indicating that the sensed value meets the threshold.

[0144] Aspect 21: A gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region such that the at least one capacitor is configured to sense a voltage transient across the power switch and provide a capacitor current proportional to the slope of the voltage transient; a sensing circuit configured to receive the capacitor current and provide a sensed current corresponding to the capacitor current; a comparator circuit configured to compare the sensed current with a threshold and generate a comparison result based on whether the sensed current meets the threshold; and a short circuit detector configured to detect a short circuit event based on detecting the on state of the power switch and based on the comparison result indicating that the sensed current meets the threshold.

[0145] Aspect 22: A system configured to perform one or more operations described in one or more of Aspects 1 to 21.

[0146] Aspect 23: An apparatus comprising means for performing one or more operations described in one or more of Aspects 1 to 21.

[0147] Aspect 24: A non-transitory computer-readable medium storing an instruction set, the instruction set including one or more instructions that, when executed by a device, cause the device to perform one or more operations described in one or more of Aspects 1 to 21.

[0148] Aspect 25: A computer program product comprising instructions or code for performing one or more operations described in one or more of Aspects 1 to 21.

[0149] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure, or may be acquired from practice of the implementations.

[0150] Some implementations may be described herein in connection with thresholds. As used herein, "meeting" a threshold may mean that a value is greater than, exceeds, is higher than, is greater than or equal to, is less than, is fewer than, is lower than, is less than or equal to, or is equal to the threshold, etc.

[0151] As used herein, the term "component" is intended to be broadly construed as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein may be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual specific control hardware or software code used to implement these systems and / or methods does not limit the implementations. Thus, the operations and behaviors of the systems and / or methods are described herein without reference to specific software code, and it should be understood that the software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0152] Any processing component may be implemented as a central processing unit (CPU) or other processor that reads and executes a software program from a non-transitory computer-readable recording medium such as a hard disk or a semiconductor memory device. For example, instructions may be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general microprocessors, application specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor" as used herein refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. The software may be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes program code or program algorithms stored thereon that, when executed, cause the processor to perform the steps of the method via a computer program.

[0153] A controller including hardware may also perform one or more of the techniques in the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its receiving, analyzing, and controlling functions, which may also include correction functions. Such hardware, software, and firmware may be implemented within the same device or in separate devices to support the various techniques described in the present disclosure.

[0154] A signal processing circuit and / or a signal conditioning circuit may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive additional information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal in such a way that the signal meets the requirements of a next stage for further processing. Signal conditioning may include converting from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, transformation, biasing, range matching, isolation, and any other processing required to make the signal suitable for processing after conditioning.

[0155] Although specific feature combinations are recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementations described herein. Many of these features may be combined in ways not specifically recited in the claims and / or not disclosed in the specification. For example, the present disclosure includes each dependent claim in a claim set combined with each other independent claim in the claim set and each combination of multiple claims in the claim set. As used herein, a phrase referring to "at least one" in a list of items means any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to cover a, b, c, a and b, a and c, b and c, and a, b, and c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other order of a, b, and c).

[0156] Furthermore, it should be understood that the disclosure of multiple acts or functions in the specification or claims may not be construed as being in a particular order. Thus, the disclosure of multiple acts or functions does not limit these acts or functions to a particular order, unless these acts or functions are non-interchangeable for technical reasons. Additionally, in some implementations, a single act may include multiple sub-acts or may be decomposed into multiple sub-acts. Such sub-acts may be included and are part of the disclosure of the single act, unless explicitly excluded.

[0157] Unless expressly so stated, no element, act, or instruction used herein shall be construed as critical or essential. Additionally, as used herein, the articles "a" and "an" are intended to include one or more items and may be used interchangeably with "one or more." Further, as used herein, the article "the" is intended to include one or more items referred to in conjunction with the article "the" and may be used interchangeably with "one or more." In cases where only one item is intended, the phrases "only one," "single," or similar language is used. Additionally, as used herein, the terms "has," "have," "having," etc. are intended to be open-ended terms with respect to the elements they modify (e.g., an element "having" A may also have B). Further, unless expressly stated otherwise, the phrase "based on" is intended to mean "at least partially based on." As used herein, the term "multiple" may be replaced with "a plurality of," and vice versa. Additionally, as used herein, unless expressly stated otherwise (e.g., when used in conjunction with "either" or "only one of"), the term "or" when used in a series is intended to be inclusive and may be used interchangeably with "and / or."

Claims

1. A gate driver circuit, comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive the power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sensing voltage representative of a voltage transient of the power switch; a comparator circuit configured to compare the sense voltage with a threshold value, and further configured to generate a comparison result based on whether the sense voltage satisfies the threshold value; as well as A short circuit detector is configured to detect a short circuit event based on the conductive state of the power switch being detected and based on the comparison result indicating that the sense voltage satisfies the threshold.

2. The gate driver circuit according to claim 1, further comprising: a state detector circuit configured to detect a switching state of the power switch and indicate to the short-circuit detector that the power switch is in the on-state or that the power switch is in the off-state, Wherein the short circuit detector is configured to detect the short circuit event based on the state detector circuit indicating that the power switch is in the on state.

3. The gate driver circuit according to claim 1, wherein: The short circuit event induces the voltage transient, and the sense voltage satisfies the threshold by causing the sense voltage to be greater than the threshold.

4. The gate driver circuit according to claim 1, wherein: The gate driver is configured to be coupled to an internal positive supply voltage and an internal ground voltage, wherein the gate driver is configured to drive the power switch between the on-state and the off-state using the internal positive supply voltage and the internal ground voltage, and Wherein, the threshold is greater than the internal positive supply voltage.

5. The gate driver circuit according to claim 1, wherein: The short circuit detector is configured to, in response to detecting the short circuit event, trigger the power switch to be set in the off state.

6. The gate driver circuit according to claim 1, wherein: The at least one capacitor is configured to sense the voltage transient and provide a capacitor current proportional to the slope of the voltage transient, and Wherein, the capacitor current is configured to generate the sensing voltage at a sensing node of the sensing circuit.

7. The gate driver circuit according to claim 6, wherein: The voltage transient corresponds to the voltage across the power switch, Wherein, the voltage across the power switch is a drain-source voltage or a collector-emitter voltage, and The capacitor current is based on a rate of change of a voltage across the power switch.

8. The gate driver circuit according to claim 1, wherein: The power switch is a high-side power switch, The gate driver and the sensing circuit are disposed in the high-side region, and The at least one capacitor is coupled to an input node of the sensing circuit and a reference node of the low-side region.

9. The gate driver circuit according to claim 1, further comprising: a sensing path including a first end and a second end, wherein the sensing path is coupled to a collector or a drain of the power switch at the first end and is coupled to an emitter or a source of the power switch at the second end, and Therein, the at least one capacitor is arranged in the sensing path.

10. The gate driver circuit according to claim 9, wherein: The at least one capacitor is indirectly coupled to the collector or drain of the power switch.

11. The gate driver circuit according to claim 1, wherein: The power switch is a low-side power switch, The gate driver and the sensing circuit are disposed in the low-side region, and The at least one capacitor is coupled to an input node of the sensing circuit and a floating reference node of the high-side region.

12. A half-bridge gate driver circuit comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a first gate driver disposed in the high-side region and configured to drive the high-side power switch between an on-state and an off-state; a second gate driver disposed in the low-side region and configured to drive the low-side power switch between an on-state and an off-state; a phase node terminal coupled to or configured to be coupled to a phase node coupled to the high-side power switch and the low-side power switch; at least one capacitor cross-coupled to the high-side region and the low-side region; a first sensing circuit disposed in the high-side region, wherein the first sensing circuit is coupled to a first corresponding capacitor of the at least one capacitor and is configured to provide a first sensed value representative of a voltage transient of a phase voltage present at the phase node; a second sensing circuit disposed in the low-side region, wherein the second sensing circuit is coupled to a second corresponding capacitor of the at least one capacitor and is configured to provide a second sensed value representative of the voltage transient; a first comparator circuit configured to compare the first sensed value with a first threshold value, and further configured to generate a first comparison result based on whether the first sensed value satisfies the first threshold value; a second comparator circuit configured to compare the second sensed value with a second threshold value, and further configured to generate a second comparison result based on whether the second sensed value satisfies the second threshold value; a first short circuit detector configured to detect a first short circuit event based on the on-state of the high-side power switch being detected and based on the first comparison result indicating that the first sensed value satisfies the first threshold; and a second short circuit detector configured to detect a second short circuit event based on the on-state of the low-side power switch being detected and based on the second comparison result indicating that the second sensed value satisfies the second threshold, The first corresponding capacitor and the second corresponding capacitor are the same capacitor or different capacitors.

13. The half-bridge gate driver circuit according to claim 12, wherein: In case the high-side power switch is turned on by the first gate driver, the phase node terminal is configured to be connected to a high-side supply potential through the high-side power switch, and wherein in case the low-side power switch is turned on by the second gate driver, the phase node terminal is configured to be connected to a low-side supply potential through the low-side power switch.

14. The half-bridge gate driver circuit according to claim 12, wherein: The first short circuit event induces the voltage transient, and the first sensed value satisfies the first threshold by making the first sensed value greater than the first threshold, and The second short circuit event induces the voltage transient, and the second sensed value satisfies the second threshold by making the second sensed value greater than the second threshold.

15. The half-bridge gate driver circuit according to claim 12, wherein: The first gate driver is configured to be coupled to a first internal positive supply voltage and a first internal ground voltage, wherein the second gate driver is configured to be coupled to a second internal positive supply voltage and a second internal ground voltage, wherein the first gate driver is configured to drive the high-side power switch between the on-state and the off-state using the first internal positive supply voltage and the first internal ground voltage, wherein the second gate driver is configured to drive the low-side power switch between the on-state and the off-state using the second internal positive supply voltage and the second internal ground voltage, wherein the first threshold is greater than the first internal positive supply voltage, and Wherein, the second threshold is greater than the second internal positive supply voltage.

16. The half-bridge gate driver circuit according to claim 12, wherein: The first short circuit detector is configured to: in response to detecting the first short circuit event, trigger the high-side power switch to be set to the off state, and The second short-circuit detector is configured to: in response to detecting the second short-circuit event, trigger the low-side power switch to be set to the off state.

17. The half-bridge gate driver circuit of claim 12, wherein: The first corresponding capacitor is coupled to an input node of the first sensing circuit and a reference node of the low-side region, and The second corresponding capacitor is coupled to an input node of the second sensing circuit and a floating reference node of the high-side region.

18. The half-bridge gate driver circuit of claim 12, further comprising: a first sensing path including a first end and a second end, wherein the first sensing path is coupled to a collector or a drain of the high-side power switch at the first end and is coupled to an emitter or a source of the high-side power switch at the second end, wherein the first corresponding capacitor is arranged in the first sensing path, and A second sensing path comprising a third terminal and a fourth terminal, wherein the second sensing path is coupled to the collector or drain of the low-side power switch at the third terminal and is coupled to the emitter or source of the low-side power switch at the fourth terminal, wherein the second corresponding capacitor is arranged in the second sensing path.

19. The half-bridge gate driver circuit of claim 12, wherein: The at least one capacitor is coupled to an input node of the first sensing circuit and an input node of the second sensing circuit.

20. A method for detecting a short circuit, comprising: generating a drive signal by a gate driver in a gate driver circuit, the drive signal being configured to drive the power switch between an on state and an off state; sensing a voltage transient of a voltage across the power switch by a capacitor, wherein the capacitor is cross-coupled to a high-side region and a low-side region of the gate driver circuit such that the capacitor is configured to provide a capacitor current proportional to a slope of the voltage transient; generating a sense value based on the capacitor current at a sense node coupled to the capacitor, wherein the sense value is proportional to a slope of the voltage transient; generating, by a state detector circuit, a state signal indicating whether the power switch is set by the gate driver to be in the on state or the off state; comparing the sensed value with a threshold by a comparator circuit to generate a comparison result indicating whether the sensed value satisfies the threshold; and The short circuit is detected by a short circuit detector based on the state signal indicating that the power switch is set to the on state and based on the comparison result indicating that the sensed value satisfies the threshold value.

21. A gate driver circuit comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; a gate driver configured to drive the power switch between an on state and an off state; at least one capacitor cross-coupled to the high-side region and the low-side region such that the at least one capacitor is configured to sense a voltage transient of a voltage across the power switch and to provide a capacitor current proportional to a slope of the voltage transient; a sensing circuit configured to receive the capacitor current and provide a sensing current corresponding to the capacitor current; a comparator circuit configured to compare the sensed current with a threshold value and generate a comparison result based on whether the sensed current satisfies the threshold value; as well as A short circuit detector is configured to detect a short circuit event based on the conductive state of the power switch being detected and based on the comparison result indicating that the sense current satisfies the threshold.

22. A non-transitory computer readable medium storing an instruction set, the instruction set comprising one or more instructions, which when executed by a device causes the device to perform one or more operations of the method for detecting a short circuit according to claim 20.

23. A computer program product comprising instructions or codes for executing one or more operations of the method for detecting a short circuit according to claim 20.

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