Dynamic biasing circuit and method for radio frequency power amplifier

Abstract

The invention relates to the technical field of wireless digital communication, and particularly provides a dynamic bias circuit and method for a radio frequency power amplifier, the circuit comprises an LDO module and a dynamic control module, the LDO module adopts an operational amplifier AMP and a transistor MP, and the dynamic control module adopts a dynamic bias circuit. The dynamic control module adopts an OSC, a trigger group formed by connecting a plurality of first D triggers in series, a second D trigger and a third D trigger; according to the method, the output process of the radio frequency power amplifier is divided into nodes T0, T1, T2 and T3 according to the time relation, T0-T1 is a preheat stage, T1-T2 is a preheat stable stage, and T2-T3 is a post stage; according to the invention, the dynamic bias circuit is optimally designed, the two stages of preheating and post-heating are dynamically controlled by introducing preheat, and the vreg voltage is dynamically adjusted through the dynamic bias circuit, so that the flatness of the output power of the radio frequency power amplifier along with time is greatly improved, the error vector amplitude performance of the PA under the dynamic condition is improved, and the linear index of the PA is improved.

Description

Technical Field

[0001] The present invention relates to the field of wireless digital communication technologies, and particularly to a dynamic biasing circuit and method for a radio frequency power amplifier. Background Art

[0002] A radio frequency power amplifier is an essential key component in various wireless communication applications, and is used to amplify the power of the modulated radio frequency signal output by a transceiver to meet the power requirements of the radio frequency signal required for wireless communication.

[0003] In the wifi application of a radio frequency power amplifier PA, in order to reduce power consumption, it generally works in a time-sharing manner, works for a period of time and is silent for a period of time, and does not always remain in the radio frequency power transmission state. Because of this, the states of the PA at the initial stage of startup and during stable operation are different. Due to the existence of heat loss, there is a large difference between the temperature of the device at the initial stage of startup and the temperature of the device in the thermally stable state, which is manifested as a large difference in power gain and digital dynamic error vector magnitude (DEVM) between the initial stage of startup and the thermally stable state.

[0004] According to the length and size of data packets, the duration of PA transmission work is different. The transmission duration of a long packet is about 6 mS, and the application duration for the seventh-generation Wi-Fi wireless network technology wifi7 is even longer, while the transmission duration of a short packet is about 200 uS. For different transmission durations, the thermal states of the PA during operation are different. Due to the influence of the memory effect, the curve of the output power of the PA changing with time is not flat. When a general constant bias voltage or current is used as the PA bias, the relationship curves of the output power of the PA, the bias voltage Vreg, and time are as Figure 1a 、 1b shown. Vreg makes the PA work at time t0 and turns off the PA work at time t3. The output power of the PA changes with time, showing a process of first climbing and then decreasing. From time t0 - t1, Vreg biases the PA, and the ICC of the PA power transistor slowly increases, and the output power climbs; from time t1 - t2, the output power is approximately stable; from time t2 - t3, due to the fact that the PA power transistor works for a long time and generates more heat, the current gain multiple, gm, etc. of the power transistor decrease to a certain extent, and the output power slowly decreases with time, affecting the output power of the radio frequency power amplifier and the reliability of signal transmission. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a dynamic biasing circuit and method for a radio frequency power amplifier, which are used to solve the problem that the output power of the radio frequency power amplifier and the reliability of signal transmission are affected due to the existence of heat loss in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a dynamic bias circuit for a radio frequency power amplifier, and the circuit includes an LDO module and a dynamic control module;

[0007] The LDO module uses an operational amplifier AMP and a transistor MP. The inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, and the output terminal is connected to the base of the transistor MP. The emitter of the transistor MP is connected to a high level, and the collector is grounded; the LDO module further includes a preheating unit and a post-heating unit. The preheating unit uses a transistor M1_pre, the collector of the transistor M1_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP; the post-heating unit uses a transistor M1_pos, the collector of the transistor M1_pos is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP;

[0008] The vreg voltage of the PA is generated at the collector of the transistor MP;

[0009] The dynamic control module uses an OSC, a trigger group composed of several first D flip-flops connected in series, a second D flip-flop, and a third D flip-flop. The OSC is used to generate a periodic square wave signal, and the trigger group is used to stretch the clock cycle generated by the OSC to 2 n T, where T is time and n is the number of first D flip-flops connected in series; the D terminal of the second D flip-flop is connected to a high level, and the Q terminal outputs the preheat_off signal. The D terminal of the third D flip-flop is connected to a high level, and the Q terminal outputs the postheat_on signal. The second D flip-flop is connected in parallel to the first D flip-flop at the n / 2 position of the trigger group, and the third D flip-flop is connected in parallel to the first D flip-flop at the end of the trigger group.

[0010] In an embodiment of the present invention, a resistor R1 and a resistor R2 are connected to the collector of the transistor MP, and the non-inverting input terminal of the operational amplifier AMP is connected between the resistor R1 and the resistor R2.

[0011] In an embodiment of the present invention, the output voltage expression of the vreg voltage of the PA generated by the LDO module is as follows:

[0012] Vreg = Vref(R1 + R2) / R1+(is_pre + is_post)*R2

[0013] In an embodiment of the present invention, signals V1, V2, V3, V4, V5, and V6 exist in sequence in the trigger group. Signals V1, V2, and V3 respectively control the extraction of current is_pre in the preheat unit through a NOR gate; signals V4, V5, and V6 respectively control the extraction of current is_pos in the postheat unit through a NOR gate.

[0014] In an embodiment of the present invention, in the initial state, both the preheat_off signal and the postheat_on signal are 0.

[0015] In an embodiment of the present invention, a three-phase six-arm drive structure is adopted in both the preheat unit and the postheat unit. Each phase of the three-phase six-arm drive structure uses two MOS transistors. The emitter of the MOS transistor located in the upper arm in the same phase is connected to the collector of the MOS transistor located in the lower arm.

[0016] In an embodiment of the present invention, the duty cycle of the periodic square wave signal generated by the OSC is set to 50%.

[0017] A dynamic biasing method for a radio frequency power amplifier, including the dynamic biasing circuit for the radio frequency power amplifier, comprises the following steps:

[0018] S1. Divide the output process of the radio frequency power amplifier into nodes T0, T1, T2, and T3 according to the time relationship. T0 - T1 is the preheat stage, T1 - T2 is the preheat stable stage, and T2 - T3 is the postheat stage;

[0019] S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50%, and the period to T;

[0020] S3. Connect a number of first D flip - flops constituting the trigger group in a frequency - division - by - two form, so that the clock period of the square wave signal is stretched by 2 n times; that is, the period of V1 in the trigger group is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 covers the transmission time of the entire long data packet;

[0021] S4. At T0, both the preheat_off signal and the postheat_on signal are 0;

[0022] S5. During the T0 - T1 stage, V1, V2, and V3 in the trigger group control the three extraction currents is_pre in the preheat stage through a NOR gate; during the T1 - T2 stage, as the clock signal repeats periodically, V1, V2, and V3 in the trigger group form a long clock cycle loop, and the three extraction currents is_pre gradually decrease. At the end of the preheat stage, preheat_off is set high, causing en1_pre, en2_pre, and en3_pre to be set to 0, thereby closing the preheat stage; during the T2 - T3 stage, V4, V5, and V6 in the trigger group control the three extraction currents is_post in the postheat stage through a NOR gate; when the V6 signal does not jump, postheat_on remains 0, and the postheat stage is still working, and is_post increases successively; when the V6 signal jumps, postheat is set high, causing the postheat stage to be closed, thus completing the transmission of the entire data packet.

[0023] In an embodiment of the present invention, in step S5, since the input D terminal of the second D flip - flop related to preheat_off is connected to VDD, when the reset signal does not appear, the entire preheat stage is in a closed state, and the preheat stage will restart only when the next reset signal arrives, that is, the preheat stage will start again at the beginning of the next data packet transmission.

[0024] As described above, the dynamic bias circuit and method for a radio frequency power amplifier of the present invention have the following beneficial effects:

[0025] The present invention designs a dynamic vreg voltage biasing scheme. The output process of the radio frequency power amplifier is divided into nodes T0, T1, T2, and T3 according to the time relationship. In the t0 - t1 stage, which is called the preheat stage, the vreg voltage has a certain overshoot and gradually decays. This period generally lasts about 100uS and is used to compensate for the slow power ramp - up state at the initial stage of PA startup, thereby improving the flatness of the output power over time at the initial startup stage. In the t1 - t2 stage, the preheat overshoot disappears and the vreg is consistent with the biasing voltage in the thermal stable state. In the t2 - t3 stage, which is called the postheat stage, the vreg voltage slowly increases in this stage. The postheat stage mainly compensates for the decrease in current gain beta or transconductance gm caused by the thermal effect after the PA has been working for a certain time, thereby also improving the flatness of the output power over time during this period, preventing the power curve from dropping, enabling the radio frequency power amplifier to provide high - power output, and ensuring the reliability and stability of signal transmission. The present invention optimizes the design of the dynamic biasing circuit, introduces preheat to enable dynamic control in the two stages of preheat and postheat, and realizes the dynamic adjustment of the vreg voltage through the dynamic biasing circuit, greatly improving the flatness of the output power of the radio frequency power amplifier over time, improving the error vector magnitude performance of the PA under dynamic conditions, and enhancing the linearity index of the PA. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a It shows a curve graph of the output power of the PA versus time.

[0027] Figure 1b It shows a curve graph of the biasing voltage Vreg of the PA versus time.

[0028] Figure 2a It shows the circuit schematic diagram of the LDO module of the dynamic biasing circuit for the radio frequency power amplifier disclosed in the present invention.

[0029] Figure 21a It shows Figure 2a The enlarged view of the operational amplifier AMP and the transistor MP in

[0030] Figure 22a It shows Figure 2a The enlarged view of the preheat unit in

[0031] Figure 23a It shows Figure 2a The enlarged view of the postheat unit in

[0032] Figure 2b It shows the circuit schematic diagram of the dynamic control module of the dynamic biasing circuit for the radio frequency power amplifier disclosed in the present invention.

[0033] Figure 21b Shown as Figure 2b the partial enlarged view in

[0034] Figure 22b Shown as Figure 2b another partial enlarged view in

[0035] Figure 3a Shown as the relationship curve of the output power varying with time improved by using the dynamic biasing method for the RF power amplifier disclosed in the present invention.

[0036] Figure 3b Shown as the relationship curve of the bias voltage Vreg varying with time improved by using the dynamic biasing method for the RF power amplifier disclosed in the present invention.

[0037] Label description:

[0038] Preheating unit 1; post-heating unit 2; trigger group 3; first D flip-flop 31; second D flip-flop 4; third D flip-flop 5. Detailed implementation manners

[0039] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0040] Please refer to Figure 1a 、 1b 、2a, 21a - 23a, 2b, 21b - 22b, 3a, 3b. It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the implementation conditions of the present invention. Therefore, they do not have technical essence. Any modification of the structure, change of the ratio relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention.

[0041] Embodiment 1, please refer to Figure 2a 、 21a -23a, 2b, 21b - 22b. This embodiment provides a dynamic biasing circuit for an RF power amplifier, and the circuit includes an LDO module and a dynamic control module.

[0042] The LDO module uses an operational amplifier AMP and a transistor MP. The inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, and the output terminal is connected to the base of the transistor MP. The emitter of the transistor MP is connected to a high level, and the collector is grounded. A resistor R1 and a resistor R2 are connected to the collector of the transistor MP. The non-inverting input terminal of the operational amplifier AMP is specifically connected between the resistor R1 and the resistor R2. The LDO module further includes a preheating unit 1 and a post-heating unit 2. The preheating unit 1 uses a transistor M1_pre. The collector of the transistor M1_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP. The post-heating unit 2 uses a transistor M1_pos. The collector of the transistor M1_pos is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP. A three-phase six-arm driving structure is adopted in both the preheating unit 1 and the post-heating unit 2. Each phase of the three-phase six-arm driving structure uses two MOS transistors. The emitter of the MOS transistor located in the upper arm in the same phase is connected to the collector of the MOS transistor located in the lower arm. The vreg voltage of the PA is generated at the collector of the transistor MP. That is, the output voltage expression of the vreg voltage is Vreg = Vref(R1 + R2) / R1+(is_pre + is_post)*R2.

[0043] The dynamic control module uses an OSC, a trigger group 3 composed of several first D flip-flops connected in series, a second D flip-flop 4, and a third D flip-flop 5. The OSC is used to generate a periodic square wave signal. The duty cycle of the periodic square wave signal generated by the OSC is set to 50%, and the period is T. The trigger group 3 is used to stretch the clock cycle generated by the OSC to 2 n T, where T is time and n is the number of series-connected first D flip-flops 31; in the trigger group 3, there are V1, V2, V3, V4, V5, and V6 signals in sequence. The V1, V2, and V3 signals respectively control the extraction of the current is_pre in the preheat unit through NOR gates; the V4, V5, and V6 signals respectively control the extraction of the current is_pos in the postheat unit through NOR gates. In the initial state, both the preheat_off signal and the postheat_on signal are 0. The D terminal of the second D flip-flop 4 is connected to a high level, and the Q terminal outputs the preheat_off signal. The D terminal of the third D flip-flop 5 is connected to a high level, and the Q terminal outputs the postheat_on signal. The second D flip-flop 4 is connected in parallel to the first D flip-flop 31 located at n / 2 of the trigger group 3, and the third D flip-flop 5 is connected in parallel to the first D flip-flop 31 located at the end of the trigger group 3.

[0044] In this embodiment, a dynamic bias circuit composed of an LDO module and a dynamic control module is designed. The LDO module generates the vreg voltage of the PA. According to the output voltage expression of the vreg voltage, Vreg = Vref(R1 + R2) / R1 + (is_pre + is_post)*R2, the vreg voltage is controlled by the dynamic control module and is divided into the preheat stage and the postheat stage. Dynamic extraction currents are provided respectively in the two stages, thereby increasing the voltage output of vreg.

[0045] Embodiment 2. Please refer to Figure 2a 、 2b Based on Embodiment 1, FIGS. 3a and 3b, this embodiment provides a dynamic biasing method for a radio frequency power amplifier, including the following steps:

[0046] S1. Divide the output process of the radio frequency power amplifier into nodes T0, T1, T2, and T3 according to the time relationship. T0 - T1 is the preheat stage, T1 - T2 is the preheat stable stage, and T2 - T3 is the postheat stage;

[0047] S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50%, and the period to T;

[0048] S3. Connect several first D flip - flops 31 that make up the flip - flop group 3 in a divide - by - two form, so that the clock period of the square wave signal is stretched by 2 n times; that is, the period of V1 in the flip - flop group 3 is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 covers the transmission time of the entire long data packet;

[0049] S4. At T0, under the action of the reset signal or the PA working signal, both the preheat_off signal and the postheat_on signal are 0;

[0050] S5. During the T0 - T1 stage, V1, V2, and V3 in the trigger group 3 control the three extraction currents is_pre in the preheat stage through a NOR gate; during the T1 - T2 stage, as the clock signal repeats periodically, V1, V2, and V3 in the trigger group 3 form a long clock cycle loop, and the three extraction currents is_pre gradually decrease. At the end of the preheat stage, preheat_off is set high, causing en1_pre, en2_pre, and en3_pre to be set to 0, thus closing the preheat stage. Since the input D terminal of the second D - flip - flop 4 related to preheat_off is connected to VDD, the entire preheat stage is in the off state when the reset signal does not appear, and the preheat stage will restart only when the next reset signal arrives, that is, the preheat stage will start again at the beginning of the next data packet transmission. During the T2 - T3 stage, V4, V5, and V6 in the trigger group 3 control the three extraction currents is_post in the postheat stage through a NOR gate; when the V6 signal does not jump, postheat_on is still set to 0, and the postheat stage is still working, and is_post increases successively; when the V6 signal jumps, postheat is set high, causing the postheat stage to be closed, thus completing the transmission of the entire data packet.

[0051] The present invention designs a dynamic vreg voltage biasing scheme, which divides the output process of the radio - frequency power amplifier into nodes T0, T1, T2, and T3 according to the time relationship. During the t0 - t1 stage, which is called the preheat stage, the vreg voltage has a certain overshoot and gradually decays. In practical applications, the overshoot and gradual decay of the vreg voltage generally last about 100 μS, which is used to compensate for the slow power climb state at the initial stage of PA startup, thereby improving the flatness of the output power over time at the initial startup stage. During the t1 - t2 stage, the preheat overshoot disappears, and the vreg is consistent with the bias voltage in the thermal stable state. During the t2 - t3 stage, which is called the postheat stage, in this stage, the vreg voltage slowly increases. The postheat stage mainly compensates for the decrease in the current gain beta or transconductance gm caused by the thermal effect after the PA works for a certain period of time, thereby also improving the flatness of the output power over time during this period, preventing the power curve from dropping, enabling the radio - frequency power amplifier to provide high - power output, and ensuring the reliability and stability of signal transmission.

[0052] In summary, the present invention optimizes the design of the dynamic bias circuit, introduces preheat to enable dynamic control in two stages: preheat and postheat, and realizes the dynamic adjustment of the vreg voltage through the dynamic bias circuit, greatly improving the flatness of the output power of the RF power amplifier over time, improving the error vector magnitude performance of the PA under dynamic conditions, and enhancing the linearity index of the PA. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0053] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A dynamic bias circuit for a radio frequency power amplifier, characterized in that: The circuit includes an LDO module and a dynamic control module; The LDO module uses an operational amplifier AMP and a transistor MP, the inverting input terminal of the operational amplifier AMP is connected to the vref voltage, the non-inverting input terminal is connected to the collector of the transistor MP, the output terminal is connected to the base of the transistor MP, the emitter of the transistor MP is connected to a high level, and the collector is grounded; the LDO module also includes a preheating unit and a post-heating unit, the preheating unit uses a transistor M1_pre, the collector of the transistor M1_pre is connected to the reference current Iref_pre, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP; the post-heating unit uses a transistor M1_pos, the collector of the transistor M1_pos is connected to the reference current Iref_pos, the emitter is grounded, and the base is connected to the non-inverting input terminal of the operational amplifier AMP; generating a vreg voltage of PA at the collector of the transistor MP; The dynamic control module uses an OSC, a trigger group consisting of a plurality of first D flip-flops connected in series, a second D flip-flop, and a third D flip-flop. The OSC is used to generate a periodic square wave signal, and the trigger group is used to extend the OSC clock period to 2 n T, where T is time and n is the number of first D flip-flops connected in series; the D terminal of the second D flip-flop is connected to a high level and the Q terminal outputs a preheat_off signal, the D terminal of the third D flip-flop is connected to a high level and the Q terminal outputs a postheat_on signal, the second D flip-flop is connected in parallel to the first D flip-flop located at n / 2 of the trigger group, and the third D flip-flop is connected in parallel to the first D flip-flop located at the end of the trigger group.

2. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, characterized in that: The collector of the transistor MP is connected to a resistor R1 and a resistor R2 , and the non-inverting input terminal of the operational amplifier AMP is connected between the resistor R1 and the resistor R2 .

3. The dynamic bias circuit for a radio frequency power amplifier according to claim 2, characterized in that: The output voltage expression of the vreg voltage of the PA generated by the LDO module is as follows: Vreg=Vref(R1+R2) / R1+(is_pre+is_post)*R2.

4. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, characterized in that: In the trigger group, there are V1, V2, V3, V4, V5, and V6 signals in sequence. The V1, V2, and V3 signals are respectively controlled by NOR gates to extract current is_pre in the preheat unit; the V4, V5, and V6 signals are respectively controlled by NOR gates to extract current is_pos in the postheat unit.

5. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, characterized in that: In the initial state, the preheat_off signal and the postheat_on signal are both 0.

6. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, characterized in that: A three-phase six-arm drive structure is used in both the preheating unit and the post-heating unit. Each phase of the three-phase six-arm drive structure uses two MOS tubes. The emitter of the MOS tube located in the upper arm in the same phase is connected to the collector of the MOS tube located in the lower arm.

7. The dynamic bias circuit for a radio frequency power amplifier according to claim 1, characterized in that: The duty cycle of the periodic square wave signal generated by the OSC is set to 50%.

8. A dynamic bias method for a radio frequency power amplifier, comprising the dynamic bias circuit for a radio frequency power amplifier according to any one of claims 1 to 7, characterized in that: The steps include: S1. Divide the output process of the RF power amplifier into nodes T0, T1, T2, and T3 according to the time relationship, where T0-T1 is the preheat stage, T1-T2 is the preheat stabilization stage, and T2-T3 is the postheat stage; S2. Use an OSC to generate a periodic square wave signal, set the duty cycle of the signal to 50%, and the period is T; S3, connect the first D flip-flops constituting the flip-flop group into a two-way frequency division form, so that the clock period of the square wave signal is 2 n times; that is, in the trigger group, the period of V1 is 2T, the period of V2 is 4T, the period of V3 is 8T, the period of V4 is 32T, the period of V5 is 64T, and the period of V6 is 128T, where V6 is the transmission time covering the entire long data packet; At S4 and T0, both the preheat_off signal and the postheat_on signal are 0; S5, in the T0-T1 stage, V1, V2, and V3 in the trigger group control the three extraction currents is_pre in the preheat stage through the NOR gate; In the T1-T2 stage, with the periodic repetition of the clock signal, V1, V2, and V3 in the trigger group form a long clock cycle, and the three extracted currents is_pre gradually decrease. At the end of the preheat stage, preheat_off is set high, so that en1_pre, en2_pre, and en3_pre are all set to 0, thereby closing the preheat stage; in the T2-T3 stage, V4, V5, and V6 in the trigger group control the three extracted currents is_post in the postheat stage through the NOR gate; when the V6 signal does not jump, postheat_on is still set to 0, the postheat stage is still in operation, and is_post increases gradually; and when the V6 signal jumps, postheat is set high, so that the postheat stage is closed, thereby completing the transmission of the entire data packet.

9. The dynamic bias method for a radio frequency power amplifier according to claim 8, characterized in that: In step S5, since the input D terminal of the second D flip-flop related to preheat_off is connected to VDD, the entire preheat stage is in a closed state when the reset signal does not appear. The preheat stage will not be restarted until the next reset signal comes, that is, the preheat stage will not be restarted until the next data packet is sent.

Images