Storage and calculation integrated and physical unclonable function hardware architecture and implementation method

Abstract

The invention discloses a storage and calculation integrated and physical unclonable function hardware architecture and an implementation method, and the architecture comprises a physical unclonable function generator, an encryption and decryption unit, a voltage-current converter and a multiplication accumulator. The physical unclonable function generator comprises a first memory, a second memory and an SR trigger; the second memory is connected with the multiplication accumulator; the first memory and the second memory are connected with the SR trigger; the first memory, the SR trigger and the voltage-current converter are connected with the encryption and decryption unit; the voltage-current converter is connected with the first memory; wherein the thickness of the free layer of the second memory is different from that of the free layer of the first memory. The circuit can be widely applied to the technical field of electronic circuits.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a storage-computation-in-one and physically unclonable function hardware architecture and implementation method. Background Art

[0002] Storage and computing integration is a technology that integrates data storage modules with computing modules and performs computing near the storage modules. With the development of modern electronics, the development of Moore's Law has approached its physical theoretical limit. The past method of using size reduction to improve performance no longer has broad prospects. Relying on von Neumann structure computers gradually cannot meet the performance requirements of large-scale matrix operations, so storage and computing integration technology came into being. Storage and computing integration technology can greatly reduce the huge energy consumption caused by high-frequency transmission of data between storage units and computing units, and at the same time reduce the huge delay introduced by this. Physical unclonable function is a technology that uses tiny differences in the physical manufacturing process to generate digital fingerprints. These tiny differences include tiny changes in transistor size and threshold voltage values, and the tiny differences produced are unique and unpredictable. Compared with the traditional key system that stores passwords in non-volatile memory, the output of PUF is based on physical properties, so they are unclonable. Based on its above characteristics, it is currently widely studied and applied in the field of information security, and is irreplaceable in the fields of limited devices, mature cryptography, and hardware security.

[0003] In the related art, most of the current physical unclonable functions are implemented through non-electronic methods, digital circuit methods and analog circuit methods; non-electronic methods are difficult to be compatible with integrated circuits, and analog circuits are easily interfered due to the essential characteristics of analog signals. Therefore, there are still technical problems that need to be solved in the related art. Summary of the invention

[0004] The purpose of this application is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] To this end, an object of an embodiment of the present application is to provide a storage-computing-in-one and physically unclonable function hardware architecture and implementation method, which can improve the stability of the architecture.

[0006] In order to achieve the above-mentioned technical objectives, the technical solutions adopted by the embodiments of the present application include: a storage-computing-in-one and physical unclonable function hardware architecture, including: a physical unclonable function generator, an encryption and decryption unit, a voltage-current converter and a multiplication accumulator; the physical unclonable function generator includes a first memory, a second memory and an SR trigger; the second memory is connected to the multiplication accumulator; the first memory and the second memory are connected to the SR trigger; the first memory, the SR trigger and the voltage-current converter are connected to the encryption and decryption unit; the voltage-current converter is connected to the first memory; wherein the free layer thickness of the second memory is different from the free layer thickness of the first memory.

[0007] In addition, according to the storage-computing-in-one and physical unclonable function hardware architecture of the above embodiment of the present application, the following additional technical features may also be provided:

[0008] Furthermore, in an embodiment of the present application, the circuit structure of the first memory is the same as the circuit structure of the second memory.

[0009] Further, in the embodiment of the present application, the first memory includes a fixed layer, an isolation layer, a free layer, a first input terminal, a second input terminal, a third input terminal, a first inverter, a second inverter, a first field effect transistor, a second field effect transistor and a third field effect transistor;

[0010] The first input terminal is used to input a spin transfer torque current; the second input terminal is used to input a spin orbit torque current; the free layer has a terminal which is a first output terminal of the first memory; the first output terminal is connected to the drain of the second field effect transistor; the source of the second field effect transistor is connected to the first inverter; the first inverter is connected to the second inverter; the fixed layer has a terminal which is connected to the source of the first field effect transistor;

[0011] The third input terminal is connected to the drain of the third field effect transistor; the source of the third field effect transistor is grounded; the gate of the first field effect transistor, the drain of the first field effect transistor, the gate of the second field effect transistor and the gate of the third field effect transistor are connected to a control bus.

[0012] Further, in the embodiment of the present application, the encryption and decryption unit includes a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a third inverter and a fourth inverter;

[0013] The drain of the fourth field effect tube, the drain of the fifth field effect tube and the source of the ninth field effect tube are all grounded; the source of the fourth field effect tube is connected to the drain of the sixth field effect tube; the source of the fifth field effect tube is connected to the drain of the seventh field effect tube;

[0014] The source of the sixth field effect transistor, the source of the seventh field effect transistor, the drain of the eighth field effect transistor and the drain of the ninth field effect transistor are connected to the input end of the third inverter; the source of the eighth field effect transistor is connected to the first power supply;

[0015] The output end of the third inverter is connected to the input end of the fourth inverter; the output end of the third inverter serves as the first output end of the encryption / decryption unit, and the output end of the fourth inverter serves as the second output end of the encryption / decryption unit;

[0016] The gates of the fourth field effect tube, the fifth field effect tube, the sixth field effect tube, the seventh field effect tube, the eighth field effect tube, and the ninth field effect tube are connected to the control bus.

[0017] Further, in the embodiment of the present application, the voltage-to-current converter includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, and a fourteenth field effect transistor;

[0018] The source of the tenth field effect transistor, the source of the eleventh field effect transistor and the drain of the fourteenth field effect transistor are all grounded;

[0019] The drain of the tenth field effect transistor and the source of the twelfth field effect transistor are connected to the forward current;

[0020] The drain of the eleventh field effect transistor and the source of the thirteenth field effect transistor are connected to the forward current;

[0021] The drain of the twelfth field effect transistor and the drain of the thirteenth field effect transistor are connected to the source of the fourteenth field effect transistor; the source of the fourteenth field effect transistor serves as the output end of the voltage-current converter; the gate of the tenth field effect transistor, the gate of the eleventh field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor are connected to the encryption and decryption unit; the gate of the fourteenth field effect transistor is connected to the control bus.

[0022] Further, in the embodiment of the present application, the voltage-to-current converter includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor, and a fourteenth field effect transistor;

[0023] The drain of the tenth field effect transistor, the drain of the eleventh field effect transistor and the source of the fourteenth field effect transistor are all grounded;

[0024] The source of the tenth field effect transistor and the drain of the twelfth field effect transistor are connected to the forward current;

[0025] The source of the eleventh field effect transistor and the drain of the thirteenth field effect transistor are connected to the forward current;

[0026] The source of the twelfth field effect transistor and the source of the thirteenth field effect transistor are connected to the drain of the fourteenth field effect transistor; the drain of the fourteenth field effect transistor serves as the output end of the voltage-current converter; the gate of the tenth field effect transistor, the gate of the eleventh field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor are connected to the encryption and decryption unit; the gate of the fourteenth field effect transistor is connected to the control bus.

[0027] Furthermore, in the embodiment of the present application, the multiplier-accumulator includes a plurality of operators; the structure of any one of the operators is the same as the structure of the encryption and decryption unit.

[0028] Furthermore, in the embodiment of the present application, the thickness of the free layer of the first memory is T1, 0.65nm<T1<0.70nm; the thickness of the free layer of the first memory is T2, 0.70nm<T2<0.75nm.

[0029] Furthermore, in the embodiment of the present application, the fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the ninth field effect transistor are NMOS field effect transistors; and the eighth field effect transistor is a PMOS field effect transistor.

[0030] In addition, the present application also provides a method for implementing a storage-computing-in-one and physically unclonable function hardware architecture, which is implemented by the storage-computing-in-one and physically unclonable function hardware architecture described in any of the above items, and the method includes:

[0031] The first memory is pre-written with 1 and the second memory is pre-written with 0, or the first memory is pre-written with 0 and the second memory is pre-written with 1 and transmitted to the SR trigger, so that the SR trigger generates a key signal;

[0032] The first memory receives the written first operand and sends the first operand to the encryption and decryption unit, so that the encryption and decryption unit encrypts the first operand and generates an encryption level and sends it to the voltage-current converter;

[0033] The voltage-to-current converter rewrites the first operand into the first memory according to the encryption level;

[0034] The first memory receives and sends the rewritten first operand to the multiplication accumulator, and the second memory receives and sends the second operand to the multiplication accumulator;

[0035] The multiplication accumulator calculates an accumulation result according to the rewritten first operand and the second operand.

[0036] The advantages and benefits of the present application will be partially given in the following description, and partially become apparent from the following description, or be understood through the practice of the present application:

[0037] The present application can realize the generation of a physical unclonable function in an innovative way, and utilizes the different thicknesses of the free layer of the memory to generate different jump delays of two input SR triggers, thereby directly affecting the output result of the SR trigger, and then generating a physical unclonable function signal. The physical unclonable function signal can be used for encryption and decryption of subsequent operands and multiplication and accumulation, and finally obtain the target accumulation result. Compared with analog circuits, the present application forms the architecture of a digital circuit through structures such as SR triggers, first memories, and second memories, thereby improving the stability of the architecture itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a module diagram of a storage-computation-in-one and physical unclonable function hardware architecture in a specific embodiment of the present invention;

[0039] Figure 2 A schematic diagram of the circuit structure of a first memory or a second memory in a specific embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the circuit structure of an encryption and decryption unit in a specific embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the circuit structure of a voltage-to-current converter in a specific embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the steps of a method for implementing a storage-computation-integrated and physically unclonable function hardware architecture in a specific embodiment of the present invention;

[0043] Figure 6 It is a module diagram of a storage-computation-in-one and physical unclonable function hardware architecture in another specific embodiment of the present invention;

[0044] Figure 7 It is a module diagram of a storage-computation-in-one and physical unclonable function hardware architecture in another specific embodiment of the present invention;

[0045] Figure 8It is a schematic diagram of the steps of a method for implementing a storage-computation-integrated and physically unclonable function hardware architecture in another specific embodiment of the present invention;

[0046] Fig. 9 A schematic diagram of the circuit structure of a first memory or a second memory in another specific embodiment of the present invention;

[0047] Fig.10 A schematic diagram of the circuit structure of a physical unclonable function generator in a specific embodiment of the present invention;

[0048] Fig.11 A schematic diagram of the circuit structure of an encryption and decryption unit in a specific embodiment of the present invention;

[0049] Fig.12 A schematic diagram of the circuit structure of a voltage-to-current converter in a specific embodiment of the present invention;

[0050] Fig.13 The figure is a schematic diagram of the circuit structure of a multiplication and accumulation device in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following describes in detail the embodiments of the present invention in conjunction with the accompanying drawings to illustrate the principles and processes of the hardware architecture and implementation method of the storage-computation-in-one physical unclonable function in the embodiments of the present invention.

[0052] Reference Figure 1 The present application provides a storage-computation-in-one hardware architecture that can be used with a physical unclonable function. The architecture may include: a physical unclonable function generator 4, an encryption and decryption unit 2, a voltage-current converter 3, and a multiplication accumulator 1; the physical unclonable function generator 4 may include a first memory 41, a second memory 42, and an SR trigger 43; the second memory 42 may be connected to the multiplication accumulator 1; the first memory 41 and the second memory 42 may be connected to the SR trigger 43; the first memory 41, the SR trigger 43, and the voltage-current converter 3 may be connected to the encryption and decryption unit 2; the voltage-current converter 3 may be connected to the first memory 41; wherein the free layer thickness of the second memory 42 may be different from the free layer thickness of the first memory 41.

[0053] Furthermore, in the embodiment of the present application, the circuit structure of the first memory 41 may be the same as the circuit structure of the second memory 42 .

[0054] Further, in the embodiments of the present application, refer to Figure 2 The first memory 41 may include a fixed layer 411, an isolation layer 412, a free layer 413, a first input terminal T 1 , the second input terminal T 2 , the third input terminal T3 , the first inverter D 1 , the second inverter D 2 , the first field effect tube M 1 , the second field effect tube M 2 And the third field effect tube M 3 ;

[0055] The first input terminal T 1 Can be used to input spin transfer torque current; the second input terminal T 2 It can be used to input spin-orbit torque current; the free layer 413 has a terminal which is the first output terminal T of the first memory. MZ ; The first output terminal T MZ Can be connected with the second FET M 2 The drain connection of the second field effect tube M 2 The source of the first inverter D 1 Connection: First inverter D 1 Can be connected with the second inverter D 2 The fixed layer 411 has a terminal that can be connected to the first field effect transistor M 1 The source connection of

[0056] The third input terminal T 3 Can be connected with the third field effect tube M 3 The drain connection of the third field effect tube M 3 The source of the first field effect tube M 1 The gate of the first field effect transistor M can be connected to one of the control signal lines WW L in the control bus. 1 The drain of the second field effect transistor M can be connected to one of the control signal lines WBL in the control bus. 2 The gate of the third field effect transistor M can be connected to one of the control signal lines WL in the control bus. 3 The gate of the first field effect transistor M can be connected to one of the control signal lines SL in the control bus; 1 The source electrode is connected to the fixed layer 411 .

[0057] Further, in the embodiments of the present application, refer to Figure 3 The encryption and decryption unit 2 may include a fourth field effect transistor T 4 、Fifth field effect tube T 5 , the sixth field effect tube T 6 , the seventh field effect tube T 7 , the eighth field effect tube T 8 、Ninth field effect tube T 9 , the third inverter D 3 and the fourth inverter D 4 ;

[0058] The fourth field effect tube T 4 The drain of the fifth field effect transistor T 5 The drain of the ninth field effect transistor T 9 The source of the fourth field effect tube T 4 The source of the sixth field effect transistor T 6 The drain connection of the fifth field effect transistor T 5 The source of the seventh field effect transistor T 7 The drain connection of

[0059] The sixth field effect tube T 6 The source of the seventh field effect tube T 7 The source of the eighth field effect transistor T8, the drain of the ninth field effect transistor T 9 The drain of the third inverter D 3 The input terminal of the eighth field effect tube T 8 The source electrode may be connected to the first power source;

[0060] The third inverter D 3 The output terminal of the fourth inverter D 4 The input terminal of the third inverter D 3 The output end of the encryption and decryption unit is used as the first output end The fourth inverter D 4 The output end of is used as the second output end Vout of the encryption and decryption unit;

[0061] The fourth field effect tube T 4 The gate of the fifth field effect transistor T is connected to one of the control signal lines BL in the control bus. 5 The gate of the sixth field effect transistor T is connected to one of the control signal lines BLB in the control bus. 6 The gate of the seventh field effect transistor T is connected to one of the control signal lines PUF in the control bus. 7 The gate of the eighth field effect transistor T is connected to one of the control signal lines PUFB in the control bus. 8 The gate of the ninth field effect transistor T is connected to one of the control signal lines INB in ​​the control bus. 9 The gate of can be connected to one of the control signal lines INB in ​​the control bus.

[0062] Further, in the embodiments of the present application, refer to Figure 4 The voltage-to-current converter 3 may include a tenth field effect transistor P 1 , Eleventh Field Effect Transistor N 1 , 12th field effect tube N 2 、Thirteenth field effect tube P 2 And the fourteenth field effect tube P3 ;

[0063] The tenth field effect tube P 1 The source of the eleventh field effect tube N 1 The source of the fourteenth field effect transistor P 3 The drains are all grounded;

[0064] The tenth field effect tube P 1 The drain of the twelfth field effect transistor N 2 The source of can be connected with forward current;

[0065] 11th Field Effect Transistor N 1 The drain of the thirteenth field effect transistor P 2 The source of can be connected with forward current;

[0066] 12th Field Effect Transistor N 2 The drain of the thirteenth field effect transistor P 2 The drain of the fourteenth field effect transistor P 3 The source of the fourteenth field effect tube P 3 The source of the voltage-current converter is used as the output terminal; the tenth field effect transistor P 1 The gate of the eleventh field effect transistor N1, the gate of the twelfth field effect transistor N 2 The gate of the thirteenth field effect transistor P 2 The gate of the fourteenth field effect transistor P 3 The gate of can be connected to one of the control signal lines WWL in the control bus.

[0067] Further, in the embodiments of the present application, refer to Figure 4 The voltage-to-current converter 3 may include a tenth field effect transistor P 1 , Eleventh Field Effect Transistor N 1 , 12th field effect tube N 2 、Thirteenth field effect tube P 2 And the fourteenth field effect tube P 3 ;

[0068] The tenth field effect tube P 1 The drain of the eleventh field effect transistor N 1 The drain of the fourteenth field effect transistor P 3 The sources of are grounded;

[0069] The tenth field effect tube P 1 The source of the twelfth field effect transistor N 2 The drain can be connected to the forward current;

[0070] 11th Field Effect Transistor N 1The source of the thirteenth field effect transistor P 2 The drain can be connected to the forward current;

[0071] 12th Field Effect Transistor N 2 The source of the thirteenth field effect transistor P 2 The source of the fourteenth field effect transistor P 3 The drain connection of the fourteenth field effect tube P 3 The drain of the voltage-current converter is used as the output terminal; the tenth field effect transistor P 1 The gate of the eleventh field effect tube N 1 The gate of the twelfth field effect transistor N 2 The gate of the thirteenth field effect transistor P 2 The gate of the fourteenth field effect transistor P 3 The gate of can be connected to one of the control signal lines WWL in the control bus.

[0072] It is understandable that the above two embodiments illustrate that each field effect transistor in the voltage-to-current converter operates in a saturated state. The connection method of the source and drain of any field effect transistor may be unlimited.

[0073] Furthermore, in the embodiment of the present application, the multiplier accumulator 1 may include a plurality of operators; the structure of any one of the operators may be the same as the structure of the encryption and decryption unit.

[0074] Furthermore, in the embodiment of the present application, the thickness of the free layer 413 of the first memory is T1, 0.65 nm<T1<0.70 nm; the thickness of the free layer 413 of the first memory is T2, 0.70 nm<T2<0.75 nm.

[0075] Furthermore, in the embodiment of the present application, the fourth field effect transistor T 4 , the fifth field effect tube T 5 , the sixth field effect tube T 6 , the seventh field effect tube T 7 And the ninth field effect tube T 9 is an NMOS field effect tube; the eighth field effect tube T 8 It is a PMOS field effect tube.

[0076] In addition, refer to Figure 5 The present application also provides a method for implementing a storage-computing-in-one hardware architecture with a physical unclonable function. The storage-computing-in-one hardware architecture with a physical unclonable function can be implemented through any of the preceding items. The method may include steps S101 to S105.

[0077] S101, the first memory is pre-written with 1 and the second memory is pre-written with 0, or the first memory is pre-written with 0 and the second memory is pre-written with 1 and transmitted to the SR trigger, so that the SR trigger generates a key signal.

[0078] S102 , the first memory receives the written first operand and sends the first operand to the encryption / decryption unit, so that the encryption / decryption unit encrypts the first operand and generates an encryption level and sends it to the voltage-current converter.

[0079] S103 . The voltage-to-current converter rewrites the first operand into the first memory according to the encryption level.

[0080] S104, the first memory receives and sends the rewritten first operand to the multiplication accumulator, and the second memory receives and sends the second operand to the multiplication accumulator.

[0081] S105 , the multiplication accumulator calculates an accumulation result according to the rewritten first operand and the second operand.

[0082] The specific implementation principle of this application is described below with reference to the accompanying drawings:

[0083] like Figure 6 As shown, the overall architecture of the storage-computing-in-one and physical unclonable function hardware collaborative multiplexing architecture in the present invention includes a global controller, a control bus, a data storage module, a physical unclonable function signal generating circuit, a storage data encryption and decryption circuit, a perpendicular magnetic anisotropy-spin orbit torque-spin transfer torque-magnetoresistive random access memory voltage-current conversion circuit during rewriting, and a multiplication and addition operation circuit in a multiplication accumulator.

[0084] like Figure 7 , which is a schematic diagram of the data flow structure of the architecture in the present invention, including several basic units and corresponding data buses. In these data buses, IN is used for data output of memory 2, RBL is used for data output of memory 1, WBL is used for data input of memory, SL is used for memory selection, RWL is used for output selection of memory, and WWL is used for input selection of memory.

[0085] like Figure 8The figure shows a schematic diagram of the working timing state of the architecture of the present invention. The architecture of the present invention mainly has four working stages. In working stage 1, the physical unclonable function signal is generated by pre-writing signal 1 and signal 0 in the physical unclonable function generator in sequence; in working stage 2, the writing, decryption, and re-writing of the 16-bit operand 1 after encryption are mainly completed; in working stage 3, the decryption of the 16-bit operand 1 and the writing of the 16-bit operand 2 are mainly completed; in working stage 4, the multiplication and accumulation operation of the 16-bit operand 1 and the 16-bit operand 2 is mainly completed.

[0086] like Fig. 9 As shown in FIG. 1 , it is a schematic diagram of the structure of the data storage module in the present invention. The present invention uses perpendicular magnetic anisotropy-spin orbit torque-spin transfer torque-magnetoresistive random access memory to store data. It is mainly composed of three layers, namely a fixed layer (thicker, the direction of the magnetic moment is difficult to change), an isolation layer (generally using magnesium oxide), and a free layer (smaller thickness, the direction of the magnetic moment is easy to change). In addition, there are three input ports, namely T 1 Port, used for input of spin transfer torque current; T 2 Port, used for input of spin-orbit torque current; T 3 Port, used to select the ground terminal and the memory element. Output port, which is T mz The output buffer is two inverters in the figure, which adjust the -1V / 1V voltage of the output end to 0V / 1.8V respectively, so as to facilitate the use of the next level circuit.

[0087] The present invention relates to a device parameter of a memory device, namely, the thickness of a free layer. The thicker the free layer, the more difficult it is to change the direction of its magnetic moment, and the longer the delay required for the output signal to flip when the input signal flips.

[0088] like Fig.10 As shown in FIG. 1 , it is a schematic diagram of the structure of the physical unclonable function signal generating circuit in the present invention. The two memories constituting the physical unclonable function signal generating circuit are respectively X 1 , X 2 Where X 1 The free layer thickness is 0.67nm, while X 2 The free layer thickness is 0.73nm, so X 1 The jump delay of the output signal will be less than X 2 When the SR flip-flop receives two jump delays, the corresponding output will be generated at the output. The output in the figure is high. When the relative relationship of the free layer thickness is reversed, the output will become low.

[0089] like Fig.11As shown in FIG. 1 , it is a schematic diagram of the structure of the data encryption and decryption circuit in the present invention. The five NMOS transistors are T 4 , T 5 , T 6 , T 7 , T 9 ; PMOS transistor is T 8 ; The output control unit is the switch in the figure. When the switch is closed, the output signal can enter the next level. The BL and BLB in the figure respectively input the signal to be encrypted (decrypted) and its inverse signal. The PUF and PUFB in the figure respectively input the physical unclonable function signal used for encryption (decryption) and its inverse signal. The INB in ​​the figure inputs a low level before performing encryption and decryption operations. When INB inputs a low level, P1 will be turned on, so that the voltage at Vx becomes a high voltage. At this time, if BL and PUF are at a high level at the same time, N1 and N3 are turned on at the same time, and Vx is discharged to a low level; if BLB and PUFB are at a high level at the same time, N2 and N4 are turned on at the same time, and Vx is discharged to a low level. Otherwise, the voltage at Vx still maintains a high level. This process can be abstracted as the following formula,

[0090] Vout=BL⊕PUF

[0091] Among them, Vout is the encrypted output, BL is the output of MRAM, “⊕” is the logical XOR operation, and PUF is the physical unclonable function signal. When decrypting, the encrypted signal is input into the structure again through BL and BLB, and the above operation is performed again.

[0092] Vout'=Vout⊕PUF=(BL⊕PUF)⊕PUF=BL

[0093] Among them, Vout' is the decrypted signal. It is not difficult to find that the decrypted signal is restored to the original signal.

[0094] like Fig.12 As shown, it is a schematic diagram of the voltage-current conversion circuit structure of the perpendicular magnetic anisotropy-spin orbit torque-spin transfer torque-magnetoresistive random access memory when rewriting in the present invention. 1 and N 2 ; Three PMOS transistors are P 1 , P 2 , P 3 Since the output signal of the encryption phase is a voltage signal, and a spin transfer torque current needs to be generated in order to perform a rewrite operation, the present invention designs a voltage-current transfer circuit. Its input control signal is the inverse signal of the output signal of the encryption phase. The input signal is two currents I+ and I- with equal magnitude and opposite directions. When it is high, as shown on the left side of the figure, N 1 、N 2 The current I+ flows into the memory and writes a signal 0; when the input control signal When it is low, as shown on the right side of the figure, P 1 , P 2 The current I- flows into the memory and writes a signal 1. WWL is the input selection control signal of the memory. When it is high, P 3 When it is low, P3 is turned on and the current flows through P 3 flows to ground.

[0095] like Fig.13 As shown, it is a schematic diagram of the multiplication and addition circuit structure in the multiplication accumulator of the present invention. The circuit used to perform the multiplication operation is the AND operation unit in the upper left corner of the figure; the circuit used to perform the addition operation is the XOR operation unit in the upper left corner of the figure. Its hardware structure is the same as the circuit structure used to implement encryption and decryption. For the multiplication operation unit, when its PUF terminal is connected to a low level, the PUF terminal is connected to a high level, the BL / BLB terminal is connected to the 16-bit operand 1, and the INB terminal is connected to the inverse signal of the 16-bit operand 2, there is the following formula:

[0096]

[0097] Where Vout is the result of the AND operation, BL are two input operands, that is, the AND operation between the two operands is realized. For the addition unit, the INB terminal is connected to a low level, and the two operands are connected to the BL / BLB terminal and the PUF / PUFB terminal respectively, and the following formula is obtained:

[0098]

[0099] Vout is the result of XOR operation, BL and PUF are two input operands, that is, the XOR operation between the two operands is realized. After realizing the multiplication and addition of one bit, the calculation is performed bit by bit according to the steps of partial sum product, carry accumulation, and merge calculation, and finally a 31-bit operation result is obtained.

[0100] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the application is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are expected, wherein the order of various operations is changed and the sub-operation described as a part of a larger operation is performed independently.

[0101] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present application. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional techniques of the engineer. Therefore, those skilled in the art can implement the present application set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the attached claims and their equivalents.

[0102] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing the logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution systems, devices or apparatuses. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution systems, devices or apparatuses.

[0103] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0104] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

[0105] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the described embodiments. Technical personnel familiar with the field can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A storage-computing-in-one and physically unclonable function hardware architecture, characterized in that: include: Physical unclonable function generator, encryption and decryption unit, voltage-to-current converter, and multiplication-accumulation unit; The physical unclonable function generator includes a first memory, a second memory and an SR trigger; The second memory is connected to the multiplication accumulator; the first memory and the second memory are connected to the SR trigger; the first memory, the SR trigger and the voltage-current converter are connected to the encryption and decryption unit; the voltage-current converter is connected to the first memory; wherein the free layer thickness of the second memory is different from the free layer thickness of the first memory.

2. According to the storage-computing-in-one and physically unclonable function hardware architecture of claim 1, it is characterized by: The circuit structure of the first memory is the same as the circuit structure of the second memory.

3. According to claim 2, a storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The first memory includes a fixed layer, an isolation layer, a free layer, a first input terminal, a second input terminal, a third input terminal, a first inverter, a second inverter, a first field effect transistor, a second field effect transistor and a third field effect transistor; The first input terminal is used to input a spin transfer torque current; the second input terminal is used to input a spin orbit torque current; the free layer has a terminal which is a first output terminal of the first memory; The first output terminal is connected to the drain of the second field effect transistor; the source of the second field effect transistor is connected to the first inverter; The first inverter is connected to the second inverter; the fixed layer has a terminal connected to the source of the first field effect transistor; The third input terminal is connected to the drain of the third field effect transistor; the source of the third field effect transistor is grounded; the gate of the first field effect transistor, the drain of the first field effect transistor, the gate of the second field effect transistor and the gate of the third field effect transistor are connected to a control bus.

4. According to claim 1, the storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The encryption / decryption unit includes a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a third inverter and a fourth inverter; The drain of the fourth field effect tube, the drain of the fifth field effect tube and the source of the ninth field effect tube are all grounded; the source of the fourth field effect tube is connected to the drain of the sixth field effect tube; the source of the fifth field effect tube is connected to the drain of the seventh field effect tube; The source of the sixth field effect transistor, the source of the seventh field effect transistor, the drain of the eighth field effect transistor and the drain of the ninth field effect transistor are connected to the input end of the third inverter; The source of the eighth field effect transistor is connected to the first power supply; The output end of the third inverter is connected to the input end of the fourth inverter; the output end of the third inverter serves as the first output end of the encryption / decryption unit, and the output end of the fourth inverter serves as the second output end of the encryption / decryption unit; The gates of the fourth field effect tube, the fifth field effect tube, the sixth field effect tube, the seventh field effect tube, the eighth field effect tube, and the ninth field effect tube are connected to the control bus.

5. According to claim 1, the storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The voltage-to-current converter includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor and a fourteenth field effect transistor; The source of the tenth field effect transistor, the source of the eleventh field effect transistor and the drain of the fourteenth field effect transistor are all grounded; The drain of the tenth field effect transistor and the source of the twelfth field effect transistor are connected to the forward current; The drain of the eleventh field effect transistor and the source of the thirteenth field effect transistor are connected to the forward current; The drain of the twelfth field effect transistor and the drain of the thirteenth field effect transistor are connected to the source of the fourteenth field effect transistor; the source of the fourteenth field effect transistor serves as the output end of the voltage-current converter; the gate of the tenth field effect transistor, the gate of the eleventh field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor are connected to the encryption and decryption unit; the gate of the fourteenth field effect transistor is connected to the control bus.

6. According to claim 1, a storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The voltage-to-current converter includes a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, a thirteenth field effect transistor and a fourteenth field effect transistor; The drain of the tenth field effect transistor, the drain of the eleventh field effect transistor and the source of the fourteenth field effect transistor are all grounded; The source of the tenth field effect transistor and the drain of the twelfth field effect transistor are connected to the forward current; The source of the eleventh field effect transistor and the drain of the thirteenth field effect transistor are connected to the forward current; The source of the twelfth field effect transistor and the source of the thirteenth field effect transistor are connected to the drain of the fourteenth field effect transistor; the drain of the fourteenth field effect transistor serves as the output end of the voltage-current converter; the gate of the tenth field effect transistor, the gate of the eleventh field effect transistor, the gate of the twelfth field effect transistor, and the gate of the thirteenth field effect transistor are connected to the encryption and decryption unit; the gate of the fourteenth field effect transistor is connected to the control bus.

7. According to claim 1, the storage-computing-in-one and physically unclonable function hardware architecture is characterized by: The multiplication accumulator includes a plurality of operators; the structure of any one of the operators is the same as the structure of the encryption and decryption unit.

8. According to claim 1, the storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The thickness of the free layer of the first memory is T1, 0.65nm<T1<0.70nm; the thickness of the free layer of the first memory is T2, 0.70nm<T2<0.75nm.

9. According to claim 4, a storage-computing-in-one and physically unclonable function hardware architecture is characterized in that: The fourth field effect transistor, the fifth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the ninth field effect transistor are NMOS field effect transistors; and the eighth field effect transistor is a PMOS field effect transistor.

10. A method for implementing a storage-computation-in-one and physically unclonable function hardware architecture, characterized in that: The method is implemented by the storage-computation-in-one and physical unclonable function hardware architecture described in any one of claims 1 to 9, and includes: The first memory is pre-written with 1 and the second memory is pre-written with 0, or the first memory is pre-written with 0 and the second memory is pre-written with 1 and transmitted to the SR trigger, so that the SR trigger generates a key signal; The first memory receives the written first operand and sends the first operand to the encryption and decryption unit, so that the encryption and decryption unit encrypts the first operand and generates an encryption level and sends it to the voltage-current converter; The voltage-to-current converter rewrites the first operand into the first memory according to the encryption level; The first memory receives and sends the rewritten first operand to the multiplication accumulator, and the second memory receives and sends the second operand to the multiplication accumulator; The multiplication accumulator calculates an accumulation result according to the rewritten first operand and the second operand.

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