Chip packaging structure

Abstract

The invention discloses a chip packaging structure which comprises a substrate, a chip set is welded and installed on the upper surface of the substrate, an intermediate layer is arranged in the middle of the bottom layer of the chip set, a control chip is arranged on the top of the intermediate layer, and a plurality of storage particles are arranged on the two sides of the intermediate layer and the two sides of the control chip. The storage particles close to the control chip are electrically connected with the control chip, the control chip is electrically connected with the outside through the interposer, and the control chip is lifted by a certain height through the interposer, so that the storage particles can be stacked on the two sides of the control chip to obtain a larger storage space, and the storage capacity of the control chip is improved. A plurality of placement positions of one layer can be additionally obtained below the control chip, so that the overall storage space and storage capacity are greatly improved on the basis of a limited area, and the data communication rate is improved through a staggered series structure and a shortened connection distance; and the improvement of the overall data throughput and bandwidth is further promoted.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and specifically to a chip packaging structure. Background Art

[0002] CoWoS (Chip-on-Wafer-on-Substrate) is an advanced packaging technology. It integrates multiple chips using the Through-Silicon Via (TSV) technology. First, the chips are soldered to the silicon substrate through the back side, and then electrical connections are achieved.

[0003] CoWoS is applied to fields such as high-end logic chips, processors, deep learning accelerators, and data centers. However, it also faces challenges such as high-precision manufacturing, material adaptation, and testing difficulties.

[0004] In recent years, with the growing demand for smaller-sized electronic devices, more innovative packaging technologies are required for semiconductor wafers. Among them, the three-dimensional semiconductor wafer package technology has become an effective option to further reduce the physical size of the semiconductor wafer package.

[0005] For high-speed data exchange ports, in the prior art, a high-speed data exchange port can only connect one high-bandwidth memory chip, and the peripheral space of the processor is limited. Generally, only eight high-speed data exchange ports can be arranged, that is, the prior art can connect at most eight high-bandwidth memory chips at most. This situation greatly limits the connection expansion between the processor and the high-bandwidth memory chips.

[0006] In addition, in the prior art, both the processor and the high-bandwidth memory chip communicate with the substrate through the interpose layer. However, the interpose layers in the prior art are all made of silicon wafers, so the cost is very high. At the same time, the thickness is relatively thin, and it does not support a thicker thickness. A higher aspect ratio is required, and it is even more necessary to completely transform the chip structure from 2.5D packaging to 3D packaging. Summary of the Invention

[0007] The purpose of the present invention is to provide a chip packaging structure aiming at the above-mentioned existing problems and deficiencies, which improves the overall working efficiency.

[0008] The present invention solves at least one of the following technical problems:

[0009] (1) How to increase the connection quantity of memory particles to achieve a capacity expansion structure in multiples;

[0010] (2) The silicon interposer is costly and a low-cost alternative solution is needed;

[0011] (3) The silicon interposer cannot fabricate an interposer with a relatively thick thickness to form an interposer with a high aspect ratio.

[0012] The object of the present invention can be achieved by the following technical solutions: A chip packaging structure includes a substrate, on the upper surface of which a chip group is welded and installed. In the middle of the bottom layer of the chip group, there is an interposer. On the top of the interposer, there is a control chip. On both sides of the interposer and on both sides of the control chip, there are a number of memory particles. The memory particles on both sides are electrically connected to each other and are both electrically connected to the control chip. The control chip is electrically connected to the interposer.

[0013] As a further solution of the invention, the interfaces of the control chip are divided into three parts. The interface in the middle is electrically connected to the outside through the interposer, and the interfaces on both sides are correspondingly electrically connected to the memory particles on the same side.

[0014] As a further solution of the invention, the memory particles on each side of the control chip are orderly divided into several columns.

[0015] As a further solution of the invention, the number of interfaces on each side of the control chip is the same as the number of columns of the memory particles on the same side. The memory particles in each column are distributed in an S-shaped staggered manner and are electrically connected end to end.

[0016] As a further solution of the invention, the interposer includes a polymer layer, through which copper pillars are penetrated. On the upper and lower surfaces of the polymer layer, there are third RDL layers.

[0017] As a further solution of the invention, both ends of the copper pillars are electrically connected to the third RDL layers on both sides.

[0018] As a further solution of the invention, there are several layers of polymer layers, and the adjacent polymer layers are connected in a glued structure. The total thickness of the several polymer layers is the same as the height of the copper pillars.

[0019] As a further solution of the invention, a first RDL layer is jointly provided at the bottom of the interposer and the memory particles on both sides thereof, and a second RDL layer is jointly provided between the interposer and the memory particles on both sides thereof and the control chip and the memory particles on both sides thereof.

[0020] As a further solution of the invention, connection bumps for electrical connection to the outside are provided at the interfaces of the third RDL layers on both sides of the interposer, the interfaces on both sides of the memory particles, the interfaces on both sides of the first RDL layer, the interfaces on both sides of the second RDL layer, and the interfaces of the control chip.

[0021] As a further solution of the invention, the interposer, the control chip, the memory particles, the first RDL layer, and the second RDL layer are jointly encapsulated with a plastic encapsulation layer.

[0022] The beneficial effects of the present invention:

[0023] (1) During operation, the control chip is lifted by a certain height through an intermediate layer, enabling the memory particles to not only be stacked on both sides of the control chip to obtain a larger storage space, but also obtain a number of placement positions in an additional layer below the control chip, thereby greatly improving the overall storage space and storage capacity on the basis of a limited area;

[0024] (2) During operation, the communication rate of data is increased through an interleaved series structure and a shortened connection distance, further promoting the improvement of the overall data throughput and bandwidth;

[0025] (3) During operation, the distance of data communication is further reduced and the communication rate is increased through the stacking of the self-structure of the memory particles. Through the first RDL layer and the second RDL layer, both sides of each memory particle have the ability to communicate with the outside world, enabling different parts to set corresponding processes and circuit structures according to functional division and actual needs. In the stacking structure, technologies such as through-silicon vias, RDL, UBM, and metal bumps are used to not only increase the number of communication channels with each other, but also increase the capacity of the communication process, enabling the memory particles themselves to form a network and communicate and connect with each other after being set in large numbers, and further cooperating with the control chip to perform more complex logical operations;

[0026] (4) During operation, through the setting of copper pillars and the third RDL layer, the overall data communication rate can be improved, and different control chips and different memory particles can be adapted, so as to design the number and mounting structure of memory particles and control chips according to actual needs, making it more suitable for commercial design and production activities. Through the polymer layer, the manufacturing cost of the intermediate layer can be reduced, and the size of the intermediate layer can be flexibly adjusted;

[0027] (5) During operation, the overall electrical connection structure is reorganized and arranged through the first RDL layer and the second RDL layer, and the position of the electrical connection ports of the recombined chip is adjusted, so that the communication channels between the memory particles, the control chip, and the intermediate layer are greatly expanded and more reasonably arranged, which is more conducive to the mounting of the next-layer chip, and the electrical connection between the same-layer chips can also be established through the circuit production of the same-layer RDL layer;

[0028] (6) During operation, the position of the control chip is lifted through the intermediate layer, so that the chip group has a more complex three-dimensional distribution structure relative to the planar distribution, thereby greatly increasing the communication performance and storage performance of the chip group, and expanding the storage capacity, processing performance, and interaction performance of the chip group. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] For the convenience of those skilled in the art to understand, the present invention will be further described below with reference to the accompanying drawings.

[0030] Figure 1 Explosion structure schematic diagram of the chipset of the present invention;

[0031] Figure 2 Overall structure schematic diagram of the present invention;

[0032] Figure 3 is Figure 2 Front view of the sectional structure of the A-A section in

[0033] Figure 4 Overall structure schematic diagram of the interposer of the present invention;

[0034] Figure 5 is Figure 4 Front view of the sectional structure of the B-B section in

[0035] In the figure: 100, substrate; 200, chipset; 201, interposer; 202, control chip; 203, memory particles; 204, first RDL layer; 205, second RDL layer; 206, encapsulation layer; 301, polymer layer; 302, copper pillar; 303, third RDL layer; 304, connection bump. Specific embodiments

[0036] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific embodiments, structures, features and their effects of the present invention as follows.

[0037] Please refer to Figures 1-3 as shown: A chip packaging structure includes a substrate 100. A chipset 200 is welded and installed on the upper surface of the substrate 100. An interposer 201 is provided in the middle of the bottom layer of the chipset 200. A control chip 202 is provided on the top of the interposer 201. A plurality of memory particles 203 are provided on both sides of the interposer 201 and on both sides of the control chip 202. The memory particles 203 on both sides are electrically connected to each other and are both electrically connected to the control chip 202. The control chip 202 is electrically connected to the interposer 201;

[0038] The interfaces of the control chip 202 are divided into three parts. The interfaces in the middle are electrically connected to the outside through the interposer 201. The interfaces on both sides are electrically connected to the memory particles 203 on the same side correspondingly. The interfaces on both sides do not need to be symmetrical and can be designed as a symmetrical or asymmetrical distribution structure according to the product design requirements. The memory particles 203 on each side of the control chip 202 are orderly divided into several columns. The number of interfaces on each side is consistent with the number of columns of the memory particles 203 on the same side. The memory particles 203 in each column are distributed in an S-shaped staggered manner and are electrically connected end to end;

[0039] The control chip 202 can be a processor chip such as a central processing unit or a graphics processing unit;

[0040] During the operation of this embodiment, the 2.5D structure of the existing GPU and storage chip is changed to a 3D structure. The control chip 202 is lifted by one layer through the interposer 201, so that the memory particles 203 can not only be stacked on both sides of the control chip 202 to obtain a larger storage space, but also obtain a number of placement positions in an additional layer below the control chip 202. Thus, on the basis of a limited area, the overall storage space and storage capacity are greatly improved. At the same time, through the interleaved series structure and the shortened connection distance, the data communication rate is increased, further promoting the improvement of the overall data throughput and bandwidth.

[0041] The description and illustration of this application only show an optimal embodiment. In actual production, one or several columns of the memory particles 203 can be missing.

[0042] Please refer to Figure 4 and Figure 5 , the interposer 201 includes a polymer layer 301. Copper pillars 302 are penetrated in the polymer layer 301. Third RDL layers 303 are provided on both the upper and lower surfaces of the polymer layer 301, and both ends of the copper pillars 302 are electrically connected to the third RDL layers 303 on both sides. The polymer layer 301 has several layers, and adjacent polymer layers 301 are connected to each other in a glued connection structure. The total thickness of several polymer layers 301 is the same as the height of the copper pillars 302;

[0043] During the operation of this embodiment, the polymer layer 301 replaces the silicon material, and the copper pillars 302 replace the silicon vias for signal transmission functions. This can not only maintain the overall data communication efficiency, but also reduce the production cost of the interposer 201. At the same time, due to the characteristics of the adjustable thickness and size of the polymer layer 301 and the convenience of stacking, combined with the characteristics that the copper pillars 302 can be sized and heightened by photolithographic printing, the production difficulty of the interposer 201 is further reduced, and the overall external dimensions and structure of the interposer 201 can be quickly adapted according to different requirements during the production process, thereby improving the overall work efficiency and yield.

[0044] Please refer to Figure 3 , a first RDL layer 204 is provided at the bottom of the interposer 201 and the memory particles 203 on both sides thereof. A second RDL layer 205 is provided between the interposer 201 and the memory particles 203 on both sides thereof and the control chip 202 and the memory particles 203 on both sides thereof;

[0045] On both sides of the third RDL layer 303 interface of the interposer layer 201, both sides of the memory die 203, both sides of the first RDL layer 204, both sides of the second RDL layer 205, and the interface of the control chip 202, there are connection bumps 304 electrically connected to the outside;

[0046] When this embodiment works, the first RDL layer 204 and the second RDL layer 205 are used to reorganize and arrange the overall electrical connection structure, that is, through the secondary adjustment of the first RDL layer 204 and the second RDL layer 205, the respective electrical connection interfaces of the interposer layer 201, the control chip 202, and the memory die 203 are fixedly and stably connected correspondingly, avoiding the phenomenon of misalignment and other unstable connections due to production errors when the electrical connection interfaces are directly connected, improving the stability of the connection structure, greatly expanding and more reasonably arranging the communication channels between the memory die 203, the control chip 202, and the interposer layer 201, further improving the overall communication rate, and at the same time, through the spatial stacking and arrangement of its own physical size, increasing the number of memory chips, and improving the capacity and bandwidth.

[0047] Please refer to Figure 2 and Figure 3 , an encapsulation layer 206 is commonly encapsulated around the interposer layer 201, the control chip 202, the memory die 203, the first RDL layer 204, and the second RDL layer 205;

[0048] The chip group 200 and the memory die 203 are supported and protected by the encapsulation layer 206.

[0049] When the present invention works, the control chip 202 is lifted by a certain height through the interposer layer 201, so that the memory die 203 can not only be stacked on both sides of the control chip 202 to obtain a larger storage space, but also obtain a number of placement positions in an additional layer below the control chip 202, thereby greatly improving the overall storage space and storage capacity on the basis of a limited area;

[0050] The communication rate of data is improved through the interleaved series structure and the shortened connection distance, further promoting the improvement of the overall data throughput and bandwidth;

[0051] By further stacking the structures of the storage particles 203 themselves, the distance of data communication is reduced and the communication rate is increased. Through the first RDL layer 204 and the second RDL layer 205, both sides of each storage particle 203 have the ability to communicate with the outside world, enabling different parts to set corresponding processes and circuit structures according to functional divisions and actual requirements. In the stacked structure, technologies such as through-silicon vias, RDL, UBM, and metal bumps are used to not only increase the number of communication channels between each other but also increase the capacity of the communication process, enabling the storage particles 203 themselves to form a network and communicate and connect with each other after being set in large numbers, and further cooperating with the control chip 202 to perform more complex logical operations;

[0052] Through the settings of the copper pillars 302 and the third RDL layer 303, not only can the overall data communication rate be increased, but also different control chips 202 and different storage particles 203 can be adapted, facilitating the design of the number of storage particles 203 and control chips 202 and their mounting structures according to actual requirements, and being more suitable for commercial design and production activities. Through the polymer layer 301, the manufacturing cost of the interposer 201 can be reduced, and at the same time, the size of the interposer 201 can be flexibly adjusted;

[0053] Through the first RDL layer 204 and the second RDL layer 205, the overall electrical connection structure is reorganized and arranged, greatly expanding and more reasonably arranging the communication channels between the storage particles 203, the control chip 202, and the interposer 201, further increasing the overall communication rate. At the same time, through spatial stacking and arrangement of their own physical sizes, the number of storage chips is increased, and the capacity and bandwidth are improved;

[0054] By raising the position of the control chip 202 through the interposer 201, the chipset 200 has a more complex three-dimensional distribution structure compared to the planar distribution, thus greatly increasing the communication performance and storage performance of the chipset 200, and expanding the storage capacity, processing performance, and interaction performance of the chipset 200.

[0055] The above is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A chip packaging structure, characterized in that: The invention comprises a substrate (100), wherein a chipset (200) is welded and mounted on the upper surface of the substrate (100), an intermediate layer (201) is arranged in the middle of the bottom layer of the chipset (200), a control chip (202) is arranged on the top of the intermediate layer (201), a plurality of storage particles (203) are arranged on both sides of the intermediate layer (201) and both sides of the control chip (202), the storage particles (203) on both sides are electrically connected to each other and are electrically connected to the control chip (202), and the control chip (202) is electrically connected to the intermediate layer (201).

2. The chip packaging structure according to claim 1, characterized in that: The interface of the control chip (202) is divided into three parts, the interface located in the middle is electrically connected to the outside through the intermediate layer (201), and the interfaces located on both sides are electrically connected to the storage particles (203) on the same side accordingly.

3. The chip packaging structure according to claim 1, characterized in that: The storage particles (203) on each side of the control chip (202) are orderly divided into a plurality of columns.

4. The chip packaging structure according to claim 3, characterized in that: The number of interfaces on each side of the control chip (202) is consistent with the number of columns of storage particles (203) on the same side, and the storage particles (203) in each column are distributed in an S-shaped staggered manner and are electrically connected end to end.

5. The chip packaging structure according to claim 1, characterized in that: The intermediate layer (201) comprises a polymer layer (301), a copper column (302) is provided in the polymer layer (301), and a third RDL layer (303) is provided on both the upper and lower surfaces of the polymer layer (301).

6. The chip packaging structure according to claim 5, characterized in that: Two ends of the copper column (302) are electrically connected to the third RDL layer (303) on both sides respectively.

7. The chip packaging structure according to claim 5, characterized in that: The polymer layer (301) is provided with a plurality of layers, and adjacent polymer layers (301) are mutually bonded and connected in a structure, and the total thickness of the plurality of polymer layers (301) is consistent with the height of the copper column (302).

8. The chip packaging structure according to claim 5, characterized in that: A first RDL layer (204) is provided at the bottom of the intermediate layer (201) and the storage particles (203) on both sides thereof, and a second RDL layer (205) is provided between the intermediate layer (201) and the storage particles (203) on both sides thereof and the control chip (202) and the storage particles (203) on both sides thereof.

9. The chip packaging structure according to claim 8, characterized in that: The interfaces of the third RDL layer (303) on both sides of the intermediate layer (201), the interfaces on both sides of the storage particles (203), the interfaces on both sides of the first RDL layer (204), the interfaces on both sides of the second RDL layer (205) and the interface of the control chip (202) are all provided with connection bumps (304) electrically connected to the outside world.

10. The chip packaging structure according to claim 8, characterized in that: The intermediate layer (201), the control chip (202), the storage particles (203), the first RDL layer (204) and the second RDL layer (205) are collectively sealed with a plastic sealing layer (206) at their peripheries.

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