GaAs-based enhanced / depletion type PHEMT structure, epitaxial structure and preparation method thereof

Abstract

The invention provides a GaAs-based enhanced / depletion type PHEMT structure, an epitaxial structure and a preparation method thereof. An epitaxial insertion layer composed of a GaAs insertion layer and a GaP insertion layer is arranged between a second AlGaAs barrier layer (an enhanced barrier layer) and an InGaP barrier layer (a depletion barrier layer), the GaAs insertion layer and the GaP insertion layer are sequentially grown after the second AlGaAs barrier layer is grown, and then the InGaP barrier layer is grown, so that a low-band-gap InGaAs or InGaAsP intermediate layer generated by the influence of an As and P exchange process can be effectively avoided, and the performance of the device is improved. Meanwhile, the epitaxial insertion layer can reduce and even avoid the risk that As atoms in the second AlGaAs barrier layer diffuse into the InGaP barrier layer to generate an InGaAsP low-band-gap interface layer, and the effect of optimizing the growth interface of the second AlGaAs barrier layer and the InGaP barrier layer and the growth quality of the barrier layer is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of HEMT semiconductors, and particularly to a GaAs-based enhancement / depletion PHEMT structure, an epitaxial structure and a preparation method thereof. Background Art

[0002] Gallium arsenide, as a mature compound semiconductor material, has a high breakdown voltage and is widely used in ultra-high speed and ultra-high frequency devices. The gallium arsenide-based pseudomorphic high electron mobility transistor (GaAs-based PHEMT) has characteristics such as high frequency, high power gain and low noise, and thus is widely used in communication fields such as optical fiber communication, microwave communication and satellite communication, as well as in integrated circuits. In a GaAs-based PHEMT, due to a lattice mismatch of about 1% between InGaAs (channel layer) and GaAs, the InGaAs channel layer is usually grown very thin to distort its lattice so as to absorb stress, and this structure is usually called a pseudomorphic structure.

[0003] With the development of the GaAs-based PHEMT structure, four basic logic circuit forms of GaAs ICs have been proposed: BFL (Buffered FET Logic); SDFL (Schottky Diode FET Logic); SCFL (Source Couple FET Logic); DCFL (Direct Coupled FET Logic). The first three are based on depletion-type field effect transistors, and the latter DCFL is based on enhancement / depletion-type field effect transistors. BFL, SCFL and SDFL require the use of dual power supplies or negative power supplies and there is a level shift, resulting in a complex structure and high power consumption of the GaAs IC logic circuit, and large-scale integrated circuit design cannot be realized. The advantages of the DCFL logic circuit such as low power consumption, high speed, very simple circuit structure (such as no level shift) and single power supply make it one of the best logic technologies in large-scale integrated circuits.

[0004] The quality of the GaAs-based enhancement / depletion PHEMT epitaxial structure plays a decisive role in the important performance of the final product. In the existing GaAs-based enhancement / depletion PHEMT epitaxial structure, AlGaAs is used as the enhancement-type barrier layer and InGaP is grown thereon as the depletion-type barrier layer. The barrier layer is an important device layer that restricts the movement of two-dimensional electron gas (2-DEG) to form a quantum well. Therefore, the material growth of high-quality AlGaAs enhancement-type barrier layer and InGaP depletion-type barrier layer is the basis for realizing the device structure performance of GaAs-based enhancement / depletion PHEMT. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a GaAs-based enhancement / depletion PHEMT structure, an epitaxial structure and a preparation method thereof, which are used to solve the problem of low material growth quality of the AlGaAs enhancement barrier layer and the InGaP depletion barrier layer in the GaAs-based enhancement / depletion PHEMT epitaxial structure in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a GaAs-based enhancement / depletion PHEMT epitaxial structure, and the epitaxial structure includes:

[0007] a substrate; and

[0008] a buffer layer, a first AlGaAs barrier layer, a first AlGaAs isolation layer, an InGaAs channel layer, a second AlGaAs isolation layer, a second AlGaAs barrier layer, an epitaxial insertion layer, an InGaP barrier layer and a GaAs cap layer, which are arranged in sequence from bottom to top on one side of the substrate;

[0009] wherein, the epitaxial insertion layer includes a GaAs insertion layer and a GaP insertion layer in sequence from bottom to top;

[0010] the buffer layer includes a GaAs buffer layer and a superlattice buffer layer composed of an AlGaAs layer / GaAs layer in sequence from bottom to top.

[0011] Optionally, the thickness of the GaAs insertion layer is 0.25 nm to 0.35 nm, and the thickness of the GaP insertion layer is 0.3 nm to 0.6 nm.

[0012] Optionally, the upper surface of the first AlGaAs barrier layer is subjected to first silicon δ doping, the upper surface of the second AlGaAs isolation layer is subjected to second silicon δ doping, and the doping concentration of the second silicon δ doping is 2.9 to 3.1 times that of the first silicon δ doping; preset thicknesses are set for the upper and lower surfaces of the InGaAs channel layer as GaAs growth transition layers, and the component of the remaining thickness of the InGaAs channel layer is denoted as In x Ga 1-x As layer, where the component x of In takes a value of 0.25 < x < 0.3, and the In x Ga 1-x As layer is doped with silicon with a gradually increasing doping concentration from bottom to top.

[0013] Furthermore, the In in the InGaAs channel layer x Ga 1-xThe thickness of the As layer is 8 nm to 10 nm, and the thickness of the GaAs growth transition layer is 0.9 nm to 1.1 nm; the x Ga 1-x silicon doping concentration in the As layer gradually changes from 2E17 cm -3 to 4E17 cm -3 .

[0014] Further, the doping concentration of the first silicon δ-doping is 1.4E12 cm -2 to 1.6E12 cm -2 , and the doping concentration of the second silicon δ-doping is 4.2E12 cm -2 to 4.8E12 cm -2 .

[0015] Optionally, the GaAs cap layer is a silicon-doped GaAs cap layer, and the doping concentration of silicon is 0.5E19 cm -3 to 1.0E19 cm -3 .

[0016] Further, the thickness of the GaAs buffer layer is 100 nm to 200 nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer is 9 nm to 11 nm, and the single-layer thickness of the GaAs layer is 1.3 nm to 1.7 nm; the thickness of the first AlGaAs barrier layer is 30 nm to 40 nm; the thickness of the first AlGaAs isolation layer is 5 nm to 10 nm; the thickness of the second AlGaAs isolation layer is 5 nm to 10 nm; the thickness of the second AlGaAs barrier layer is 6 nm to 10 nm; the thickness of the InGaP barrier layer is 30 nm to 35 nm; the thickness of the GaAs cap layer is 48 nm to 52 nm.

[0017] The present invention also provides a method for preparing a GaAs-based enhancement / depletion type PHEMT epitaxial structure, and the preparation method includes the following steps:

[0018] S1: Provide a substrate;

[0019] S2: Grow a GaAs buffer layer and a superlattice buffer layer composed of an AlGaAs layer / GaAs layer on one side of the substrate in sequence, and the growth temperature is 580 °C to 600 °C;

[0020] S3: Grow a first AlGaAs barrier layer on the superlattice buffer layer;

[0021] S4: Grow a first AlGaAs isolation layer on the first AlGaAs barrier layer;

[0022] S5: Grow an InGaAs channel layer on the first AlGaAs isolation layer at a growth temperature of 480°C to 500°C;

[0023] S6: Raise the temperature to 580°C to 600°C and grow a second AlGaAs isolation layer on the InGaAs channel layer;

[0024] S7: Grow a second AlGaAs barrier layer and a GaAs insertion layer in sequence on the second AlGaAs isolation layer;

[0025] S8: Lower the temperature to 500°C to 520°C and grow a GaP insertion layer and an InGaP barrier layer in sequence on the GaAs insertion layer;

[0026] S9: Grow a GaAs cap layer on the InGaP barrier layer.

[0027] Optionally, in step S4, perform a first silicon δ-doping on the upper surface of the first AlGaAs barrier layer and then grow the first AlGaAs isolation layer; a GaAs growth transition layer with a preset thickness is provided on the upper and lower surfaces of the InGaAs channel layer formed in step S5, and the composition of the InGaAs channel layer with the remaining thickness is denoted as an In x Ga 1-x As layer, where the component x of In has a value of 0.25 < x < 0.3, and the In x Ga 1-x As layer is doped with silicon with a gradually increasing doping concentration from bottom to top; perform a second silicon δ-doping on the upper surface of the second AlGaAs isolation layer after the second AlGaAs isolation layer is formed in step S6.

[0028] The present invention also provides a GaAs-based enhancement / depletion type PHEMT structure, and the PHEMT structure is prepared based on the GaAs-based enhancement / depletion type PHEMT epitaxial structure described in any one of the above.

[0029] As described above, in the GaAs-based enhancement / depletion PHEMT structure, epitaxial structure and preparation method thereof of the present invention, by arranging an epitaxial insertion layer composed of a GaAs insertion layer and a GaP insertion layer between the second AlGaAs barrier layer (enhancement-type barrier layer) and the InGaP barrier layer (depletion-type barrier layer), after the growth of the second AlGaAs barrier layer, the GaAs insertion layer and the GaP insertion layer are successively grown first, and then the InGaP barrier layer is grown, which can effectively avoid the influence of the As and P exchange process to generate a low-bandgap InGaAs or InGaAsP intermediate layer. At the same time, the epitaxial insertion layer can also reduce or even avoid the risk that As atoms in the second AlGaAs barrier layer diffuse into the InGaP barrier layer to generate an InGaAsP low-bandgap interface layer, achieving the effect of optimizing the growth interfaces of the second AlGaAs barrier layer and the InGaP barrier layer and the growth quality of the barrier layer. Description of the Drawings

[0030] Figure 1 It shows a schematic cross-sectional structure diagram of a GaAs-based enhancement / depletion PHEMT epitaxial structure according to an embodiment of the present invention.

[0031] Figure 2 It shows a schematic cross-sectional structure diagram of the InGaAs channel layer in this embodiment.

[0032] Figure 3 It shows a schematic cross-sectional structure diagram of the epitaxial insertion layer in this embodiment.

[0033] Figure 4 It shows a schematic shutter sequence diagram during the growth from the enhancement-type barrier layer to the GaAs cap layer in the preparation method of a GaAs-based enhancement / depletion PHEMT epitaxial structure according to an embodiment of the present invention.

[0034] Figure 5 It shows a schematic flow diagram of the preparation method of a GaAs-based enhancement / depletion PHEMT epitaxial structure according to an embodiment of the present invention.

[0035] Description of Component Labels

[0036] 10 Substrate

[0037] 11 Buffer layer

[0038] 110 GaAs buffer layer

[0039] 111 Superlattice buffer layer

[0040] 12 First AlGaAs barrier layer

[0041] 120 First silicon δ-doping

[0042] 13 First AlGaAs isolation layer

[0043] 14 InGaAs channel layer

[0044] 140 GaAs growth transition layer

[0045] 141 In x Ga 1-x As layer

[0046] 15 Second AlGaAs isolation layer

[0047] 150 Second silicon δ-doping

[0048] 16 Second AlGaAs barrier layer

[0049] 17 Epitaxial insertion layer

[0050] 170 GaAs insertion layer

[0051] 171 GaP insertion layer

[0052] 18 InGaP barrier layer

[0053] 19 GaAs cap layer Detailed implementation manners

[0054] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For the sake of description, spatial relative terms such as "above...", "over...", "on the upper surface of...", "above" etc. can be used here to describe the spatial position relationship between a device or feature shown in the figure and other devices or features. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device shown in the figure. For example, if the device in the figure is inverted, the device described as "above other devices or structures" or "over other devices or structures" will then be positioned as "below other devices or structures" or "under other devices or structures". Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding explanations are made for the spatial relative descriptions used here.

[0056] It should be understood that the use of terms such as "first", "second", "third", etc. to limit components is only for the convenience of distinguishing the above components. Without additional statements, these terms have no special meaning, and thus should not be construed as limiting the scope of protection of the present invention.

[0057] Please refer to Figures 1 to 5 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout type of its components may also be more complex.

[0058] Such as Figure 1 and Figure 3 As shown, this embodiment provides a GaAs-based enhancement / depletion type PHEMT epitaxial structure, and the epitaxial structure includes:

[0059] Substrate 10; and

[0060] A buffer layer 11, a first AlGaAs barrier layer 12, a first AlGaAs isolation layer 13, an InGaAs channel layer 14, a second AlGaAs isolation layer 15, a second AlGaAs barrier layer 16, an epitaxial insertion layer 17, an InGaP barrier layer 18, and a GaAs cap layer 19, which are arranged in sequence from bottom to top on one side of the substrate 10;

[0061] Wherein, the epitaxial insertion layer 17 sequentially includes a GaAs insertion layer 170 and a GaP insertion layer 171 from bottom to top;

[0062] The buffer layer 11 sequentially includes a GaAs buffer layer 110 and a superlattice buffer layer 111 composed of an AlGaAs layer / GaAs layer from bottom to top.

[0063] In a GaAs-based enhancement / depletion PHEMT epitaxial structure, when an AlGaAs barrier layer (enhancement barrier layer) is in direct contact with an InGaP barrier layer (depletion barrier layer), on the one hand, due to the influence of the As and P exchange process (P-to-As exchange process), a low-bandgap InGaAs or InGaAsP intermediate layer will be formed at the interface between the two; on the other hand, As atoms are prone to form a diffusion effect (Diffusion of As atoms from a surface layer deeper into the bulk InGaP). Prolonged irradiation of As will cause As to diffuse into the InGaP material, forming an InGaAsP interface layer. Since the bandgap of InGaAs or InGaAsP is lower than that of InGaP or AlGaAs, the position of the interface PL peak is not completely determined by the energy band offset between InGaP and AlGaAs, thus affecting the energy band offset between the AlGaAs barrier layer and the InGaP barrier layer, and further reducing the performance of the GaAs-based enhancement / depletion PHEMT device. In this embodiment, an epitaxial insertion layer 17 composed of a GaAs insertion layer 170 and a GaP insertion layer 171 is provided between the second AlGaAs barrier layer 16 (enhancement barrier layer) and the InGaP barrier layer 18 (depletion barrier layer). After the growth of the second AlGaAs barrier layer 16, the GaAs insertion layer 170 and the GaP insertion layer 171 are grown in sequence first, and then the InGaP barrier layer 18 is grown, which can effectively avoid the formation of a low-bandgap InGaAs or InGaAsP intermediate layer caused by the influence of the As and P exchange process. At the same time, the epitaxial insertion layer 17 can also reduce or even avoid the risk of As atoms in the second AlGaAs barrier layer 16 diffusing into the InGaP barrier layer 18 to form a low-bandgap InGaAsP interface layer, achieving the effect of optimizing the growth interface of the second AlGaAs barrier layer 16 and the InGaP barrier layer 18 and the growth quality of the barrier layer.

[0064] As a preferred example, the thickness of the GaAs insertion layer 170 is 0.25 nm to 0.35 nm, and the thickness of the GaP insertion layer 171 is 0.3 nm to 0.6 nm. More preferably, the thickness of the GaAs insertion layer 170 is about 0.3 nm, and the thickness of the GaP insertion layer 171 can be selected within the range of 0.3 nm to 0.6 nm.

[0065] As another preferred example, as Figure 1 and Figure 2As shown, the upper surface of the first AlGaAs barrier layer 12 is subjected to a first silicon δ-doping 120, and the upper surface of the second AlGaAs isolation layer 15 is subjected to a second silicon δ-doping 150. The doping concentration of the second silicon δ-doping 150 is 2.9 to 3.1 times, more preferably 3 times, that of the first silicon δ-doping 120. The upper and lower surfaces of the InGaAs channel layer 14 are provided with GaAs growth transition layers 140 with a preset thickness, and the composition of the InGaAs channel layer with the remaining thickness is denoted as In x Ga 1-x As layer 141, where the component x of In has a value of 0.25 < x < 0.3, and the In x Ga 1-x As layer 141 is doped with silicon with a gradually increasing doping concentration from bottom to top (i.e., along the growth direction). While taking into account the influence of the In / As content in the channel layer on lattice mismatch, the In / As content in the channel layer is moderately increased (x has a value of 0.25 < x < 0.3) to effectively improve the electron transport speed in the channel. Additionally, a graded doping of silicon is added to the channel layer and the silicon δ-doping ratio on both the upper and lower sides of the channel layer is synergistically changed (2.9 to 3.1 times), which can effectively improve the efficiency of electrons transferring from the silicon δ-doping layer to the channel layer in the epitaxial layer, increase the 2DEG density in the channel, and improve the distribution of 2DEG, making the electron distribution in the channel approach a square well, that is, making the electron distribution in the channel more uniform, thereby improving the linearity of the PHEMT device and making the PHEMT device more suitable for high-linearity applications of microwave power devices. It can also improve the Ids performance of the PHEMT device and the noise performance of the PHEMT device.

[0066] Furthermore, as Figure 2 shown, the thickness of the In x Ga 1-x As layer 141 in the InGaAs channel layer 14 is 8 nm to 10 nm; the thickness of the GaAs growth transition layer 140 is 0.9 nm to 1.1 nm, and can be, for example, 0.9 nm, 1.0 nm, 1.1 nm; the silicon doping concentration in the In x Ga 1-x As layer 141 gradually changes from 2E17 cm -3 to 4E17 cm -3 . More preferably, as Figure 1 shown, the doping concentration of the first silicon δ-doping 120 is 1.4E12 cm -2 to 1.6E12 cm -2 , and the doping concentration of the second silicon δ-doping 150 is 4.2E12 cm -2 to 4.8E12 cm -2Preferably, the doping concentration of the first silicon δ-doped layer 120 is 1.5E12 cm -2 , and the doping concentration of the second silicon δ-doped layer 150 is 4.5E12 cm -2 .

[0067] As an example, the GaAs cap layer 19 is a silicon-doped GaAs cap layer, and the doping concentration of silicon is 0.5E19 cm -3 ~1.0E19 cm -3 .

[0068] As a specific example, the thickness values of each layer in the GaAs-based enhancement / depletion PHEMT epitaxial structure are as follows: the thickness of the GaAs buffer layer 110 is 100 nm to 200 nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer 111 is 9 nm to 11 nm (preferably 10 nm), and the single-layer thickness of the GaAs layer is 1.3 nm to 1.7 nm (preferably 1.5 nm), and the cycle period is 18 to 22 (preferably 20); the thickness of the first AlGaAs barrier layer 12 is 30 nm to 40 nm; the thickness of the first AlGaAs isolation layer 13 is 5 nm to 10 nm; the In x Ga 1-x As layer 141 in the InGaAs channel layer 14 has a thickness of 8 nm to 10 nm, and the thickness of the GaAs growth transition layer 140 is 0.9 nm to 1.1 nm (preferably 1 nm); the thickness of the second AlGaAs isolation layer 15 is 5 nm to 10 nm; the thickness of the second AlGaAs barrier layer 16 is 6 nm to 10 nm; the thickness of the GaAs insertion layer 170 is 0.25 nm to 0.35 nm (preferably 0.3 nm), and the thickness of the GaP insertion layer 171 is 0.3 nm to 0.6 nm; the thickness of the InGaP barrier layer 18 is 30 nm to 35 nm; the thickness of the GaAs cap layer 19 is 48 nm to 52 nm (preferably 50 nm).

[0069] As a specific example, when the AlGaAs material is involved in the GaAs-based enhancement / depletion PHEMT epitaxial structure, its composition is denoted as Al x Ga 1-x As, where the composition x of Al ranges from 0.2 < x < 0.3; when the InGaP material is involved, its composition is denoted as In y Ga 1-y P, where the composition y of In ranges from 0.49 < x < 0.51.

[0070] This embodiment also provides a method for preparing a GaAs-based enhancement / depletion PHEMT epitaxial structure for preparing the above-mentioned GaAs-based enhancement / depletion PHEMT epitaxial structure. Figure 5 It is a schematic flow chart of the method for preparing the GaAs-based enhancement / depletion PHEMT epitaxial structure of this embodiment. Figure 1 It is a GaAs-based enhancement / depletion PHEMT epitaxial structure obtained by using this preparation method. The preparation method includes the following steps:

[0071] S1: Provide a substrate;

[0072] S2: Grow a GaAs buffer layer and a superlattice buffer layer composed of an AlGaAs layer / GaAs layer on one side of the substrate in sequence, and the growth temperature is 580°C to 600°C;

[0073] S3: Grow a first AlGaAs barrier layer on the superlattice buffer layer;

[0074] S4: Grow a first AlGaAs isolation layer on the first AlGaAs barrier layer;

[0075] S5: Grow an InGaAs channel layer on the first AlGaAs isolation layer, and the growth temperature is 480°C to 500°C;

[0076] S6: Raise the temperature to 580°C to 600°C, and grow a second AlGaAs isolation layer on the InGaAs channel layer;

[0077] S7: Grow a second AlGaAs barrier layer and a GaAs insertion layer on the second AlGaAs isolation layer in sequence;

[0078] S8: Lower the temperature to 500°C to 520°C, and grow a GaP insertion layer and an InGaP barrier layer on the GaAs insertion layer in sequence;

[0079] S9: Grow a GaAs cap layer on the InGaP barrier layer.

[0080] As an example, the method for preparing the GaAs-based enhancement / depletion PHEMT epitaxial structure of this embodiment is prepared by molecular beam epitaxy (MBE). Further, the "growth interruption method" is adopted during molecular beam epitaxy to improve the crystallization quality of the epitaxial thin film, control the interface characteristics or realize a specific material structure.

[0081] Specifically, such as Figure 1As shown, in step S1, a substrate 10 is provided. The substrate 10 includes, but is not limited to, a gallium arsenide substrate of 2 inches, 4 inches, 6 inches, or 8 inches, and a composite substrate composed of a silicon-based gallium arsenide. In this embodiment, a semi-insulating GaAs substrate is used as the substrate 10 for growing the epitaxial structure.

[0082] As an example, in step S2, a GaAs buffer layer 110 is grown on the substrate 10. Generally, the thickness is 100 nm to 200 nm, which can flatten the surface of the substrate 10 after high-temperature deoxidation. The superlattice buffer layer 111 grown on the GaAs buffer layer 110 can sufficiently prevent the defects of the substrate 10 from extending to the channel within a short growth time to ensure the quality of the channel layer adjacent to the buffer layer. The single-layer thickness of the AlGaAs layer in the superlattice buffer layer 111 is 9 nm to 11 nm (the preferred value is 10 nm), the single-layer thickness of the GaAs layer is 1.3 nm to 1.7 nm (the preferred value is 1.5 nm), and the cycle period is 18 to 22 (the preferred value is 20). In step S3, the thickness of the grown first AlGaAs barrier layer 12 is 30 nm to 40 nm. In step S4, the thickness of the grown first AlGaAs isolation layer 13 is 5 nm to 10 nm. In step S5, the In x Ga 1-x As layer 141 in the grown InGaAs channel layer 14 has a thickness of 8 nm to 10 nm, and the GaAs growth transition layer 140 has a thickness of 0.9 nm to 1.1 nm (the preferred value is 1 nm). In step S6, the thickness of the grown second AlGaAs isolation layer 15 is 5 nm to 10 nm. In step S7, the thickness of the grown second AlGaAs barrier layer 16 is 6 nm to 10 nm, and the GaAs insertion layer 170 has a thickness of 0.25 nm to 0.35 nm (the preferred value is 0.3 nm). In step S8, the thickness of the grown GaP insertion layer 171 is 0.3 nm to 0.6 nm, and the thickness of the InGaP barrier layer 18 is 30 nm to 35 nm. In step S9, the thickness of the grown GaAs cap layer 19 is 48 nm to 52 nm (the preferred value is 50 nm).

[0083] In the preparation method of the GaAs-based enhancement / depletion type PHEMT epitaxial structure in this embodiment, when growing AlGaAs materials and GaAs materials, the same growth temperature is adopted. For example, the growth temperature in step S1 is 580 °C to 600 °C.

[0084] As Figure 4As shown, it is a schematic diagram of the shutter sequence during the growth of the enhancement barrier layer (i.e., the second AlGaAs barrier layer 16) to the GaAs cap layer 19 in the preparation method of the GaAs-based enhancement / depletion PHEMT epitaxial structure of this embodiment. Combining Figure 1 and Figure 4 , where: the a time period is the growth time of the second AlGaAs barrier layer 16, and the specific growth time is determined according to the thickness and growth rate; the b time period is the growth time of the GaAs insertion layer 170, which is used to protect the second AlGaAs barrier layer 16 and prevent it from being affected by the environment in the MBE chamber during the growth temperature change waiting process. In addition, during the protection of the As / P switching process, it protects the influence of the P element on the material composition; the c time period is the temperature change time of the growth temperature between the second AlGaAs barrier layer 16 and the InGaP barrier layer 18. During this process, the As source is continuously introduced to protect the growth surface. There is a large temperature difference between the growth temperatures of the AlGaAs material and the InGaP material. As described above, the growth temperature of the second AlGaAs barrier layer 16 is 580 °C to 600 °C, and the growth temperature of the InGaP barrier layer 18 is 500 °C to 520 °C; the d time period is the As / P exchange process time in the structure of the second AlGaAs barrier layer 16 and the InGaP barrier layer 18; the e time period is the stable time of the P atmosphere after the As / P exchange; the f time period is the growth time of the GaP insertion layer 171, which is used to protect the InGaP barrier layer 18 (depletion barrier layer). As the interface between the arsenide and phosphide materials, it protects the energy level of the depletion barrier layer and improves the growth quality of the barrier layer; the g time period is the growth time of the InGaP barrier layer 18, and the specific growth time is determined according to the thickness and growth rate; the h time period is the temperature change time of the growth temperature between the InGaP barrier layer 18 and the GaAs cap layer 19. During this process, the P source is continuously introduced to protect the growth surface; the i time period is the As / P exchange process time to prevent the diffusion effect of As atoms; the j time period is the growth time of the GaAs cap layer 19; the k time period is the temperature reduction time after the growth ends.

[0085] As Figure 1 shown, as a preferred example, in step S4, the upper surface of the first AlGaAs barrier layer 12 is first subjected to the first silicon δ doping 120 and then the first AlGaAs isolation layer 13 is grown; as Figure 2 shown, on the upper and lower surfaces of the InGaAs channel layer 14 formed in step S5, GaAs growth transition layers 140 with a preset thickness are provided, and the composition of the remaining thickness of the InGaAs channel layer 14 is denoted as In x Ga 1-x As layer 141, where the component x of In takes a value of 0.25 < x < 0.3, and the In x Ga1-x The As layer 141 is doped with silicon with a gradually increasing doping concentration from bottom to top; after the second AlGaAs isolation layer 15 is formed in step S6, a second silicon δ-doping 150 is performed on its upper surface.

[0086] This embodiment also provides a GaAs-based enhancement / depletion PHEMT structure, and the PHEMT structure is prepared based on the GaAs-based enhancement / depletion PHEMT epitaxial structure described in this embodiment.

[0087] In summary, the present invention provides a GaAs-based enhancement / depletion PHEMT structure, an epitaxial structure, and a preparation method thereof. By providing an epitaxial insertion layer composed of a GaAs insertion layer and a GaP insertion layer between the second AlGaAs barrier layer (enhancement-type barrier layer) and the InGaP barrier layer (depletion-type barrier layer), after the growth of the second AlGaAs barrier layer, the GaAs insertion layer and the GaP insertion layer are sequentially grown first, and then the InGaP barrier layer is grown, which can effectively avoid the influence of the As and P exchange process to generate a low-bandgap InGaAs or InGaAsP intermediate layer. At the same time, the epitaxial insertion layer can also reduce or even avoid the risk of As atoms in the second AlGaAs barrier layer diffusing into the InGaP barrier layer to generate an InGaAsP low-bandgap interface layer, achieving the effect of optimizing the growth interface of the second AlGaAs barrier layer and the InGaP barrier layer and the growth quality of the barrier layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0088] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A GaAs-based enhancement / depletion mode PHEMT epitaxial structure, characterized in that: The epitaxial structure comprises: substrate; and A buffer layer, a first AlGaAs barrier layer, a first AlGaAs isolation layer, an InGaAs channel layer, a second AlGaAs isolation layer, a second AlGaAs barrier layer, an epitaxial insertion layer, an InGaP barrier layer and a GaAs cap layer are arranged in sequence from bottom to top on one side of the substrate; Wherein, the epitaxial insertion layer includes a GaAs insertion layer and a GaP insertion layer in order from bottom to top; The buffer layer includes, from bottom to top, a GaAs buffer layer and a superlattice buffer layer composed of an AlGaAs layer / GaAs layer.

2. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 1, characterized in that: The thickness of the GaAs insertion layer is 0.25nm-0.35nm, and the thickness of the GaP insertion layer is 0.3nm-0.6nm.

3. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 1, characterized in that: The upper surface of the first AlGaAs barrier layer is doped with a first silicon delta, and the upper surface of the second AlGaAs isolation layer is doped with a second silicon delta, and the doping concentration of the second silicon delta doping is 2.9 to 3.1 times the doping concentration of the first silicon delta doping; the preset thickness of the upper and lower surfaces of the InGaAs channel layer is set to a GaAs growth transition layer, and the remaining thickness of the InGaAs channel layer component is recorded as In x Ga 1-x As layer, wherein the In component x is 0.25<x<0.3, and the In x Ga 1- x The As layer is doped with silicon with increasing doping concentration from bottom to top.

4. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 3, characterized in that: The InGaAs in the channel layer x Ga 1-x The thickness of the As layer is 8nm to 10nm, the thickness of the GaAs growth transition layer is 0.9nm to 1.1nm; x Ga 1-x The silicon doping concentration in the As layer is 2E17cm -3 Gradually to 4E17cm -3 .

5. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 4, characterized in that: The doping concentration of the first silicon delta doping is 1.4E12cm -2 ~1.6E12cm -2 The doping concentration of the second silicon delta doping is 4.2E12cm -2 ~4.8E12cm -2 .

6. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 1, characterized in that: The GaAs cap layer is a silicon-doped GaAs cap layer, and the doping concentration of silicon is 0.5E19cm -3 ~1.0E19cm -3 .

7. The GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to any one of claims 1 to 6, characterized in that: The thickness of the GaAs buffer layer is 100nm to 200nm; the single-layer thickness of the AlGaAs layer in the superlattice buffer layer is 9nm to 11nm, and the single-layer thickness of the GaAs layer is 1.3nm to 1.7nm; the thickness of the first AlGaAs barrier layer is 30nm to 40nm; the thickness of the first AlGaAs isolation layer is 5nm to 10nm; the thickness of the second AlGaAs isolation layer is 5nm to 10nm; the thickness of the second AlGaAs barrier layer is 6nm to 10nm; the thickness of the InGaP barrier layer is 30nm to 35nm; and the thickness of the GaAs cap layer is 48nm to 52nm.

8. A method for preparing a GaAs-based enhancement / depletion mode PHEMT epitaxial structure, characterized in that: The preparation method comprises the following steps: S1: providing a substrate; S2: sequentially growing a GaAs buffer layer and a superlattice buffer layer consisting of an AlGaAs layer / GaAs layer on one side of the substrate, at a growth temperature of 580° C. to 600° C.; S3: growing a first AlGaAs barrier layer on the superlattice buffer layer; S4: growing a first AlGaAs isolation layer on the first AlGaAs barrier layer; S5: growing an InGaAs channel layer on the first AlGaAs isolation layer at a growth temperature of 480° C. to 500° C.; S6: raising the temperature to 580° C. to 600° C., and growing a second AlGaAs isolation layer on the InGaAs channel layer; S7: sequentially growing a second AlGaAs barrier layer and a GaAs insertion layer on the second AlGaAs isolation layer; S8: lowering the temperature to 500° C. to 520° C., and sequentially growing a GaP insertion layer and an InGaP barrier layer on the GaAs insertion layer; S9: growing a GaAs cap layer on the InGaP barrier layer.

9. The method for preparing a GaAs-based enhancement / depletion mode PHEMT epitaxial structure according to claim 8, characterized in that: In step S4, the first AlGaAs barrier layer is first doped with silicon delta and then the first AlGaAs isolation layer is grown; in step S5, the upper and lower surfaces of the InGaAs channel layer formed have a preset thickness of a GaAs growth transition layer, and the remaining thickness of the InGaAs channel layer is recorded as InGaAs. x Ga 1-x As layer, wherein the In component x is 0.25<x<0.3, and the In x Ga 1-x The As layer is doped with silicon from bottom to top with a gradually increasing doping concentration; after the second AlGaAs isolation layer is formed in step S6, a second silicon delta doping is performed on the upper surface thereof.

10. A GaAs-based enhancement / depletion mode PHEMT structure, characterized in that: The PHEMT structure is prepared based on the GaAs-based enhancement / depletion mode PHEMT epitaxial structure described in any one of claims 1 to 7.

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