Single-layer capacitor

Abstract

A single-layer capacitor may include a substrate having a first surface and a second surface opposite the first surface. A resistive layer may be formed on at least a portion of the first surface of the substrate. A first conductive layer may be formed on at least a portion of the resistive layer. A second conductive layer may be formed on at least a portion of the second surface of the substrate. Accordingly, the single-layer capacitor may include a resistor and a capacitor formed in series with each other.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 418,107, filed on October 21, 2022, which is incorporated herein by reference. BACKGROUND OF THE INVENTION

[0003] Single layer capacitors (SLCs) offer various benefits such as temperature stability, generally higher breakdown voltages, and lower leakage currents. However, generally, the frequency response of SLCs may limit their ultimate applications. Increasing the equivalent series resistance (ESR) can broaden the applications of SLCs. SUMMARY OF THE INVENTION

[0004] According to one embodiment of the present disclosure, a single layer capacitor may include a substrate having a first surface and a second surface opposite the first surface. A resistive layer may be formed on at least a portion of the first surface of the substrate. A first conductive layer may be formed on at least a portion of the resistive layer. A second conductive layer may be formed on at least a portion of the second surface of the substrate.

[0005] According to another embodiment of the present disclosure, a method for forming a single layer capacitor may include: depositing a resistive layer on at least a portion of a first surface of a substrate; depositing a first conductive layer on at least a portion of the resistive layer; and depositing a second conductive layer on at least a portion of a second surface of the substrate opposite the first surface.

[0006] According to another embodiment of the present disclosure, an embedded capacitor assembly may include: a circuit board substrate having a mounting surface; and a single layer capacitor at least partially embedded within the circuit board substrate. The single layer capacitor may include: a substrate having a first surface opposite a second surface; a resistive layer formed on at least a portion of the first surface; a first conductive layer formed on at least a portion of the resistive layer; and a second conductive layer formed on at least a portion of the second surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the remaining part of the specification that refers to the drawings, the complete and enabling disclosure of the invention, including its best mode, is set forth more specifically for those of ordinary skill in the art, in which:

[0008] Figure 1A is a side view of a capacitor according to aspects of the present disclosure;

[0009] Figure 1B is a side view of another capacitor according to aspects of the present disclosure;

[0010] Figure 1C is a side view of yet another capacitor according to aspects of the present disclosure;

[0011] Figure 2A is a top view of a capacitor according to aspects of the present disclosure;

[0012] Figure 2B is Figure 2A a side view of the capacitor in

[0013] Figure 3 shows an embedded capacitor assembly including a capacitor embedded in a circuit board substrate according to aspects of the present disclosure;

[0014] Figure 4A is a circuit diagram of a capacitor according to aspects of the present disclosure;

[0015] Figure 4B is a circuit diagram of a high electron mobility transistor including multiple capacitors according to aspects of the present disclosure; and

[0016] Figure 5 is a flowchart of a method for forming a capacitor according to aspects of the present disclosure.

[0017] The repeated use of reference numerals in this specification and the drawings is intended to represent the same or similar features or elements of the invention. Detailed Description

[0018] Those of ordinary skill in the art will understand that this discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the invention, which are embodied in the exemplary structures.

[0019] Generally, the present invention relates to a single-layer capacitor having a resistive layer. For example, a single-layer capacitor (SLC or "capacitor" as used herein) can include: a substrate; a resistive layer formed on at least a portion of a first surface of the substrate; a first conductive layer formed on at least a portion of the resistive layer; and a second conductive layer formed on at least a portion of a second surface of the substrate, the second surface of the substrate being opposite the first surface of the substrate.

[0020] The effective circuit formed by a capacitor having a resistive layer is a resistor in series with the capacitor, which can make the capacitor having the resistive layer a capacitor with a higher equivalent series resistance (ESR). The increased ESR can reduce the Q factor or quality factor of the capacitor and broaden the frequency response of the capacitor. The broadened frequency response of the SLC can improve the performance of the bias line in an active RF device, for example, by providing a filtered voltage to the active radiofrequency (RF) device. It will be appreciated that the quality factor or Q factor is the reactance of the capacitor divided by the ESR of the capacitor.

[0021] Additionally or alternatively, the frequency response broadened due to the increased ESR can enhance the performance of the SLC in RF shunt applications and noise filtering applications. For example, a bias bank of an RF active device utilizing one or more SLCs as described herein can have, for example, a reduced number of components compared to a bias bank that does not utilize an SLC having a resistive layer as described herein. Reducing the number of components in the bias bank can improve the reliability of the bias bank, reduce the size of the bias bank, and improve the performance of the active devices in the bias bank. Other applications can include voltage controlled oscillators (VCOs), mixers, and cascaded amplifier voltage sources.

[0022] Furthermore, reducing the Q factor of the capacitor can increase the frequency range of the capacitor and its usefulness in broadband applications. Reducing the Q factor also facilitates the miniaturization of the capacitor.

[0023] As stated, a single-layer capacitor can include a substrate and a resistive layer formed on the substrate. In some embodiments, the substrate can be formed of a material having a dielectric constant (K) that is determined to be less than about 30 according to ASTM D2520-13 at an operating temperature of 25 °C and a frequency of 500 megahertz (MHz), less than about 25 in some embodiments, less than about 20 in some embodiments, and less than about 15 in some embodiments. However, in other embodiments, materials having a dielectric constant higher than 30 can be used to achieve higher frequencies and / or smaller components. For example, in such embodiments, the dielectric constant determined according to ASTM D2520-13 at an operating temperature of 25 °C and a frequency of 500 MHz can be in the range of about 30 to about 120 (or greater), in the range of about 50 to about 100 in some embodiments, and in the range of about 70 to about 90 in some embodiments.

[0024] In still other embodiments, the substrate can be formed of a material having a relatively high dielectric constant (K), such as from about 10 to about 40000, from about 50 to about 30000 in some embodiments, and from about 100 to about 20000 in some embodiments.

[0025] The substrate may include one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may include sapphire, ruby, alumina (Al 2 O 3 ), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al 2 O 3 ), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO 2 ), silicon nitride (Si 3 N 4 ), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO 2 ), mixtures thereof, oxides and / or nitrides of such materials, or any other suitable ceramic materials. Additional example ceramic materials include barium titanate (BaTiO 3 ), calcium titanate (CaTiO 3 ), zinc oxide (ZnO), ceramics containing low-fire glass, or other glass-bonded materials.

[0026] Specific examples of such high dielectric materials include, for example, NPO (COG) materials (up to about 100), X7R materials (from about 3000 to about 7000), X7S materials, Z5U materials, and / or Y5V materials. It should be recognized that the above materials are described by their industry-recognized definitions, and some of these materials are standard classifications established by the Electronic Industries Alliance (EIA), and thus should be recognized by those of ordinary skill in the art. For example, such materials may include ceramics. These materials may include perovskites such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, strontium barium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), and sodium bismuth titanate, etc. In a particular embodiment, for example, the formula Ba xSr 1-x TiO 3 Barium strontium titanate (“BSTO”), where x ranges from 0 to 1, and in some embodiments x ranges from about 0.15 to about 0.65, and in some embodiments x ranges from about 0.25 to about 0.6. Other suitable perovskites can include, for example: Ba x Ca 1-x TiO 3 (where x ranges from about 0.2 to about 0.8, and in some embodiments x ranges from about 0.4 to about 0.6), Pb x Zr 1-x TiO 3 (“PZT”) (where x ranges from about 0.05 to about 0.4), lead lanthanum zirconium titanate (“PLZT”), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), potassium niobate (KNbO 3 ), lithium niobate (LiNbO 3 ), lithium tantalate (LiTaO 3 ), lead metaniobate (PbNb 2 O 6 ), lead tantalate (PbTa 2 O 6 ), KSr(NbO 3 ) and NaBa 2 (NbO 3 ) 5 KHb 2 PO 4 . There are additional complex perovskites that can include A[B1 1 / 3 B2 2 / 3 O 3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1); B1 is Mg y Zn 1-y (y can be a value from 0 to 1); B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In a particular embodiment, the dielectric material can include titanates.

[0027] As used herein, a layer "formed on" an object can include a layer formed directly on the object and a layer formed on one or more intermediate layers between the layer and the object. Further, forming "on" a bottom surface means outward from the center of the component.

[0028] The resistive layer of the capacitor can be formed on at least a portion of the surface of the substrate. In some embodiments, the resistive layer can be a thin film resistor. The thin film resistor can be configured to exhibit various resistance values as needed. For example, in some embodiments, the thin film resistor can have a resistance in the range of from about 1 ohm (Ω) to about 2000 Ω, in some embodiments in the range of from about 2 Ω to about 1000 Ω, in some embodiments in the range of from about 5 Ω to about 750 Ω, in some embodiments in the range of from about 10 Ω to about 500 Ω, and in some embodiments in the range of from about 25 Ω to about 400 Ω.

[0029] As further described herein, various thin film techniques can be used to form the resistive layer of the thin film resistor. The resistive layer of the thin film resistor can be formed of various suitable resistive materials. For example, the resistive layer can include tantalum nitride (TaN), silicon chromium (SiCr), nickel chromium (NiCr), tantalum aluminide, chromium silicon, titanium nitride, titanium tungsten, tantalum tungsten, oxides and / or nitrides of such materials, and / or any other suitable thin film resistive material.

[0030] The first conductive layer of the capacitor can be formed on at least a portion of the resistive layer. The first conductive layer can be contained within the outer edge of the resistive layer. The first conductive layer can not be in direct contact with and / or directly electrically connected to the substrate.

[0031] The capacitor can further include an additional conductive layer or a second conductive layer. The second conductive layer can be formed on the surface of the substrate opposite the resistive layer. For example, the substrate can have a first surface and a second surface opposite the first surface, and the resistive layer can be formed on the first surface and the second conductive layer can be formed on the second surface.

[0032] The conductive layer can be formed of any one of a variety of different metals known in the art. The electrode layer can be made of a metal such as a conductive metal. The materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloy, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. The electrode can also be made of a low-resistance material such as silver, copper, gold, aluminum, palladium, etc. In a particular embodiment, the electrode layer can include nickel or an alloy thereof.

[0033] The capacitor can include a pair of terminals, referred to as the first terminal and the second terminal, respectively. The first terminal can be connected to the first conductive layer, or the first terminal can be connected to the first surface of the substrate. The second terminal can be connected to the second surface of the substrate (opposite to the surface on which the resistance layer is formed), or the second terminal can be connected to the second conductive layer. As used herein, "connected to" can refer to components in direct physical contact. "Connected to" can also refer to such items: these items are physically connected through one or more intermediate conductive layers such that these items are directly electrically connected (e.g., there is no resistance layer or dielectric layer between them). For example, as described herein, the first terminal can be formed on the first conductive layer, and the second terminal can be formed on the second surface of the substrate, with or without a second conductive layer between the second terminal and the second surface.

[0034] In some embodiments, the first conductive layer and / or the second conductive layer can be one of the pair of terminals. That is, instead of attaching a separate first terminal to the first conductive layer and / or a separate second terminal to the second conductive layer, the first conductive layer can form the first terminal and / or the second conductive layer can form the second terminal.

[0035] Thus, in some embodiments, the first terminal can include a conductive material that directly contacts the first surface of the substrate, and in other embodiments, the first terminal can include a conductive material that directly contacts the first conductive layer formed on the first surface of the substrate. Similarly, in some embodiments, the second terminal can include a conductive material that directly contacts the second surface of the substrate, and in other embodiments, the second terminal can include a conductive material that directly contacts the second conductive layer formed on the second surface of the substrate.

[0036] One or more protective layers may be formed on the substrate. For example, one or more protective layers may be formed on the first surface and / or the second surface of the substrate. In some embodiments, the first terminal and / or the second terminal may be exposed through the one or more protective layers for electrical connection. Example materials for the one or more protective layers include benzocyclobutene (BCB), polyimide, silicon oxynitride, aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon nitride (Si3N4), epoxy resin, glass, or other suitable materials.

[0037] Various thin film techniques may be used to form the thin film layers of the capacitor. For example, one or more of the first conductive layer, the second conductive layer, the resistive layer, and the terminals may be the thin film layers of the capacitor. Examples of such techniques that may be employed include chemical deposition (e.g., chemical vapor deposition), plasma enhanced chemical vapor deposition (PECVD) processing, physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin film elements. Additional examples include any suitable patterning technique (e.g., lithography), etching, and any other suitable thinning technique for forming thin film elements.

[0038] The thin film layers may have a range of thicknesses. For example, the thin film layers may have a thickness that, in some embodiments, may range from about 0.001 micrometer (or micron) to about 100 micrometers, in some embodiments from about 0.0375 micrometers to about 40 micrometers, in some embodiments from about 0.1 micrometers to about 30 micrometers, in some embodiments from about 0.2 micrometers to about 20 micrometers, and in some embodiments from about 0.4 micrometers to about 10 micrometers. For example, in some embodiments, the resistive layer may have a thickness that is less than about 10 micrometers, in some embodiments less than about 8 micrometers, in some embodiments less than about 6 micrometers, and in some embodiments less than about 4 micrometers.

[0039] In some embodiments, the conductive layer formed on the resistive layer may be relatively small compared to the resistive layer, and this conductive layer defines the capacitive area. By providing a relatively small conductive layer, only a relatively small area is available for current to flow through, which forces the current through the resistive layer and can increase the resistance from the edge of the resistive layer to the relatively small conductive layer.

[0040] The relative size of the conductive layer compared to the resistive layer can be defined by the ratio of the area of the resistive layer to the area of the conductive layer. The area of the resistive layer can be defined by the length of the resistive layer extending in the Y direction and the width of the resistive layer extending in the X direction. Similarly, the area of the conductive layer can be defined by the length of the conductive layer extending in the Y direction and the width of the conductive layer extending in the X direction. In some embodiments, the ratio of the area of the resistive layer to the area of the conductive layer can be in the range of about 100:1, in some embodiments in the range of about 75:1, in some embodiments in the range of about 50:1, in some embodiments in the range of about 25:1, in some embodiments in the range of about 15:1, in some embodiments in the range of about 10:1, in some embodiments in the range of about 5:1, in some embodiments in the range of about 3:1, and in some embodiments in the range of about 1.5:1.

[0041] In some aspects of the present subject matter, the capacitor can be configured to be embedded within a circuit board substrate (e.g., a printed circuit board). For example, the first terminal and the second terminal can be exposed along opposite surfaces of the substrate (e.g., the top surface and the bottom surface of the substrate), and can be included within the outer edge of the respective surface of the substrate.

[0042] The present subject matter also relates to an embedded capacitor assembly that includes a circuit board substrate (e.g., a printed circuit board) having a capacitor at least partially embedded therein. The circuit board substrate can be formed of any suitable material, such as FR4 or polytetrafluoroethylene, etc. One or more electronic components can be mounted to the circuit board substrate, such as capacitors, resistors, transistors, switches, and / or other electronic components. As used herein, "mounted to" the circuit board can include any type of connection to the circuit board substrate that provides an electrical connection, such as surface mounting to the surface of the circuit board substrate or embedding within the circuit board substrate, etc.

[0043] The circuit board substrate can have a recessed opening in the mounting surface (e.g., the upper surface or the lower surface) of the circuit board substrate. The recessed opening can be configured to receive an electronic component to be embedded within the circuit board substrate. For example, a capacitor (e.g., the capacitor described herein) can be inserted into the recessed opening to be embedded within the circuit board substrate. One or more conductive terminations of the capacitor can be coupled to the circuit board substrate. For example, one or more vias can be formed in, on, or through the termination to electrically connect the capacitor to one or more conductive traces of the circuit board substrate and / or one or more electronic components mounted to the circuit board substrate.

[0044] The first and second terminals of the capacitor can be formed of copper, for example, by copper plating. Generally, solid copper may not be a suitable material for forming the exposed terminations of electronic components because copper is prone to oxidation when exposed. Therefore, soldering materials such as alloys of copper, tin, and gold are often used to form the electrical terminations of electronic components such as capacitors. However, the inventors have found that forming the first and second terminals of the embeddable capacitor with copper, for example, by plating solid copper on the conductive layer and / or on one or more surfaces of the substrate, can provide better electrical connections without the risk of oxidation when embedding the capacitor into the circuit board substrate. For example, laser drilling can be performed on the first and second terminals to form direct electrical connections with the circuit board substrate and / or additional electronic components mounted to the circuit board substrate.

[0045] Figure 1A is a side view of a single-layer capacitor 100 according to aspects of the present disclosure. The single-layer capacitor 100 may also be referred to herein as the SLC 100 or the capacitor 100. Figure 1B and Figure 1C is a side view of the capacitor 100 according to other aspects of the present disclosure.

[0046] As Figure 1A 、 Figure 1B and Figure 1C shown, the capacitor 100 may include a substrate 102 having a first surface 104 and a second surface 106 opposite the first surface 104. The substrate 102 may be formed of a dielectric material. In some embodiments, the dielectric material may have a relatively low dielectric constant (K), but in other embodiments, the dielectric material may have a relatively high dielectric constant.

[0047] The capacitor 100 may include a resistive layer 108 formed on at least a portion of the first surface 104 of the substrate 102. In some embodiments, the resistive layer 108 may have a thickness of less than about 10 microns. In some embodiments, the resistive layer 108 may be formed of tantalum nitride (TaN), and in other embodiments, the resistive layer 108 may be formed of chromium silicon (CrSi). As described elsewhere herein, the resistive layer 108 may have other thicknesses and / or be formed of other materials.

[0048] The capacitor 100 may further include a first conductive layer 110 formed on at least a portion of the resistive layer 108. The first conductive layer 110 may be included within the outer edge of the resistive layer 108. The first conductive layer 110 may not be in direct contact and / or direct electrical connection with the substrate 102.

[0049] The capacitor 100 may further include a second conductive layer 112 formed on the second surface 106 of the substrate 102. As Figure 1A , Figure 1B and Figure 1C shown, the second conductive layer 112 may extend over the entire second surface 106. Alternatively, similar to the resistive layer 108 and the first conductive layer 110 formed on the first surface 104 of the substrate 102, for example, the second conductive layer 112 may be offset from one or more edges of the substrate 102 such that the second conductive layer 112 extends over a portion of the second surface 106.

[0050] A pair of terminals 114, 116 may be connected to the capacitor. Each terminal of the pair of terminals may include a conductive material such as gold, copper, another suitable metal, or other conductive material. In some embodiments, at least one of the first conductive layer 110 or the second conductive layer 112 is one of the pair of terminals. For example, as Figure 1C shown, the first conductive layer 110 and the second conductive layer 112 may each form one of the pair of terminals.

[0051] In other embodiments, only one of the first conductive layer 110 or the second conductive layer 112 may form one of the pair of terminals, and in still other embodiments, neither the first conductive layer 110 nor the second conductive layer 112 may form a terminal of the pair of terminals. For example, as Figure 1A and Figure 1B shown, the first terminal 114 of the pair of terminals may be connected to the first conductive layer 110.

[0052] In addition, the substrate 102 may include a pair of end surfaces 120, 122, and the first terminal 114 may be located closer to one of the pair of end surfaces 120, 122, i.e., the second end surface 122, than to the other end surface 120 of the pair of end surfaces 120, 122. For example, the substrate may include a first end surface 120 and a second end surface 122, which are opposite to each other along the Y direction and perpendicular to the first surface 104 and the second surface 106 of the substrate 102. As Figure 1A and Figure 1B shown, the first terminal 114 may be disposed closer to the second end surface 122 than to the first end surface 120. In other embodiments, the first terminal 114 may be disposed closer to the first end surface 120 than to the second end surface 122. In other embodiments, the first terminal 114 may be disposed equidistant from the first end surface 120 and the second end surface 122 along the Y direction.

[0053] The second terminal 116 of the pair of terminals may be connected to the substrate 102 or the second conductive layer 112. For example, the capacitor 100 may include the second terminal 116 on the second surface 106 of the substrate 102. As Figure 1A shown, the second terminal 116 may be formed by the second conductive layer 112 formed on the second surface 106 of the substrate 102, and the second surface is opposite to the first surface 104 in the Z direction. That is, the second conductive layer 112 may be the second terminal 116. Refer to Figure 1B , in other embodiments, the second terminal 116 may be formed on the second conductive layer 112 such that the second conductive layer 112 is disposed between the second terminal 116 and the substrate 102. As Figure 1B shown, the second terminal 116 may be aligned with the first terminal 114 in the Z direction, or the second terminal 116 may be offset from the first terminal 114 in the Z direction. For example, the second terminal 116 may be formed closer to the first end surface 120 than to the second end surface 122.

[0054] In other embodiments, each of the second conductive layer 112 and the second terminal 116 may be formed on the second surface 106 of the substrate 102 without forming the second terminal 116 on the second conductive layer 112. For example, the second conductive layer 112 may be formed on a part of the second surface 106, and the second terminal 116 may be formed on another different part of the second surface 106.

[0055] In any case, for the capacitor 100, whether the pair of terminals 114, 116 are formed separately from the first conductive layer 110 and the second conductive layer 112 or are formed by the first conductive layer 110 and / or the second conductive layer 112, the pair of terminals are connected to the respective layers of the capacitor 100 or the substrate 102 such that the capacitor 100 includes a resistor and a capacitor formed in series with each other.

[0056] Now turning to Figure 2A and Figure 2B , a top view and a side view of a capacitor 200 according to aspects of the present disclosure are provided respectively. In Figure 2A and Figure 2B the same reference numerals as in Figure 1A , Figure 1B and Figure 1C are used. For example, the capacitor 200 includes a substrate 202 having a resistive layer 208 formed on at least a part of the first surface 204 of the substrate 202. A first conductive layer 210 is formed on at least a part of the resistive layer 208. A second conductive layer 212 is formed on at least a part of the second surface 206 of the substrate 202, where the second surface 206 is opposite to the first surface 204.

[0057] In Figure 2Aand Figure 2B In the embodiment of, the first surface 204 is the top surface of the capacitor 200, thus Figure 2A the first surface 204 is shown. As described with reference to capacitor 100, the first conductive layer 210 may be included within the outer edge 209 of the resistive layer 208. In Figure 2A the embodiment shown, the first conductive layer 210, which forms the first terminal 214 in some embodiments, is relatively small compared to the resistive layer 208, and this first conductive layer defines the capacitive area. By providing a relatively small first conductive layer 210, only a relatively small area is available for current to flow through, which forces the current to pass through the resistive layer 208.

[0058] The relative size of the first conductive layer 210 compared to the resistive layer 208 can be defined by the ratio of the area of the resistive layer 208 to the area of the first conductive layer 210. The area of the resistive layer 208 can be defined by the length L R of the resistive layer 208 and the width W R of the resistive layer 208, where the length extends in the Y direction between the first end edge 224 and the second end edge 226 of the substrate 202, and the width extends in the X direction between the first side edge 228 and the second side edge 230 of the substrate 202. Similarly, the area of the first conductive layer 210 can be defined by the length L C1 that extends in the Y direction of the first conductive layer 210 and the width W C1 that extends in the X direction of the first conductive layer 210. In some embodiments, the ratio of the area of the resistive layer 208 to the area of the first conductive layer 210 can be in the range of about 100:1, in some embodiments in the range of about 75:1, in some embodiments in the range of about 50:1, in some embodiments in the range of about 25:1, in some embodiments in the range of about 15:1, in some embodiments in the range of about 10:1, in some embodiments in the range of about 5:1, in some embodiments in the range of about 3:1, and in some embodiments in the range of about 1.5:1.

[0059] Figure 3Shows an embedded capacitor assembly 350 including a capacitor 100 embedded in a circuit board substrate 352 according to aspects of the present disclosure. The circuit board substrate 352 can be, for example, a printed circuit board and can be formed of any suitable material, such as FR4 or polytetrafluoroethylene, etc. The circuit board substrate 352 includes a mounting surface 354. The capacitors 100, 200 can be at least partially embedded within the circuit board substrate 352 of the assembly 350. For example, the mounting surface 354 can have an opening 355 that is recessed into the circuit board substrate 352. To minimize its height profile on the board, known techniques can be used to embed the capacitor 100 into the opening 355 and attach it to the circuit board substrate 352. For example, as further described herein, using known techniques, one or more vias can connect one or more terminals of the capacitor 100 to one or more conductive traces of the circuit board substrate 352.

[0060] The degree of embedding of the capacitor 100 depends on various factors, such as the thickness of the circuit board substrate 352, the depth of the opening 355, the thickness of the capacitor 100, etc. The thickness of the circuit board substrate 352 (excluding the attached electronic components) can be from about 0.1 mm to about 5 mm in some embodiments, from about 0.2 mm to about 3 mm in some embodiments, and from about 0.4 mm to about 1.5 mm in some embodiments. Thus, depending on the particular thickness employed, the capacitor 100 can be embedded such that the exposed surface of the first terminal 114 is generally coplanar with or below the mounting surface 354 of the circuit board substrate 352. For example, the capacitor 100 can be embedded and enclosed within the opening 355 of the circuit board substrate 352. Alternatively, the capacitor 100 can be embedded such that the exposed surface of the first terminal 114 slightly extends above the mounting surface 354 of the circuit board substrate 352. In any case, by embedding the capacitor 100 at least partially within the circuit board substrate 352, the height profile or thickness occupied by the capacitor 100 is reduced and can be controlled according to the desired application.

[0061] It should be understood that, as is well known in the art, various other electronic components can also be mounted on the circuit board substrate 352, and the single capacitor 100 is shown for illustrative purposes only. Additionally, Figure 3 the capacitor 100 shown can generally be configured to be similar to Figures 1A to 1C the capacitor 100 in Figure 2A and Figure 2B the capacitor 200 in

[0062] Refer to Figure 3, a first terminal 114 and a second terminal 116 are formed on opposite surfaces of a substrate 102 of the illustrated capacitor 100. For example, the first terminal 114 is formed on a first surface 104, which may be the upper surface of the substrate 102, while the second terminal 116 is formed on a second surface 106, which may be the lower surface of the substrate 102. As Figure 3 shown, a via 356 can extend from the first terminal 114 of the capacitor 100 toward the mounting surface 354 and be connected to a conductive layer 358 formed on the mounting surface 354. The via 356 of the embedded capacitor assembly 350 can electrically connect the first terminal 114 to the first conductive layer 358, which can be, for example, a conductive trace of the circuit board substrate 352. Alternatively, the via 356 can extend toward the mounting surface 354 and be connected to one or more intermediate layers (e.g., embedded within the circuit board substrate 352), which can in turn be electrically connected to the conductive layer 358. The via 356 can form at least a part of the electrical connection between the first terminal 114 of the capacitor 100 and the conductive layer 358 of the embedded capacitor assembly 350. However, it should be understood that in other embodiments, the terminal 114 can be exposed along the mounting surface 354. In such an embodiment, the embedded capacitor assembly 350 can be without the via 356.

[0063] In some embodiments, the circuit board substrate 352 can include a plurality of conductive layers 358, e.g., a plurality of conductive traces, and the capacitor 100 can include a plurality of terminals 114 exposed along the first surface 104. A plurality of vias 356 can extend from these terminals to the conductive layers of the circuit board substrate 352, e.g., at least one via can extend from a respective one of the terminals 114 of the capacitor 100 to a respective one of the conductive layers 358 of the circuit board substrate 352.

[0064] Turning to Figure 4A and Figure 4B , circuit diagrams depicting the capacitors 100, 200 described herein are provided. As Figure 4A shown, each of the capacitors 100, 200 includes a resistor R and a capacitor C arranged in series with each other. Referring Figure 4B to Figures 1A to 2B to, one or more of the exemplary capacitors 100, 200 described can be used in various electrical systems or devices. For example, Figure 4B an exemplary high electron mobility transistor (HEMT) according to aspects of the present subject matter is shown. In Figure 4BOn the left side of the circuit diagram shown, multiple capacitors described herein (denoted as R6 / C18, R5 / C10, and R14 / C32) are arranged in the negative bias group, while on the right side, multiple capacitors described herein (denoted as R15 / C33, R3 / C8, and R4 / C17) are arranged in the Vdd bias group. Figure 4B The HEMT shown in is only an example; it will be recognized that the capacitors 100, 200 described herein can be used in various applications.

[0065] Now referring to Figure 5 , aspects of the present subject matter relate to a method 500 for forming capacitors such as those described herein. Generally, the method 500 will be described herein with reference to the capacitor 100 in Figure 1A , Figure 1B and Figure 1C . However, it should be recognized that the disclosed method 500 can be implemented with any suitable capacitor. Additionally, although Figure 5 the steps are depicted for purposes of illustration and discussion as being performed in a particular order, the methods described herein are not limited to any particular order or arrangement. Those skilled in the art will recognize, using the disclosures provided herein, that the various steps of the methods disclosed herein can be omitted, rearranged, combined, and / or adjusted in various ways without departing from the scope of the present subject matter.

[0066] The method 500 may include (502) depositing a resistive layer 108 on at least a portion of a first surface 104 of a substrate 102 of the capacitor 100. The resistive layer 108 may have a thickness of less than about 10 micrometers. The resistive layer 108 may be formed of tantalum nitride, chromium silicon, or other suitable resistive materials such as those described herein.

[0067] The method 500 may include (504) depositing a first conductive layer 110 on at least a portion of the resistive layer 108. The first conductive layer 110 may be included within an outer edge 110 of the resistive layer 108. The first conductive layer 110 may not be in direct contact and / or direct electrical connection with the substrate 102.

[0068] The method 500 may include (506) depositing a second conductive layer 112 on at least a portion of a second surface 106 of the substrate 102. The second surface 106 of the substrate 102 may be opposite the first surface 104 of the substrate 102.

[0069] Method 500 may optionally include (508) depositing a first terminal 114 on the first conductive layer 110. For example, as described herein, a separate first terminal 114 may be deposited on the first conductive layer 110, or the first conductive layer 110 may form the first terminal 114. The method may optionally include (510) depositing a second terminal 116 such that at least the substrate 102 and the resistive layer 108 are disposed between the first conductive layer 110 and the second terminal 116. For example, as described herein, in some embodiments, the second conductive layer 112 may form the second terminal 116. In other embodiments, the second terminal 116 may be deposited on the second conductive layer 112 such that the substrate 102, the resistive layer 108, and the second conductive layer 112 are disposed between the first conductive layer 110 and the second terminal 116. In any case, the pair of terminals 114, 116 are connected to the respective layers or the substrate of the capacitor 100 such that a resistor and a capacitor are formed in series with each other.

[0070] Application

[0071] The capacitors described herein are useful in a variety of applications. For example, the single-layer capacitors described herein may be particularly useful in front-end preamplifiers, HEMT V-gs, Vdd, hybrid-packaged components, and filtering internal-packaged semiconductors. Additionally, the capacitor may be useful in devices that process broadband radio frequency signals because the capacitor exhibits excellent performance at high frequencies (e.g., frequencies of 20 GHz or higher). Example devices include mobile devices (e.g., cell phones, tablets, etc.), cell phone signal towers, Receiver Optical Sub Assemblies (ROSA), Transmission Optical Sub Assemblies (TOSA), and other radio frequency (RF) communication devices. Such RF devices may be particularly useful in military and space applications.

[0072] Those of ordinary skill in the art may practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. Additionally, it should be understood that aspects of the various embodiments may be interchanged in whole or in part. Furthermore, those of ordinary skill in the art will recognize that the foregoing description is by way of example only and is not intended to limit the present invention as further described in the appended claims.

Claims

1. A single-layer capacitor, comprising: a substrate having a first surface and a second surface opposite to the first surface; a resistive layer formed on at least a portion of the first surface of the substrate; a first conductive layer formed on at least a portion of the resistive layer; and a second conductive layer formed on at least a portion of the second surface of the substrate.

2. The single-layer capacitor according to claim 1, further comprising: a first terminal connected to the first conductive layer; and a second terminal connected to the second conductive layer.

3. The single-layer capacitor according to claim 1, wherein the resistive layer has a thickness of less than about 10 micrometers.

4. The single-layer capacitor according to claim 1, wherein the resistive layer is formed of tantalum nitride.

5. The single-layer capacitor according to claim 1, wherein the resistive layer is formed of chromium silicon.

6. The single-layer capacitor according to claim 1, further comprising: a first terminal connected to the first conductive layer; and a second terminal connected to the first surface of the substrate.

7. The single-layer capacitor according to claim 1, wherein the ratio of the area of the resistive layer to the area of the first conductive layer is at least about 1.5:

1.

8. The single-layer capacitor according to claim 1, wherein the ratio of the area of the resistive layer to the area of the first conductive layer is at least about 10:

1.

9. The single-layer capacitor according to claim 1, wherein the ratio of the area of the resistive layer to the area of the first conductive layer is at least about 20:

1.

10. A method for forming a single-layer capacitor, the method comprising: depositing a resistive layer on at least a portion of a first surface of a substrate; depositing a first conductive layer on at least a portion of the resistive layer; and depositing a second conductive layer on at least a portion of a second surface of the substrate, the second surface being opposite to the first surface.

11. The method according to claim 10, further comprising: depositing a first terminal such that the first terminal is connected to the first conductive layer; and depositing a second terminal such that the second terminal is connected to the second conductive layer.

12. The method according to claim 10, further comprising: depositing a first terminal such that the first terminal is connected to the first conductive layer; and depositing a second terminal such that the second terminal is connected to the substrate.

13. An embedded capacitor assembly, comprising: a circuit board substrate having a mounting surface; and a single-layer capacitor at least partially embedded within the circuit board substrate, the single-layer capacitor comprising: a substrate having a first surface opposite to a second surface, a resistive layer formed on at least a portion of the first surface; a first conductive layer formed on at least a portion of the resistive layer; and a second conductive layer formed on at least a portion of the second surface.

14. The embedded capacitor component according to claim 13, wherein the single-layer capacitor further includes a first terminal, and the first terminal is connected to the first conductive layer.

15. The embedded capacitor component according to claim 13, further comprising at least one via, the at least one via being connected to the first terminal and extending towards the mounting surface of the circuit board substrate.

16. The embedded capacitor component according to claim 15, wherein, the circuit board substrate further includes a conductive layer, and wherein the at least one via is connected to the conductive layer of the circuit board substrate.

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