Chip testing device and system
By introducing a signal path switching module into the chip test system, rapid testing of different types of chips is achieved, and the problem of time-consuming and low efficiency of chip testing in the existing technology is solved, and the testing efficiency and flexibility are improved.
Patent Information
- Application Number
- CN202510312034.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-05-30
AI Technical Summary
The existing chip testing technology takes a long time and has low testing efficiency. Especially when selecting a chip from multiple chips, chip co-use testing is required for different types of chips.
It provides a chip testing device and system, including a main control module and a signal path switching module, through the signal path switching module, conducts the download channel between the terminal and the chip under test, downloads the test program, and conducts the test operation by conducting the test channel between the measured chip under test and the main control module or the test equipment.
It realizes rapid testing of different types of chips, improves testing efficiency, reduces testing time, and is suitable for rapid screening and testing of multiple types of chips.
Smart Images
Figure CN120064943A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of chip testing, and particularly to a chip testing device and system. Background Art
[0002] With the rapid development of chips, the demand for chip replacement by chip users has also increased. Before chip replacement, chip users need to conduct chip compatibility tests. The test process includes principle design, PCB (Printed Circuit Board) design, board making and trial production, and debugging to screen out chips that meet specific working conditions. If one chip is selected from multiple chips, chip compatibility tests need to be carried out separately for different types of chips. This process takes a long time and the chip testing efficiency is low. Summary of the Invention
[0003] In view of the above problems, this application provides a chip testing device and system, which can implement chip testing for different types of chips and improve the testing efficiency. The specific solutions are as follows:
[0004] In the first aspect of this application, a chip testing device is provided, including:
[0005] A main control module and a signal path switching module;
[0006] The controlled end of the signal path switching module is connected to the main control module, and the output end of the signal path switching module is connected to multiple pins of the chip under test;
[0007] The main control module is used to control the signal path switching module to conduct the channel connecting the terminal to the download pin of the chip under test, so that the terminal downloads the test program to the chip under test;
[0008] The main control module is further used to control the signal path switching module to conduct the channel connecting the main control module to the pins to be tested of the chip under test, and / or control the signal path switching module to conduct the channel connecting the pins to be tested of the chip under test to the test equipment, so that the chip under test runs the test program to perform test operations.
[0009] In a possible implementation, the signal path switching module includes:
[0010] A first switch array; the number of the first switch arrays is one or more;
[0011] If the number of the first switch arrays is one, the controlled end of the first switch array is connected to the main control module, and the output end of the first switch array is connected to multiple pins of the chip under test;
[0012] If the number of the first switch arrays is multiple, two adjacent first switch arrays are connected through a bus, and the chip under test is connected to the test device through the multiple first switch arrays.
[0013] In a possible implementation, the signal path switching module further includes:
[0014] A selection switch;
[0015] One input end of the selection switch is connected to the main control module, and multiple output ends of the selection switch are respectively and correspondingly connected to multiple input ends of the first switch array.
[0016] In a possible implementation, it further includes:
[0017] A power supply control module;
[0018] The controlled end of the power supply control module is connected to the main control module, and the output end of the power supply control module is connected to the power supply pin of the chip under test;
[0019] The main control module is used to control the power supply control module to turn on the power supply channel of the chip under test, so that the power supply device connected to the power supply control module outputs the voltage required by the chip under test to the chip under test.
[0020] In a possible implementation, the power supply control module includes:
[0021] A second switch array;
[0022] The input end of the second switch array is connected to the main control module, the power supply end of the second switch array is connected to the power supply device, and the output end of the second switch array is connected to the power supply pin of the chip under test.
[0023] In a possible implementation, the power supply control module further includes:
[0024] A control unit;
[0025] The input end of the control unit is connected to the main control module, and the output end of the control unit is connected to the second switch array.
[0026] In a possible implementation,
[0027] The main control module is further used to control the signal path switching module to turn on the channel for connecting the clock pin of the chip under test to the clock device, so that the clock device provides a clock signal to the chip under test;
[0028] And / or,
[0029] The main control module is further configured to control the signal path switching module to turn on the connection channel between the chip under test and the peripheral components, so as to perform at least one of the reset and mode selection operations of the chip under test.
[0030] The second aspect of the present application provides a chip testing system, including:
[0031] A chip under test, a terminal, and the chip testing device as described above;
[0032] The terminal is connected to the main control module of the chip testing device;
[0033] The chip under test is connected to the signal path switching module of the chip testing device;
[0034] The terminal is configured to transmit the test task of the chip under test to the main control module;
[0035] The main control module is configured to, after controlling the signal path switching module to turn on the channel connecting the terminal to the download pin of the chip under test, enable the terminal to download the test program to the chip under test, and then control the signal path switching module to turn on the test channel, and control the chip under test to run the test program for testing operations based on the test task; wherein, the test channel is the channel connecting the main control module to the pins to be tested of the chip under test, and / or the channel connecting the pins to be tested of the chip under test to the test equipment.
[0036] In a possible implementation, it further includes:
[0037] A power supply device;
[0038] The power supply device is connected to the main control module;
[0039] The main control module is configured to control the power supply device to output the voltage required by the chip under test.
[0040] In a possible implementation, it further includes:
[0041] A carrier board for the chip under test;
[0042] The carrier board for the chip under test includes a base and an interface;
[0043] The chip under test is installed on the base, and the chip under test is connected to the main control module through the interface.
[0044] With the above technical solutions, for the chip testing device and system provided by the present application, the signal path switching module is respectively connected to the main control module and the chip under test. Through the signal path switching module, the download channel between the terminal and the chip under test can be conducted, enabling the terminal to download the test program into the chip under test. Through the signal path switching module, the test channel between the chip under test and the main control module or the test channel between the chip under test and the test equipment can be conducted, thereby realizing the test operation of the chip under test. The present application can perform different channel switching through the signal path switching module to adapt to the test operations of different types of chips, improving the test efficiency. Description of the Drawings
[0045] In combination with the accompanying drawings and with reference to the following specific embodiments, the above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic and that the original and elements are not necessarily drawn to scale.
[0046] Figure 1 Structural diagram of a chip testing device provided by the present application;
[0047] Figure 2 Another structural diagram of a chip testing device provided by the present application;
[0048] Figure 3 Another structural diagram of a chip testing device provided by the present application;
[0049] Figure 4 Another structural diagram of a chip testing device provided by the present application;
[0050] Figure 5 Another structural diagram of a chip testing device provided by the present application;
[0051] Figure 6 Another structural diagram of a chip testing device provided by the present application;
[0052] Figure 7 Another structural diagram of a chip testing device provided by the present application;
[0053] Figure 8 Another structural diagram of a chip testing device provided by the present application;
[0054] Figure 9 Structural diagram of a chip testing system provided by the present application;
[0055] Figure 10 Schematic diagram of a base for a chip under test provided by the present application;
[0056] Figure 11 Schematic diagram of an adapter board for a chip under test provided by the present application;
[0057] Figure 12 A structural diagram of a chip testing system provided for this application. Specific implementation manners
[0058] The embodiments of this application will be described below in conjunction with the accompanying drawings in the embodiments of this application. The terms used in the embodiments part of this application are only used to explain the specific embodiments of this application, rather than intended to limit this application.
[0059] The embodiments of this application will be described below in conjunction with the accompanying drawings. Those of ordinary skill in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.
[0060] The terms "first", "second", etc. in the description and claims of this application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing when describing objects with the same attributes in the embodiments of this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device including a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.
[0061] The embodiments of this application provide a chip testing device. The chip testing device in the embodiments of this application will be introduced in detail below in conjunction with the accompanying drawings.
[0062] Referring to Figure 1 , Figure 1 A structural diagram of a chip testing device provided for the embodiments of this application. As Figure 1 shown, a chip testing device 10 provided for the embodiments of this application may include:
[0063] A main control module 1 and a signal path switching module 2.
[0064] The controlled end of the signal path switching module is connected to the main control module, and the output end of the signal path switching module is connected to multiple pins of the chip under test 3.
[0065] The main control module is used to control the signal path switching module to conduct the channel connecting the terminal 4 to the download pin of the chip under test, so that the chip under test runs a test program to perform a test operation.
[0066] The main control module is also used to control the signal path switching module to turn on the channel connecting the main control module and the pin under test of the chip under test, and / or control the signal path switching module to turn on the channel connecting the pin under test of the chip under test and the test device 5, so as to perform the test operation on the chip under test.
[0067] The main control module can be a main control chip. The input end of the signal path switching module is connected to the main control chip, and the output end of the signal path switching module is connected to the chip under test. The output end of the signal path switching module is connected to multiple pins of the chip under test through multiple wires. The chip under test can be a chip under test MCU (Microcontroller Unit).
[0068] The signal path switching module can include multiple switches. Each switch is connected to a pin of the chip under test and the main control chip. The main control chip can control one of the multiple switches in the signal path switching module to open and the other switches to close. The pin of the chip under test connected to the opened switch is connected to the main control chip, that is, the channel connecting the main control chip and a certain pin of the chip under test is turned on.
[0069] Before testing the chip under test, the test program can be downloaded to the chip under test. At this time, the main control chip can control the signal path switching module to turn on the switch connected to the download pin of the chip under test, so that the channel connecting the terminal and the download pin of the chip under test can be turned on, and thus the terminal can download the test program to the chip under test. Optionally, the terminal can be a host computer, and the host computer can be an industrial control computer or a computer, and can run an operating system such as Windows 7 and above.
[0070] Of course, before testing the chip under test, the main control chip can also control the signal path switching module to turn on the switch connected to the debug pin of the chip under test, so that the debug channel of the chip under test can be turned on for debugging the chip under test.
[0071] The main control chip controls the signal path switching module to provide a debug and program download channel for the chip under test. Since the debug pins of different chips are different, the main control chip can flexibly configure the download debug channel of the chip under test according to the debug port definition in the chip under test specification.
[0072] The tested chip can be tested for one or more of reset, internal high- and low-speed oscillator accuracy, TIMER (timer) accuracy, PWM (Pulse Width Modulation), GPIO (General Purpose Input / Output), UART (Universal Asynchronous Receiver / Transmitter), IIC (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface).
[0073] When testing the tested chip, the master chip can control the signal path switching module to conduct the channel connecting the master module and the pins to be tested of the tested chip. The master chip can send corresponding test instructions to the tested chip, such as SPI, UART, IIC tests, etc. After receiving the test instructions, the tested chip starts the specific test. The master chip conducts data reading and writing tests in the way of direct connection and communication with the tested chip using the same protocol. Since the functional pins of different tested chips are different, the connection between the pins to be tested of the tested chip and the corresponding functional interfaces of the master chip can be flexibly configured through the signal path switching module.
[0074] When testing the tested chip, the master chip can also control the signal path switching module to conduct the channel connecting the pins to be tested of the tested chip and the test equipment. Optionally, the test equipment includes a measurement device and a working condition test device. The measurement device can provide test conditions for the pins to be tested of the tested chip, and the working condition test device can provide working condition test conditions for the tested chip. The measurement device can be one or more of an analog-to-digital converter, a current meter, and a voltage source. Among them, the analog-to-digital converter can be an analog-digital converter or a digital-analog converter, the current meter can be a bidirectional current meter, and the voltage source can be a reference voltage source. The working condition test device can be one or more of defrost heating, a fan, and a damper. The test equipment can be flexibly set according to specific test requirements, and the present application does not make specific limitations in this regard.
[0075] The test results can be obtained through two channels. One channel is to directly obtain through the chip under test. For example, in UART testing, the test results of the chip under test are directly transmitted back to the main control chip. The other channel is to obtain through a measuring device, obtaining the VOH (Output High Voltage, the minimum voltage value when the output pin is at logic 1 (high level)), VOL (Output Low Voltage, the maximum voltage value when the output pin is at logic 0 (low level)), IOH (Input OutputHigh, the current at high input and output levels), IOL (Input Output Low, the current at low input and output levels), analog signals, digital signals, etc. of the ports of the chip under test.
[0076] In a possible implementation, the main control module is further configured to control the signal path switching module to turn on the channel connecting the clock pin of the chip under test and the clock device, so that the clock device provides a clock signal to the chip under test.
[0077] When testing the chip under test, if the chip under test requires an external clock signal, the main control chip can control the signal path switching module to turn on the channel connecting the clock pin of the chip under test and the clock device, so that the clock device provides a clock signal to the chip under test.
[0078] In a possible implementation, the main control module is further configured to control the signal path switching module to turn on the connection channel between the chip under test and the peripheral components, so as to perform at least one of the operations of resetting and mode selection of the chip under test.
[0079] When testing the chip under test, if the chip under test requires external reset and mode selection, the main control chip can control the signal path switching module to turn on the connection channel between the chip under test and the peripheral components. Optionally, the peripheral components may include capacitors and resistors.
[0080] As Figure 2 shown, it is a structural diagram of a chip testing device, and the clock device 6 and the peripheral components 7 are respectively connected to the signal path switching module 2.
[0081] In a possible implementation, the signal path switching module includes:
[0082] The first switch array; the number of the first switch arrays is one or more;
[0083] If the number of the first switch arrays is one, the controlled end of the first switch array is connected to the main control module, and the output end of the first switch array is connected to multiple pins of the chip under test;
[0084] If the number of the first switch arrays is multiple, adjacent two first switch arrays are connected through a bus, and the chip under test is connected to the test equipment through multiple first switch arrays.
[0085] The first switch array includes a plurality of switches, and the number of the first switch arrays can be one or more.
[0086] Figure 3 It is a structural diagram of a chip testing device when the number of the first switch arrays is one. Figure 4 It is a structural diagram of a chip testing device when the number of the first switch arrays is two. Figure 3 In [the figure], the input end of the first switch array 21 is connected to the main control module 1, and the output end of the first switch array 21 is connected to the chip under test 3 and the testing device 5. Figure 4 In [the figure], two first array switches 21 are connected through a bus. One first switch array 21 is connected to the chip under test 3, and the other first switch array 21 is connected to the testing device, that is, the chip under test 3 is connected to the testing device 5 through two first switch arrays 21, and both first switch arrays 21 are connected to the main control module 1. When the number of the first switch arrays is multiple, channels between the chip under test and the testing device are established in a way that multiple first switch arrays are connected through a bus, and the purpose of testing the limited pins of the chip under test with multiple different testing devices can be achieved.
[0087] Optionally, the first switch array can be an analog switch array, a relay switch array, a triode array, etc.
[0088] In a possible implementation, the signal path switching module further includes:
[0089] A selection switch;
[0090] One input end of the selection switch is connected to the main control module, and multiple output ends of the selection switch are respectively and correspondingly connected to multiple input ends of the first switch array one by one.
[0091] The selection switch can be a multiple - select - one switch, and the number of the selection switches can be the same as or less than the number of the first switch arrays. Setting the multiple - select - one switch can achieve the purpose of saving the pins of the main control chip.
[0092] Figure 5 It is a structural diagram of a chip testing device when the number of the selection switches is two. As Figure 5 shown, both two selection switches 22 are connected to the main control module 1, and each selection switch 22 is correspondingly connected to the first switch array 21 one by one.
[0093] If testing the UART interface, the main control module enables the multiple - select - one switch and the channels between the first switch array and the data receiving pin RX and the data sending pin TX of the UART interface of the chip under test through SPI respectively.
[0094] In a possible implementation, the chip testing device provided by the present application, as Figure 6 shown, the device further includes:
[0095] A power supply control module 8;
[0096] The controlled end of the power supply control module is connected to the main control module, and the output end of the power supply control module is connected to the power supply pin of the chip under test;
[0097] The main control module is used to control the power supply control module to turn on the power supply channel of the chip under test, so that the power supply device 9 connected to the power supply control module outputs the voltage required by the chip under test to the chip under test.
[0098] Since the power supply pins and power supply voltages of different chips under test are different, all or part of the pins of the chip under test can be connected to the power supply device through the power supply control module. In actual applications, according to the power supply pin regulations and power supply requirements in the specification of the chip under test, the main control module programs the power supply device so that the power supply device outputs a power supply voltage that meets the requirements and outputs the voltage required by the chip under test. The power supply device can be a programmable power supply, specifically a programmable precision power supply.
[0099] In a possible implementation, as Figure 7 shown, the power supply control module includes:
[0100] A second switch array 81;
[0101] The input end of the second switch array 81 is connected to the main control module 1, the power supply end of the second switch array 81 is connected to the power supply device 9, and the output end of the second switch array 81 is connected to the power supply pin of the chip under test 3.
[0102] The second switch array includes multiple switches, and the number of the second switch arrays can be one or multiple.
[0103] If the number of the second switch arrays is one, the second switch array is respectively connected to the main control module, the power supply device and the chip under test. If the number of the second switch arrays is multiple, then multiple second switch arrays are all connected to the main control module, the power supply device and the chip under test.
[0104] Optionally, the second switch array can be an analog switch array, a relay switch array, a triode array, etc.
[0105] In a possible implementation, as Figure 8 shown, the power supply control module further includes:
[0106] A control unit 82;
[0107] The input end of the control unit is connected to the main control module, and the output end of the control unit is connected to the second switch array.
[0108] The control unit can be an MCU.
[0109] By controlling the control unit, the main control module can control the second switch array to enable the power supply channels required by the chip under test. If the second switch array is an analog switch array, and the analog switch array can be a MOS transistor (field effect transistor) switch array, the main control module can control the control unit through the bus to control the corresponding MOS transistors to enable the power supply channels required by the chip under test.
[0110] The control unit can also be one or more. If there are multiple control units, each control unit can be connected to the second switch array in one-to-one correspondence, and the number of control units can be the same as the number of the second switch arrays.
[0111] In practical applications, if the number of pins of the chip under test is 144, four second switch arrays can be set, and correspondingly four control units can also be set. Each second switch array is connected to a control unit in one-to-one correspondence. Of course, if the number of pins of the chip under test is other values, the number of the second switch arrays and the control units can be set according to actual needs.
[0112] The embodiment of the present application provides a chip testing system. The chip testing system of the embodiment of the present application will be introduced in detail below with reference to the accompanying drawings.
[0113] Refer to Figure 9 , Figure 9 which is a structural diagram of a chip testing system provided by the embodiment of the present application. As Figure 9 shown, a chip testing system 90 provided by the embodiment of the present application may include:
[0114] a chip under test 3, a terminal 4, and a chip testing device 10 as Figures 1 to 8 shown.
[0115] The terminal is connected to the main control module 1 of the chip testing device.
[0116] The chip under test is connected to the signal path switching module 2 of the chip testing device.
[0117] The terminal is used to transmit the test task of the chip under test to the main control module.
[0118] The main control module is used to control the signal path switching module to conduct the channel connecting the terminal and the download pin of the chip under test, so that after the terminal downloads the test program to the chip under test, the signal path switching module conducts the test channel, and controls the chip under test to run the test program for test operations based on the test tasks; wherein, the test channel is the channel connecting the main control module and the pins to be tested of the chip under test, and / or the channel connecting the pins to be tested of the chip under test and the test device 5.
[0119] The terminal can be a host computer, and the host computer can be an industrial control computer or a computer. Through the host computer, a friendly human-machine operation environment can be provided for users during the test. After the channel connecting the terminal and the download pin of the chip under test is conducted, the host computer can download the test program to the chip under test through the main control module. After the download and debugging channel of the chip under test is conducted, the chip under test can also be debugged. The host computer can also transmit the test tasks of the chip under test to the main control module, so that the main control module controls the chip under test to perform test operations based on the test tasks. In practical applications, the host computer can pre-define each pin of the chip under test according to the chip specification of the chip under test, and can pre-define each pin of the chip under test through EXCEL to determine the function range of each pin of the chip under test, preventing incorrect configuration of pins when setting test tasks. Then, according to the test requirements of the chip under test, several test tasks are generated. Each test task can include a task number, a test pin, the definition type of the pin, test parameters, etc. A pre-configuration task table can be generated based on the pin pre-definition table and the test tasks, and the pre-configuration task table can be modified as needed. After the task configuration is completed, the host computer generates a task configuration file and sends it to the main control module for task translation and test scheduling. The task configuration file can be in xml format. Task translation means that after the main control chip receives the task configuration file from the host computer, it extracts each test task (such as reset, internal high and low speed oscillator accuracy, TIMER accuracy, PWM, GPIO, UART, IIC, SPI, etc. test tasks) from the file, and converts them into specific test task instructions according to the interface protocol agreed with the chip under test (such as UART test task: including task frame header, frame length, chip pin numbers participating in the test, baud rate, check code, frame tail).
[0120] Optionally, the host computer can also generate a test data and test conclusion table for each task according to the test data returned by the main control module for local storage and viewing. The host computer can also perform test waveform recovery and display according to the returned test data. The waveform has a zoom function and displays key index data.
[0121] Optionally, the main control module is further configured to control the signal path switching module to turn on the channel connecting the clock pin of the chip under test and the clock device, so that the clock device provides a clock signal to the chip under test, and / or, the main control module is further configured to control the signal path switching module to turn on the connection channel between the chip under test and the peripheral components, so as to perform at least one of the reset and mode selection operations of the chip under test.
[0122] In a possible implementation, the signal path switching module includes: a first switch array. The number of the first switch arrays is one or more; if the number of the first switch arrays is one, the controlled end of the first switch array is connected to the main control module, and the output end of the first switch array is connected to multiple pins of the chip under test; if the number of the first switch arrays is multiple, two adjacent first switch arrays are connected through a bus, and the chip under test is connected to the test device through multiple first switch arrays.
[0123] In a possible implementation, the signal path switching module further includes: a selection switch. One input end of the selection switch is connected to the main control module, and multiple output ends of the selection switch are respectively connected to multiple input ends of the first switch array in one-to-one correspondence.
[0124] In a possible implementation, the chip testing device further includes: a power supply control module. The controlled end of the power supply control module is connected to the main control module, and the output end of the power supply control module is connected to the power supply pin of the chip under test; the main control module is configured to control the power supply control module to turn on the power supply channel of the chip under test, so that the power supply device connected to the power supply control module outputs the voltage required by the chip under test to the chip under test.
[0125] In a possible implementation, the power supply control module includes: a second switch array. The input end of the second switch array is connected to the main control module, the power supply end of the second switch array is connected to the power supply device, and the output end of the second switch array is connected to the power supply pin of the chip under test.
[0126] In a possible implementation, the power supply control module further includes: a control unit. The input end of the control unit is connected to the main control module, and the output end of the control unit is connected to the second switch array.
[0127] In a possible implementation, the chip testing system further includes:
[0128] A power supply device;
[0129] The power supply device is connected to the main control module;
[0130] The main control module is configured to control the power supply device to output the voltage required by the chip under test.
[0131] Optionally, the power supply device can also be connected to the power supply control module of the chip testing device. The main control module controls the power supply control module to achieve control of the output voltage of the power supply device, so that the power supply device outputs the voltage required by the chip under test to the chip under test.
[0132] In a possible implementation, the chip testing system further includes:
[0133] A circuit board for the chip under test.
[0134] The circuit board for the chip under test includes a base and an interface.
[0135] The chip under test is installed on the base, and the chip under test is connected to the main control module through the interface.
[0136] Figure 10 It is a schematic diagram of the base of the chip under test. Figure 11 It is a schematic diagram of the circuit board for the chip under test. The interface on the circuit board for the chip under test can be a locking seat, which can be made of gold-plated material. The gold-plated locking seat can be a dual-row gold-plated locking seat. Specifically, DIP (Dual In-line Package) packaging can be adopted, and a DIP36 dual-row gold-plated locking seat can be selected. DIP36 is an integrated circuit or electronic component with 36 pins in a through-hole package.
[0137] Since the packages, cores, pin numbers, and manufacturers of the chips under test are different, different circuit boards are provided for chips with different packages, that is, different chips with the same packaging form can use the same circuit board, while different chips with different packaging forms need to use different circuit boards. The chips under test with different pin numbers, packages, and cores are directly placed into the base, and then the base where the chip under test is located is connected to the main control module through the circuit board. There is no need to design an additional test board, and the rapid testing of different chips can be achieved through the channel switching of the signal path switching module.
[0138] Figure 12 It is a schematic diagram of the overall chip testing structure. Figure 12In it, the host computer 4 is connected to the main control chip 1. The main control chip 1 is respectively connected to four MCUs of the unit under test 82, namely MCU1, MCU2, MCU3, and MCU4. The main control chip can control a number of MCUs through SPI communication and then control the second switch array for power distribution. The communication control includes but is not limited to SPI, IIC, and UART communication. Each MCU is respectively connected to the second switch array 81. The second switch array 81 can be a MOS transistor array. The programmable power supply 9 is respectively connected to four MOS transistor arrays, and the four MOS transistor arrays are all connected to the chip under test. The main control chip 1 is respectively connected to two 1-of-many switches 22, and each 1-of-many switch 22 is respectively connected to the first switch array 21. The chip under test 3 is connected to one first switch array 21, and the other first switch array 21 is respectively connected to the test device 5, the clock device 6, and the peripheral components 7.
[0139] The chip testing system provided by this application realizes the quick connection between chips under test with different packages, different pin numbers, and different cores and power supplies, clocks, and test devices by flexibly configuring the switch array in the main control module, and then realizes the "plug and play" and "one-key testing" of the chips. It greatly improves the chip screening efficiency of chip using manufacturers and the failure rate coverage testing efficiency of products under working conditions, greatly reduces the human and material costs of product R & D, and shortens the R & D cycle.
[0140] In addition, it should be noted that the device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided by this application, the connection relationship between modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines.
[0141] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general hardware. Of course, it can also be implemented by dedicated hardware including application-specific integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits. However, for this application, software program implementation is a better embodiment in more cases. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disc of a computer, and includes several instructions to enable a computer device (which can be a personal computer, training device, or network device, etc.) to execute the methods described in various embodiments of this application.
[0142] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.
[0143] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, training device, or data center to another website, computer, training device, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store, or a data storage device such as a training device or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).
Claims
1. A chip testing device, characterized in that: include: Main control module and signal path switching module; The controlled end of the signal path switching module is connected to the main control module, and the output end of the signal path switching module is connected to a plurality of pins of the chip under test; The main control module is used to control the signal path switching module to conduct the channel connecting the terminal and the download pin of the chip under test, so that the terminal downloads the test program to the chip under test; The main control module is also used to control the signal path switching module to conduct the channel connecting the main control module with the pin to be tested of the chip under test, and / or to control the signal path switching module to conduct the channel connecting the pin to be tested of the chip under test and the testing equipment, so that the chip under test runs the test program to perform the test operation.
2. The chip testing device according to claim 1, characterized in that: The signal path switching module comprises: A first switch array; the number of the first switch array is one or more; If the number of the first switch arrays is one, the controlled end of the first switch array is connected to the main control module, and the output end of the first switch array is connected to a plurality of pins of the chip under test; If there are multiple first switch arrays, two adjacent first switch arrays are connected via a bus, and the chip under test is connected to the test equipment via multiple first switch arrays.
3. The chip testing device according to claim 2, characterized in that: The signal path switching module further includes: Selector switch; An input end of the selection switch is connected to the main control module, and multiple output ends of the selection switch are respectively connected to multiple input ends of the first switch array in a one-to-one correspondence.
4. The chip testing device according to any one of claims 1 to 3, characterized in that: Also includes: Power supply control module; The controlled end of the power supply control module is connected to the main control module, and the output end of the power supply control module is connected to the power supply pin of the chip under test; The main control module is used to control the power supply control module to conduct the power supply channel of the chip under test, so that the power supply device connected to the power supply control module outputs the voltage required by the chip under test to the chip under test.
5. The chip testing device according to claim 4, characterized in that: The power supply control module comprises: a second switch array; The input end of the second switch array is connected to the main control module, the power end of the second switch array is connected to the power supply device, and the output end of the second switch array is connected to the power pin of the chip under test.
6. The chip testing device according to claim 5, characterized in that: The power supply control module further includes: Control unit; The input end of the control unit is connected to the main control module, and the output end of the control unit is connected to the second switch array.
7. The chip testing device according to any one of claims 1 to 3, characterized in that: The main control module is also used to control the signal path switching module to conduct the channel connecting the clock pin of the chip under test and the clock device, so that the clock device provides a clock signal to the chip under test; and / or, The main control module is further used to control the signal path switching module to conduct the connection channel between the chip under test and the peripheral components, so as to perform at least one of the operations of resetting and mode selection of the chip under test.
8. A chip testing system, characterized in that: include: A chip under test, a terminal, and a chip testing device as claimed in any one of claims 1 to 7; The terminal is connected to a main control module of the chip testing device; The chip under test is connected to a signal path switching module of the chip testing device; The terminal is used to transmit the test task of the chip under test to the main control module; The main control module is used to control the signal path switching module to turn on the channel connecting the terminal and the download pin of the chip under test, so that after the terminal downloads the test program to the chip under test, the signal path switching module controls the test channel, and controls the chip under test to run the test program to perform a test operation based on the test task; wherein the test channel is the channel connecting the main control module and the pin to be tested of the chip under test, and / or the channel connecting the pin to be tested of the chip under test and the test equipment.
9. The chip testing system according to claim 8, characterized in that: Also includes: Power supply device; The power supply device is connected to the main control module; The main control module is used to control the power supply device to output the voltage required by the chip under test.
10. The chip testing system according to claim 8 or 9, characterized in that: Also includes: Adapter board for the chip under test; The tested chip adapter board includes a base and an interface; The chip under test is mounted on the base, and the chip under test is connected to the main control module through the interface.