A reliability test system for silicon photonics chips

Abstract

The present invention relates to a reliability testing system for a silicon light emitting chip, comprising: a damp heat test chamber for adjusting a test environment; a chip mounting board placed in the damp heat test chamber, wherein a mounting surface of the chip mounting board is provided with a soldering point area, multiple chip mounting areas and multiple pad areas, each chip mounting area in the multiple chip mounting areas is used for mounting a silicon light emitting chip to be tested, and each pad area in the multiple pad areas is arranged around a corresponding chip mounting area, and each solder point in the soldering point area is electrically connected to the same pin pad of each silicon light emitting chip to be tested in multiple silicon light emitting chips to be tested; a main control board is used to simultaneously adjust the working conditions of multiple silicon light emitting chips to be tested, and to perform reliability tests under various conditions, thereby improving compatibility and test credibility, and also protecting the components of the main control board to avoid the main control board being directly in the temperature control chamber.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon light emitting chip testing, and in particular to a reliability testing system for a silicon light emitting chip. Background Art

[0002] Silicon photonics technology uses silicon and silicon-based substrate materials (such as SiGe / Si, SOI, etc.) as optical media, and uses integrated circuit technology to manufacture corresponding photonic devices and optoelectronic devices (including silicon-based light-emitting devices, modulators, detectors, optical waveguide devices, etc.). These devices are used to excite, process and manipulate photons, realizing their application in multiple fields such as optical communications, optical interconnection, and optical computing.

[0003] Silicon-based photonic chips are manufactured using silicon photonics technology. Their core advantages lie in low cost, high integration, and compatibility with existing semiconductor processes. They are widely used in optical communications, optical computing, sensing, and other fields. However, testing silicon photonic devices faces high-precision and high-complexity challenges, including coupling loss control, thermal stability, and wavelength sensitivity.

[0004] At present, the existing silicon-based photonic chips are tested by designing a universal gyroscope performance test device to test the silicon photonic chips, such as the silicon photonic chip and the universal gyroscope performance test device and method described in publication number CN119104085A, which is tested by combining a gyroscope measurement and control module, an external light source module, an external phase modulator, an optical fiber ring, a light source module and a silicon photonic chip into a test device.

[0005] However, this solution is complex, increasing cost and weight. The device contains other IC chips, making it impossible to conduct comprehensive reliability testing of silicon photonic chips within a wide temperature range and resulting in poor compatibility. Summary of the Invention

[0006] (1) Technical issues to be resolved

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a reliability testing system for a silicon light emitting chip, which solves the technical problem of poor compatibility in the prior art.

[0008] (2) Technical solution

[0009] In order to achieve the above objectives, the main technical solutions adopted by the present invention include:

[0010] An embodiment of the present invention provides a reliability testing system for a silicon light emitting chip, comprising: a damp heat test chamber, which is used to adjust the test environment; a chip mounting board, which can be placed in the damp heat test chamber, and a mounting surface of the chip mounting board is provided with a solder point area, multiple chip mounting areas and multiple pad areas, each of the multiple chip mounting areas is used to mount a silicon light emitting chip to be tested, and each of the multiple pad areas is arranged around the corresponding chip mounting area, and each solder point in the solder point area is electrically connected to the same pin pad of each of the multiple silicon light emitting chips to be tested; a main control board, which can be arranged outside the damp heat test chamber, and the main control board and the chip mounting board are electrically connected, and the main control board is used to simultaneously adjust the working conditions of multiple silicon light emitting chips to be tested, and perform reliability tests under multiple working conditions.

[0011] In one possible embodiment, the solder joint area includes at least one of a first solder joint for testing the reverse bias voltage of a silicon photonic emitter chip to be tested, a second solder joint for testing the power supply voltage of the silicon photonic emitter chip to be tested, a third solder joint for testing the DC performance of the RF port of the silicon photonic emitter chip to be tested, and a fourth solder joint for testing the current of a monitoring photodiode of the silicon photonic emitter chip to be tested.

[0012] In one possible embodiment, the mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of optical fiber arrays mounted on the chip mounting board, and each silicon photonics emitter chip to be tested corresponds to one laser and one optical fiber array; the reliability test includes an optoelectronic performance test;

[0013] Among them, the main control board is specifically used to: when powering all channels of multiple silicon light emitting chips that need to be tested, set the MPD reverse bias voltage of the monitoring photodiode of the silicon light emitting chip that needs to be tested, and couple the optical power of the laser pulse emitted by the corresponding laser to each MZM channel of the corresponding silicon light emitting chip that needs to be tested through the optical fiber array corresponding to the monitoring photodiode, record the laser input optical power of the laser corresponding to the monitoring photodiode, the laser output optical power of the laser corresponding to the monitoring photodiode and the two-way photocurrent of the monitoring photodiode, and calculate and record the MZM modulator insertion loss of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; turn off the laser input optical power, record the two-way dark current of the monitoring photodiode; set the MZM modulator reverse bias voltage of the monitoring photodiode, and record the MZM modulator leakage current of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; adjust its constant Current output, test and record the chip internal resistance of the silicon light emitting chip to be tested corresponding to the monitoring photodiode; when the MZM modulation port of the silicon light emitting chip to be tested corresponding to the monitoring photodiode is connected to the monitoring photodiode through a coaxial cable, set the reverse bias voltage of the MZM modulator, adjust the constant current output until the laser output optical power reaches the highest point, then adjust it back to the linear region of the MZM modulator, and use the corresponding vector network analyzer to perform bandwidth testing and record the bandwidth test data; gradually increase the voltage of the RF port of the MZM modulator to a voltage range related to the reverse bias voltage, and record the minimum optical power and maximum optical power at the power output of the laser corresponding to the monitoring photodiode, and calculate the optical power difference between the maximum optical power and the minimum optical power as the optical modulation amplitude; after the preset power-on time, repeat the above steps to obtain new recorded data after the repeated execution, and compare the new recorded data with the recorded data obtained before the repeated execution to obtain the test results of the photoelectric performance test.

[0014] In one possible embodiment, the reliability test further includes a quality test, and passing the quality test means that the modulator leakage current of the silicon photonic emission chip to be tested does not change after the test environment is changed, the terminal resistance of the silicon photonic emission chip to be tested does not change after the test environment is changed, and the dark current of the monitoring photodiode does not change after the test environment is changed.

[0015] In one possible embodiment, the main control board includes a main control device and multiple slave control devices communicatively connected to the main control device, and each of the multiple slave control devices is electrically connected to a connection socket of the main control board through multiple multi-channel operational amplifiers, and the multiple slave control devices are used to sample the monitoring photodiodes of multiple silicon light emitting chips that need to be tested on the chip mounting board and to regulate the current of the multiple silicon light emitting chips that need to be tested on the chip mounting board.

[0016] In one possible embodiment, the main control board further includes multiple second Buck buck chips, and each slave control device is electrically connected to a connection socket of the main control board through a second Buck buck chip, and the connection socket between each Buck buck chip in the multiple second Buck buck chips and the main control board is also electrically connected to a pad on the main control board. The pad on the main control board is used to measure the power supply voltage required by the main control board to provide to the chip mounting board and the reverse bias voltage required by the main control board to provide to the chip mounting board.

[0017] In a possible embodiment, the main control board further includes a power interface, a first Buck step-down chip, and a low-voltage dropout linear regulator electrically connected in sequence, and the low-voltage dropout linear regulator is electrically connected to the main control device and each slave control device respectively.

[0018] In a possible embodiment, the main control board further includes a package socket and multiple JTAG pin connection interfaces, the package socket is used to burn firmware to the main control device, and the multiple JTAG pin connection interfaces are used to burn firmware to multiple slave control devices.

[0019] (3) Beneficial effects

[0020] The beneficial effects of the present invention are:

[0021] The embodiment of the present application provides a reliability testing system for silicon light emitting chips. When in use, the silicon light emitting chip to be tested is mounted on a chip mounting board, and the chip mounting board is placed in a damp heat test chamber with adjustable temperature and humidity. At the same time, the main control board is placed in a conventional environment. By controlling the main control board through host computer software, the long-term reliability and performance of the silicon light emitting chip on the chip mounting board under various environmental and operating conditions can be verified. Compared with the traditional testing of silicon light emitting chips on a wafer test system, the long-term reliability and performance of the silicon light emitting chip under various environmental and operating pressure conditions can be tested and verified, and the stability of other electrical chips on the main control board can be protected. At the same time, the chip mounting board and the main control board are small in size and easy to carry. The main control board can be adjusted in real time by the host computer, and data can be read and analyzed by the host computer. Different types of silicon light emitting chips can also be tested, and the compatibility is good.

[0022] In order to make the above-mentioned objectives, features and advantages to be achieved by the embodiments of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A schematic diagram of a reliability testing system for a silicon photonics chip provided in an embodiment of the present application is shown;

[0025] Figure 2 A schematic structural diagram of a chip mounting board provided in an embodiment of the present application is shown;

[0026] Figure 3 A schematic structural diagram of a main control board provided in an embodiment of the present application is shown;

[0027] Figure 4 A schematic diagram showing a power supply structure of a main control board provided in an embodiment of the present application is shown;

[0028] Figure 5 A schematic diagram showing communication between a master and slave control device according to an embodiment of the present application is shown;

[0029] Figure 6 A schematic diagram showing a collaborative working principle provided by an embodiment of the present application is shown;

[0030] Figure 7 A schematic diagram of controlling and adjusting the reverse bias voltage and supply voltage of a control board provided in an embodiment of the present application is shown;

[0031] Figure 8 A schematic diagram of a portion of the structure of a mounting surface of a chip mounting board provided in an embodiment of the present application is shown;

[0032] Figure 9 A flow chart of a quality testing method provided in an embodiment of the present application is shown.

[0033] [Description of Reference Numerals]

[0034] 100: wet heat test chamber;

[0035] 200: Chip mounting board;

[0036] 300: main control board;

[0037] 210: Silicon photonics chip;

[0038] 220: pad area;

[0039] 230: solder joint area;

[0040] 240: Connector on chip mounting board;

[0041] 310: power interface;

[0042] 320: Toggle switch;

[0043] 330: standard USB interface;

[0044] 340: JTAG pin connection interface;

[0045] 350: Package socket;

[0046] 360: The first Buck step-down chip;

[0047] 370: Second Buck step-down chip;

[0048] 380: Low dropout linear regulator;

[0049] 390: Connector on the main control board. DETAILED DESCRIPTION

[0050] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation methods in conjunction with the accompanying drawings.

[0051] Currently, in addition to testing silicon photonic chips by designing a universal gyroscope performance test device, existing testing methods for silicon photonic chips also include the following two testing methods:

[0052] One testing method involves moving a probe station on a coupling station to bring the probe card into contact with the chip pin pads. This method is suitable for testing the photodiodes (PDs) of multi-channel silicon photonic chips. For example, the silicon photonic chip testing method and device described in Publication No. CN119087173A places the silicon photonic emitter chip to be tested in the middle of the device's coupling station, and the test is performed by fully contacting the chip with the probe cards on both sides of the coupling station. However, this solution is bulky, uses the probes of the coupling station for contact, and adds probe cards to the structure, increasing costs. Furthermore, when moving the coupling station, the contact points between the probe card and the chip pin pads are highly demanding. As a result, only one silicon photonic chip can be tested at a time, resulting in low efficiency.

[0053] Another testing method is to design a test device such as an intermediate stage to accommodate the chip under test. For example, the silicon photonic chip testing device and test method described in Publication No. CN117191358A uses an intermediate stage assembly, left and right adjustment modules, an upper visual assembly, and a probe card adjustment assembly to complete the test through a combination of visual and pressure detection. However, this solution is large in structure and complex to operate. The stage also includes a water cooling device and a nitrogen purge device. It can only test the coupling of silicon photonic chips and cannot perform reliability testing on the electrical performance parameters of silicon photonic chips.

[0054] Based on this, an embodiment of the present application provides a reliability testing system for a silicon light emitting chip. When in use, the silicon light emitting chip is mounted on a chip mounting board, the chip mounting board is placed inside a damp heat test chamber with adjustable temperature, humidity, etc., and the main control board is placed in a conventional environment (i.e., it is outside the damp heat test chamber). The main control board can be connected to the main control board via connectors and cables on the chip mounting board. The main control board is controlled by host computer software, thereby enabling the long-term reliability and performance of the silicon light emitting chip on the chip mounting board to be verified under various environmental and operating conditions. For example, temperature cycling, damp heat, low-temperature and high-temperature storage, and high-temperature operation tests, including equipment aging and power-on damp heat. In addition, the electro-optical performance before and after each stress test is compared against the pass / fail criteria. Compared with the traditional silicon photonics chip testing on the wafer test system, it can not only test and verify the long-term reliability and performance of the silicon photonics chip under various environmental and operating pressure conditions, but also protect the stability of other electronic chips on the main control board; at the same time, due to the small structure and easy portability of the chip mounting board and the main control board, the pressure conditions can be adjusted in real time by the host computer, and the data can be read and analyzed by the host computer, and different types of silicon photonics chips can also be tested, with good compatibility.

[0055] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0056] See Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of a reliability testing system for a silicon light emitting chip provided in an embodiment of the present application. Figure 1 As shown, the reliability test system includes:

[0057] A damp heat test chamber 100 is used to adjust the test environment, that is, it can adjust the temperature, humidity, etc.;

[0058] A chip mounting board 200, which can be placed inside the damp heat test chamber 100, and a mounting surface of the chip mounting board 200 is provided with a solder joint area, multiple chip mounting areas, and multiple pad areas. Each chip mounting area in the multiple chip mounting areas is used to mount a silicon light emitting chip to be tested, and each pad area in the multiple pad areas is arranged around a corresponding chip mounting area, and each solder joint in the solder joint area is electrically connected to the same pin pad of each silicon light emitting chip to be tested in the multiple silicon light emitting chips to be tested; wherein, each chip mounting area corresponds to one pad area;

[0059] The main control board 300 can be set outside the damp heat test chamber 100 and is electrically connected to the chip mounting board 200. The main control board is used to simultaneously adjust the operating conditions of multiple silicon photonic emitter chips that need to be tested and perform reliability tests under multiple operating conditions (or multiple situations).

[0060] It should be understood that the specific humidity and heat test chamber can be set according to actual needs, and the embodiments of the present application are not limited thereto.

[0061] It should also be understood that the specific structure of the chip mounting board 200 can also be set according to actual needs, and the embodiments of the present application are not limited thereto.

[0062] Specifically, see Figure 2 , Figure 2 FIG. 2 shows a schematic structural diagram of a chip mounting board 200 provided in an embodiment of the present application. Figure 2As shown, in order to prevent the electrical chip from failing under high temperature and high humidity stress testing, no other electrical chips are mounted on the chip mounting board 200. Only eight silicon light emitting chips 210 that need to be tested are mounted on the mounting surface of the chip mounting board 200. A pad area 220 is set around each silicon light emitting chip 210 that needs to be tested, and the multiple pads of the pad area 220 are convenient for bonding with the DC pin pad DC Pad of the silicon light emitting chip 210, so as to perform routing on the PCB board of the chip mounting board 200, including the phase modulation current pin pad of the silicon light emitting chip 210. The chip mounting board 200 also has a solder pad area 230 on its mounting surface. This solder pad area 230 includes at least one of a first solder pad (or reverse bias voltage pad) for testing the reverse bias voltage (which may include the MPD reverse bias voltage and the MZM modulator reverse bias voltage) of the silicon photonics transmitter chip 210 to be tested, a second solder pad (or supply voltage pad) for testing the power supply voltage of the silicon photonics transmitter chip 210 to be tested, a third solder pad (or high-speed RF line pad) for testing the DC performance of the high-speed RF port of the silicon photonics transmitter chip 210 to be tested, and a fourth solder pad (or monitoring photodiode pad) for testing the current of the monitoring photodiode of the silicon photonics transmitter chip 210 to be tested. Furthermore, the chip mounting board 200 may also be provided with connecting wires (not shown) and a connector 240 (e.g., a right-angle connector) on the chip mounting board that is resistant to high temperature and humidity for interfacing with the main control board. The high-speed RF port may also be referred to as an RF port.

[0063] In addition, the RF Pad of each silicon photonics emitter chip 210 can be connected to the RF Pad solder joints through wire bonding, and the RF port DC performance can be tested with a probe; the MPD Pad can be used to measure the actual current value by contacting the solder joints with a probe, or it can be connected to the main control board through the wiring and the connector 240 on the chip mounting board, and the sampled data can be read through the electrical chip on the main control board; the reverse bias voltage Pad and the power supply voltage Pad can be directly supplied with the required voltage through an external source meter, or the real-time voltage can be tested with a multimeter to determine whether the voltage adjustment on the main control board is correctly applied to the reverse bias voltage and power supply voltage on the chip mounting board through the connector 240 on the chip mounting board; through the voltage adjustment on the main control board, the working conditions of the silicon photonics emitter chip 210 on the mounting board under different voltages can be controlled to better perform corresponding reliability tests on the silicon photonics emitter chip 210.

[0064] It should be noted here that although Figure 2The description is based on an example of eight silicon photonics emitting chips that need to be tested and their eight pad areas and a solder point area with three solder points. However, those skilled in the art should understand that the chip mounting board may also be provided with more or fewer pad areas, and the solder point area may include more or fewer solder points, thereby enabling reliability testing of more or fewer silicon photonics emitting chips at the same time.

[0065] It should also be understood that the specific structure of the main control board can also be set according to actual needs, and the embodiments of the present application are not limited to this.

[0066] Specifically, in order to control, regulate voltage, and sample data on the chip mounting board, the main control board 300 includes: a power interface 310 (e.g., a square power socket), a toggle switch 320, a standard USB interface 330, a JTAG (Joint Test Action Group) pin connection interface 340, a package socket 350 (e.g., a dual-in-line package socket), a first Buck step-down chip 360, a second Buck step-down chip 370, a low-dropout linear regulator 380, a connector 390 on the main control board, and other devices. For details, see Figure 3 Related content.

[0067] It should be understood that Figure 3 Only some devices of the main control board 300 are marked. For example, the main control board may also include metal oxide semiconductor field effect transistors (MOSFETs), transient voltage suppressor diodes (TVSs), control devices (such as microcontrollers MCUs), multi-channel operational amplifiers (OAs), power protectors, etc. However, these devices are not listed in the main control board 300. Figure 3 Not marked in.

[0068] Furthermore, if Figure 4 As shown in the figure, the power interface of the main control board is powered on by connecting the source meter SMU, and the power supply is protected against undervoltage, overvoltage and reverse power supply through the toggle switch, power protector and metal oxide semiconductor field effect transistor, so that the voltage provided by the source meter is within the set range to power the main control board, and the power supply is indicated by the power indicator.

[0069] And, continue to see Figure 4The power supply voltage is converted into the required power supply voltage through a first Buck step-down chip (for example, a DC-DC Buck power supply chip, etc.) and a low dropout regulator (LDO) to power the control device and other devices.

[0070] It should be noted here that although Figure 4 The low voltage drop linear regulator is used as an example for description, but those skilled in the art should understand that it can also be used according to actual needs. Figure 4 The low voltage difference linear regulator in the embodiment is replaced with other step-down chips, but the embodiments of the present application are not limited to this.

[0071] Furthermore, if Figure 5 As shown, the control device of the main control board may include a master control device and two slave control devices, and the master control device may start all communications on the I2C bus and provide clocks for all slave control devices, and determine which slave control device to communicate with by address selection.

[0072] It should be understood that although Figure 5 The description is made by taking two slave control devices as an example, but those skilled in the art should understand that the control device may include more or fewer slave control devices, and the embodiments of the present application are not limited to this.

[0073] Furthermore, if Figure 6 As shown, multiple slave control devices are responsible for providing multi-channel voltage drive and outputting constant current through multiple multi-channel operational amplifiers. The current is input to multiple silicon light emitting chips on the chip mounting board through the connector on the main control board to provide the working current of the silicon light emitting chips. The current can be regulated by the voltage drive regulation of the slave control devices. The main control device is responsible for the output acquisition of the constant power supply. At the same time, the multiple slave control devices can also sample the monitoring photodiodes MPD of the multiple silicon light emitting chips on the chip mounting board to analyze whether the corresponding monitoring photodiodes MPD are in normal working condition. Among them, MPD sampling in this application refers to the main control device converting the constant current output by multiple multi-channel operational amplifiers into voltage for sampling to determine the output constant current situation.

[0074] What needs to be explained here is that Figure 6 Each of the multiple drive currents is sampled by a sampling resistor.

[0075] It should be understood that although Figure 6 The description is made by taking one slave control device connected to two multi-channel operational amplifiers as an example, but those skilled in the art should understand that each slave control device can be connected to more multi-channel operational amplifiers, and the embodiments of the present application are not limited to this.

[0076] Furthermore, if Figure 7 As shown, the main control board further includes two second Buck step-down chips, and each slave control device is electrically connected to a connector on the main control board via a second Buck step-down chip. Each trace between the multiple second Buck step-down chips and the connector on the main control board is also electrically connected to multiple pads. The multiple pads are used to measure the power supply voltage and reverse bias voltage required by the main control board to provide to the chip mounting board. This allows the reverse bias voltage and power supply voltage of the multiple silicon photonic emitter chips to be controlled and adjusted. The reverse bias voltage and power supply voltage are also input to the multiple silicon photonic emitter chips on the chip mounting board via the connector on the main control board, and the reverse bias voltage and power supply voltage can be measured via the multiple pads. Both the main control board and the chip mounting board have pads for measuring the reverse bias voltage and power supply voltage.

[0077] It should be understood that although Figure 7 The description is made using two second Buck step-down chips as an example, but those skilled in the art should understand that when the control device may include more or fewer slave control devices, the number of the second Buck step-down chips may be adjusted accordingly with the number of slave control devices, and the embodiments of the present application are not limited to this.

[0078] Furthermore, the main control board further includes a packaging socket and a plurality of JTAG pin connection interfaces, the packaging socket is used to burn firmware to the main control device, and the plurality of JTAG pin connection interfaces are used to burn firmware to the plurality of slave control devices.

[0079] After the above steps have been completed to set up the main control board before testing (for example, checking whether the provided voltage is set correctly), the reliability test of multiple silicon photonics emitter chips that need to be tested can be performed by connecting the main control board and the chip mounting board. This reliability test includes optoelectronic performance testing and quality testing. The optoelectronic performance test tests the changes in the optical performance of the silicon photonics emitter chip under indoor environmental conditions, including optical output power, backlight current, and modulation bandwidth. The quality test evaluates the long-term reliability and performance of the silicon photonics emitter chip under various environmental and operating stress conditions, including temperature cycling (TC), damp-heat storage (DHS), low temperature storage (LTS), high temperature storage (HTS), high-temperature operation test of the silicon photonics emitter chip, and damp-heat power-up test of the silicon photonics emitter chip.

[0080] Furthermore, the mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of optical fiber arrays mounted on the chip mounting board, and as Figure 8 As shown, each silicon photonics chip that needs to be tested corresponds to a laser and a fiber array.

[0081] Furthermore, the photoelectric performance test can also be tested and verified under multiple test conditions. For different test conditions, the temperature, humidity, power supply voltage, etc. can be changed, and the photoelectric performance test is not limited to only one test condition.

[0082] The process of the photoelectric performance test includes: when all channels of multiple silicon photonics chips to be tested are powered, the MPD reverse bias voltage of the monitoring photodiode is set, and the optical power of the laser pulse emitted by the corresponding laser of the monitoring photodiode is coupled to each MZM channel of the corresponding silicon photonics chip to be tested through the optical fiber array corresponding to the monitoring photodiode, and the laser input optical power P of the laser corresponding to the monitoring photodiode is recorded. in , the laser output optical power P of the laser corresponding to the monitoring photodiode out and the two photocurrents of the monitoring photodiode (i.e., when the MZM modulator is branched into two paths, the two photocurrents are the photocurrent I of the a branch and pd_a and the photocurrent I of branch b pd_b ), and calculate and record the MZM modulator insertion loss IL of the corresponding channel of the silicon photonics transmitter chip to be tested corresponding to the monitoring photodiode MPD MZM ; Turn off the laser input light power P in , record the two dark currents of the monitoring photodiode (that is, when the MZM modulator is divided into two branches, the two dark currents are the dark current I of branch a and the dark current I of branch b). pd_dark_a and the dark current I of branch b pd_dark_b ); Set the reverse bias voltage of the MZM modulator of the monitoring photodiode and record the MZM modulator leakage current I corresponding to the channel of the silicon light emitting chip to be tested corresponding to the monitoring photodiode Leak ; Adjust the constant current I of the main control board H Output, test and record the chip internal resistance R of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode H ;

[0083] Reopen the laser light path and record the laser input optical power P using an optical power meter. in , scanning constant current I H , when the output optical power P out When the current changes by one cycle, record the current I after one cycle change. H_PSince the optical power changes sinusoidally with the input current, the current size after one cycle of optical power change is recorded as the reference current of the subsequent constant current input value, which is convenient for the reference of the constant current input size. Therefore, this value is used as the reference value and driving condition in the subsequent high temperature working test;

[0084] When the monitoring photodiode is connected to the MZM modulation port of the silicon phototransmitter chip to be tested via a coaxial cable, the reverse bias voltage of the MZM modulator is set and the constant current I is adjusted. H Output until the laser output light power P out After reaching the highest point, adjust the constant current to return to the linear region of the MZM modulator, and use the corresponding vector network analyzer to perform a small signal bandwidth test, record the bandwidth test data Bandwidth, and use it as a comparison reference; gradually increase the voltage of the RF port of the MZM modulator to a voltage range related to the reverse bias voltage (for example, the voltage range can be reverse bias voltage ±1.5V, etc.), and record the minimum optical power P at the power output of the laser corresponding to the monitoring photodiode (i.e., the laser input optical power). MZM_min and the maximum optical power P MZM_max , and calculate the maximum optical power P MZM_max and minimum optical power P MZM_min The optical power difference is used as the optical modulation amplitude OMA, and the optical modulation amplitude OMA is used as a comparison reference. After the power is turned on for a preset time, the above steps are repeated to obtain new recorded data after the repeated execution. The new recorded data is compared with the recorded data obtained before the repeated execution to determine whether the test has passed, and then the test results of the photoelectric performance test are obtained. Among them, the determination of whether the photoelectric performance test has passed is based on setting a change standard.

[0085] In addition, the quality test is passed when the modulator leakage current of the silicon photonics chip to be tested does not change after the test environment is changed, the terminal resistance (or heater resistance) of the silicon photonics chip to be tested does not change after the test environment is changed, and the dark current of the monitored photodiode (the dark current here refers to the dark current obtained when the laser and optical fiber array are not turned on) does not change after the test environment is changed.

[0086] For example, multiple channels of different constant current outputs can be achieved through multi-channel digital-to-analog converters DAC; for the sampling of the monitoring photodiode MPD, the sampling voltage is fed back to the slave control device through the sampling resistor, and the slave control device displays it to monitor whether the sampling of the monitoring photodiode MPD of the silicon photonic chip changes under different working conditions, and to judge whether the monitoring photodiode MPD of the silicon photonic chip changes; for the terminal resistance of the silicon photonic emitter chip, the constant current and sampling voltage are input to judge whether the terminal resistance of the silicon photonic chip changes.

[0087] It should be understood that the specific process of the quality test can be set according to actual needs, and the embodiments of the present application are not limited to this.

[0088] Specifically, if Figure 9 As shown, Figure 9 The following is a flow chart showing a quality testing method provided by an embodiment of the present application. Specifically, the quality testing method includes:

[0089] Step S910, power-on test;

[0090] Step S920: Setting the supply voltage and reverse bias voltage. Furthermore, the supply voltage and reverse bias voltage may vary under different test conditions.

[0091] Step S930: Check whether the MPD sampling is passed;

[0092] If the constant current sampled by the MPD does not change after the test environment is adjusted for the preset time, the MPD sampling is considered to have passed, and step S940 is executed; if the constant current sampled by the MPD changes after the test environment is adjusted for the preset time, step S970 is executed;

[0093] Step S940: whether the terminal resistance of the silicon photonics emitter chip passes the test;

[0094] If the terminal resistance test of the silicon light emitting chip passes, step S950 is executed; if the terminal resistance test of the silicon light emitting chip fails, step S970 is executed;

[0095] Step S950, whether the dark current test is passed;

[0096] If the dark current test passes, step S960 is executed; if the dark current test fails, step S970 is executed;

[0097] Step S960 , determining whether the silicon photonics transmitter chip currently to be tested has passed the test in the working environment, and then proceeding to the next silicon photonics transmitter chip for testing, and then performing a power-on test.

[0098] It should be noted here that multiple (for example, eight) silicon photonics emitter chips on the chip mounting board are sampled and tested simultaneously. After the multiple silicon photonics emitter chips have completed the test, multiple new silicon photonics emitter chips are replaced on the chip mounting board and the above test steps are repeated.

[0099] Step S970: The silicon photonics emitter chip currently to be tested fails the test.

[0100] Therefore, with the help of the above technical solution, a chip mounting board with only silicon photonic emitter chips mounted thereon is placed in a damp heat test chamber (with adjustable temperature, humidity, etc.), and the reliability of the silicon photonic emitter chips is tested in conjunction with a main control board placed in a conventional environment. This can not only test and verify the long-term reliability and performance of the silicon photonic emitter chips under various environments and working conditions, but also ensure that the electrical chips in the test solution are all in a conventional environment, thereby ensuring the reliability of the electrical chips and saving costs. The system is small in size and simple in structure, can be independently tested and verified, occupies little space, is portable, easy to develop, has a short development cycle, and improves the stability of the test system. At the same time, it can also be combined with different types of silicon photonic emitter chips for testing and verification. According to the customer's working conditions and test requirements, the main control board can be used to maximize the role of the main control board and improve the compatibility of the test system. The chip mounting board can mount multiple silicon photonic emitter chips, and the main control board has the functions of adjusting, controlling, sampling, etc. for multiple silicon photonic emitter chips. The reliability and performance of multiple silicon photonic emitter chips can be tested and verified at the same time, improving product testing efficiency and shortening test time.

[0101] It should be understood that the above-mentioned reliability testing system for silicon photonic emitter chips is merely exemplary, and those skilled in the art may make various modifications based on the above-mentioned method, and the modified schemes also fall within the scope of protection of this application.

[0102] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0103] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each process flow and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions.

[0104] It should be noted that the word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention may be implemented by means of hardware comprising several distinct components and by means of a suitably programmed computer. Among the several devices listed, several of these devices may be embodied by the same hardware. The use of the words first, second, third, etc., is for convenience only and does not imply any order. These words should be understood as part of the component name.

[0105] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0106] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments after learning the basic creative concepts. Therefore, the technical solutions should be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0107] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the technical solution of the present invention and its equivalents, the present invention shall also include such modifications and variations.

Claims

1. A reliability testing system for a silicon photonics chip, characterized in that: include: A humidity and heat test chamber, which is used to adjust the test environment; A chip mounting board, wherein the chip mounting board can be placed in the damp heat test chamber, and the mounting surface of the chip mounting board is provided with a solder point area, multiple chip mounting areas, and multiple pad areas, each of the multiple chip mounting areas is used to mount a silicon light emitting chip to be tested, and each of the multiple pad areas is arranged around a corresponding chip mounting area, and each solder point in the solder point area is electrically connected to the same pin pad of each of the multiple silicon light emitting chips to be tested; A main control board, which can be arranged outside the damp heat test chamber and is electrically connected to the chip mounting board. The main control board is used to simultaneously adjust the working conditions of multiple silicon photonic emitter chips that need to be tested and perform reliability tests under multiple working conditions. The mounting surface of the chip mounting board is further provided with a plurality of lasers and a plurality of optical fiber arrays mounted on the chip mounting board, and each silicon photon emission chip to be tested corresponds to one of the lasers and one of the optical fiber arrays; the reliability test includes an optoelectronic performance test; Among them, the main control board is specifically used to: when powering all channels of the multiple silicon light emitting chips that need to be tested, set the MPD reverse bias voltage of the monitoring photodiode of the silicon light emitting chip that needs to be tested, and couple the optical power of the laser pulse emitted by the corresponding laser to each MZM channel of the corresponding silicon light emitting chip that needs to be tested through the optical fiber array corresponding to the monitoring photodiode, record the laser input optical power of the laser corresponding to the monitoring photodiode, the laser output optical power of the laser corresponding to the monitoring photodiode and the two-way photocurrent of the monitoring photodiode, and calculate and record the MZM modulator insertion loss of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; turn off the laser input optical power and record the two-way dark current of the monitoring photodiode; set the MZM modulator reverse bias voltage of the monitoring photodiode and record the MZM modulator leakage current of the corresponding channel of the silicon light emitting chip that needs to be tested corresponding to the monitoring photodiode; adjust its Constant current output, testing and recording the chip internal resistance of the silicon light emitting chip to be tested corresponding to the monitoring photodiode; when the MZM modulator port of the silicon light emitting chip to be tested corresponding to the monitoring photodiode is connected via a coaxial cable, setting the reverse bias voltage of the MZM modulator, adjusting the constant current output until the laser output optical power reaches the highest point, then adjusting it back to the linear region of the MZM modulator, and performing a bandwidth test with a corresponding vector network analyzer to record the bandwidth test data; gradually increasing the voltage of the RF port of the MZM modulator to within a voltage range related to the reverse bias voltage, and recording the minimum optical power and maximum optical power at the power output of the laser corresponding to the monitoring photodiode, and calculating the optical power difference between the maximum optical power and the minimum optical power as the optical modulation amplitude; after a preset power-on time, repeating the above steps to obtain new recorded data obtained after repeated execution, and comparing the new recorded data with the recorded data obtained before repeated execution to obtain the test results of the photoelectric performance test.

2. The reliability testing system according to claim 1, wherein: The solder joint area includes at least one of a first solder joint for testing the reverse bias voltage of the silicon photonic emission chip to be tested, a second solder joint for testing the power supply voltage of the silicon photonic emission chip to be tested, a third solder joint for testing the DC performance of the RF port of the silicon photonic emission chip to be tested, and a fourth solder joint for testing the current of the monitoring photodiode of the silicon photonic emission chip to be tested.

3. The reliability testing system according to claim 1, wherein: The reliability test further includes a quality test, and passing the quality test means that after the test environment is changed, the modulator leakage current of the silicon light emitting chip to be tested does not change, the terminal resistance of the silicon light emitting chip to be tested does not change after the test environment is changed, and the dark current of the monitoring photodiode does not change after the test environment is changed.

4. The reliability testing system according to claim 3, wherein: The main control board includes a main control device and multiple slave control devices communicatively connected to the main control device, and each of the multiple slave control devices is electrically connected to the connection socket of the main control board through multiple multi-channel operational amplifiers, and the multiple slave control devices are used to sample the monitoring photodiodes of the multiple silicon light emitting chips that need to be tested on the chip mounting board and to regulate the current of the multiple silicon light emitting chips that need to be tested on the chip mounting board.

5. The reliability testing system according to claim 4, characterized in that: The main control board further includes a plurality of second Buck buck chips, and each of the slave control devices is electrically connected to the connection socket of the main control board via a second Buck buck chip, and each of the plurality of second Buck buck chips and the connection socket of the main control board are electrically connected to the pads on the main control board, and the pads on the main control board are used to measure the power supply voltage required by the main control board to provide to the chip mounting board and the reverse bias voltage required by the main control board to provide to the chip mounting board.

6. The reliability testing system according to claim 5, characterized in that: The main control board further includes a power supply interface, a first Buck step-down chip and a low-voltage difference linear regulator electrically connected in sequence, and the low-voltage difference linear regulator is electrically connected to the main control device and each of the slave control devices respectively.

7. The reliability testing system according to claim 6, characterized in that: The main control board further includes a packaging socket and a plurality of JTAG pin connection interfaces, the packaging socket is used to burn firmware to the main control device, and the plurality of JTAG pin connection interfaces are used to burn firmware to the plurality of slave control devices.

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