Reset isolation method of server baseboard management controller chip and memory

Abstract

The invention relates to the technical field of baseboard management controllers, in particular to a reset isolation method of a server baseboard management controller chip and a storer, and the method comprises the following steps: when an upper computer or an internal processor reads and writes a memory, firstly adding read-write data to a cache, and then sending the read-write data through the cache; and when the upper computer or the internal processor triggers a reset operation, maintaining a read-write operation based on the cache, and isolating a memory reset instruction. Aiming at the problems of memory data loss and transmission interruption caused by reset operation of a substrate management controller chip in the prior art, a cache mechanism is introduced, and data continuous transmission in a reset process is maintained by caching read-write data of an upper computer and an internal processor; and meanwhile, the reset upper computer or the reset internal processor is isolated, so that the problem that normal work of the internal processor or the upper computer on the other side is affected due to data loss of a memory in the reset process is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of baseboard management controllers, and in particular, to a reset isolation method and a memory for a server baseboard management controller chip. Background Art

[0002] A baseboard management controller chip (Baseboard Management Controller, BMC) is a controller designed specifically for monitoring and managing servers. The BMC chip is responsible for device information management, server status monitoring, remote control management, and maintenance management, and ensures the stable and efficient operation of the server through these functions. It is independent of the server's main system and runs as a small operating system on an integrated ARM processor, with its own memory and flash memory. In current technologies, the baseboard management controller chip communicates with the host computer (server) through PCIe. There are multiple modules in the BMC chip controlled by the CPU on the baseboard management controller chip, while the display controller is controlled and driven by the host computer. The host computer and the baseboard management controller chip system itself will jointly use a shared memory space and perform read and write operations on the data.

[0003] For example, Chinese Patent CN202311112118.9 discloses a server management board and a server. The server management board includes: a BMC chip, a DDR memory module, a CPLD chip, a serial port, an interface chip, a CPU socket, and a PCIe switch chip; the BMC chip is electrically connected to the DDR memory module, the CPLD chip, and the CPU socket; the serial port is electrically connected to the CPLD chip through the interface chip, and the interface chip is used to convert the output level of the serial port into a level adapted to the BMC chip; the CPU socket is electrically connected to the first end of the PCIe switch chip, and multiple second ends of the PCIe switch chip are used to connect multiple computing boards.

[0004] However, since the memory space of DDR is shared, when the host computer or the baseboard management controller chip is reset, the reset side will perform a reset operation on the memory, resulting in the loss of memory data and the interruption of data on the other side. Summary of the Invention

[0005] In view of the above problems existing in the prior art, the present invention provides a reset isolation method and a memory for a server baseboard management controller chip.

[0006] The specific technical solution is as follows: A reset isolation method for a server baseboard management controller chip, where the server baseboard management controller chip includes an internal processor and a bus, and the baseboard management controller chip is connected to a host computer and a memory; the host computer and the internal processor respectively read and write the memory through the bus; the reset isolation method includes: Step S1: When the host computer or the internal processor reads and writes the memory, first add the read and write data to a cache, and then send the read and write data through the cache; Step S2: Monitor the host computer or the internal processor, and when the host computer or the internal processor triggers a reset operation, go to Step S3; Step S3: Maintain the read and write operations based on the cache, and isolate the memory reset instruction output by the host computer or the internal processor that is being reset to the memory.

[0007] On the other hand, Step S1 includes: Step S11: Read and determine the operation instruction input by the host computer or the internal processor to the bus. When it is determined to be a read and write instruction, go to Step S12; Step S12: When the read and write instruction is a read operation, obtain read data from the memory and write it into the cache. And when the read and write instruction is a write operation, write the write data into the cache in sequence; Step S13: Transfer the read data to the host computer or the internal processor from the cache in the read and write order, or write the write data into the memory in the read and write order.

[0008] On the other hand, when executing Step S12, a monitor is also created, and the monitor is used to monitor the internal processor or the host computer in Step S2.

[0009] On the other hand, in Step S12, when executing the read and write instruction, a corresponding cache index is constructed for the read data or the write data; in Step S13, a first-in-first-out operation is performed according to the cache index.

[0010] On the other hand, Step S2 includes: Collect the operation instructions sent by the internal processor or the host computer to the bus through the monitor, and determine whether a reset operation occurs.

[0011] On the other hand, the step S3 includes: step S31: isolate the memory reset instruction, and determine whether the current operation is a read operation; if so, go to step S32; if not, go to step S33; step S32: after waiting for the upper computer or the internal processor to complete the reset, continue to send the read data to the upper computer or the internal processor according to the read-write sequence; step S33: continue to send the write data to the memory according to the read-write sequence, and continue to write to the cache after the upper computer or the internal processor completes the reset.

[0012] On the other hand, before executing the step S32 or the step S33, it further includes: step A31: in the cache, perform operation marks on each piece of data for read-write operations respectively, and start a read-write timer during each transmission operation; step A32: when the read-write timer times out, it is considered that the upper computer or the internal processor is resetting.

[0013] On the other hand, during the execution of the step S32 or the step S33, determine the breakpoint according to the operation mark, and resend the read-write data.

[0014] On the other hand, during the execution of the step S3, it further includes: step A4: when the internal processor or the upper computer on the other side issues a read-write instruction, the bus operates on the memory and obtains the read-write data.

[0015] A memory includes computer instructions, and when a computer device runs the computer instructions, the above-mentioned reset isolation method is executed.

[0016] The above technical solution has the following advantages or beneficial effects: In view of the problem that the memory data is lost and the transmission is interrupted when the server baseboard management controller chip in the prior art performs a reset operation, in this embodiment, a cache mechanism is introduced on one side of the bus. By caching the read-write data of the upper computer and the internal processor, the continuous data transmission during the reset process is maintained. At the same time, the reset upper computer or internal processor is isolated to avoid the problem that the data in the memory is lost during the reset process and affects the normal operation of the internal processor or the upper computer on the other side. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Referring to the accompanying drawings, the embodiments of the present invention are described more fully. However, the accompanying drawings are only for illustration and explanation, and do not constitute a limitation on the scope of the present invention.

[0018] Figure 1 It is a schematic diagram of the whole of the embodiment of the present invention; Figure 2 It is a schematic diagram of the architecture of the server baseboard management controller chip; Figure 3 Schematic diagram of the architecture of the server baseboard management controller chip in an embodiment of the present invention; Figure 4 Schematic diagram of step S1 in an embodiment of the present invention; Figure 5 Schematic diagram of step S3 in an embodiment of the present invention. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0021] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0022] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0023] The present invention includes: a reset isolation method for a server baseboard management controller chip, as Figure 1 , Figure 2 shown, the baseboard management controller chip U4 includes an internal processor U7 and a bus U6, the baseboard management controller chip U4 is connected to the host computer U1 and the memory U9; the host computer U1 and the internal processor U7 respectively read and write the memory U9 through the bus U6; the reset isolation method includes: step S1: when the host computer or the internal processor reads and writes the memory, first add the read and write data to the cache, and then send the read and write data through the cache; step S2: monitor the host computer or the internal processor, and when the host computer or the internal processor triggers a reset operation, turn to step S3; step S3: maintain the read and write operations based on the cache, and isolate the memory reset instruction output by the host computer or the internal processor that is being reset to the memory.

[0024] Specifically, in view of the problem that the memory data is lost and the transmission is interrupted when the server baseboard management controller chip in the prior art performs a reset operation, in this embodiment, a caching mechanism is introduced on one side of the bus. By caching the read and write data of the host computer and the internal processor, the continuous data transmission during the reset process is maintained. At the same time, the reset host computer or internal processor is isolated to avoid the loss of memory data during the reset process, which affects the normal operation of the internal processor or host computer on the other side.

[0025] Specifically, Figure 2 FIG. shows a system architecture of a typical server baseboard management controller chip. In this system, an internal processor U7 is built in the server baseboard management controller chip U4; this internal processor U7 is usually a central processing unit, which is used to run a specific operating system of the baseboard management controller chip U4, and is mainly used to implement the monitoring of various system resources in the server, that is, the host computer U1, as well as the triggering of timed tasks, data display and other functions.

[0026] The internal processor U7 is connected to the DDR controller U8 through the built-in bus U6 in the server baseboard management controller chip U4, and this DDR controller U8 is used to control external devices of the DDR protocol, such as the memory U9.

[0027] Some data corresponding to the server baseboard management controller chip U4 is stored in the memory U9, such as the data corresponding to the working state of the server collected through relevant software, etc. The server baseboard management controller chip U4 performs read and write operations on the data in the memory U9 through the bus U6, the DDR controller U8, and the channel to the memory U9.

[0028] A display controller U5 is also built in the server baseboard management controller chip U4, which is used to provide display for the host computer U1, such as monitoring data display. The host computer U1, as the server, needs to access the server baseboard management controller chip U4, usually based on the PCIe bus.

[0029] Specifically, the host computer U1 first accesses the PCIe host U2 through the PCIe bus, and then the PCIe host U2 interacts with the PCIe slave U3 in the server baseboard management controller chip U4 to build a data channel, so that the host computer U1 can access the display controller U5 through the PCIe slave U3 and perform read and write operations on the video memory data.

[0030] Among them, the video memory data is stored in the memory U9, and the display controller U5 connects to the DDR controller U8 through the bus U6 according to the read and write requirements of the host computer U1, so as to perform read and write operations on the data in the memory U9 through the bus U6, the DDR controller U8, and the channel to the memory U9.

[0031] Under normal circumstances, the host computer U1 and the internal processor U7 will work together to perform read and write operations on data. The memory U9 will store data on both sides simultaneously and perform parallel read and write operations.

[0032] When the host computer U1 or the internal processor U7 performs a reset operation, for a single-sided branch, usually the host computer U1 or the internal processor U7 performs a reset and issues a memory reset instruction. The memory reset instruction is sent to the DDR controller U8 via the bus U6, and the DDR controller U8 performs a memory reset operation on the memory U9.

[0033] However, when the host computers U1 and the internal processors U7 on both sides perform parallel operations, it is easy to see that when the DDR controller U8 performs a memory reset operation on the memory U9, the memory reset action may cause other data stored in the memory U9, that is, the data that the host computer U1 or the internal processor U7 on the other side is about to read and write, to be lost. If the memory is not reset, it will cause the data read and write operations performed by the original host computer U1 or internal processor U7 that is being reset to be interrupted.

[0034] To address the above problems, the technical means adopted in this solution include, as Figure 3 shown, on one side of the bus U6, mainly between the display controller U5 and the bus U6, and between the internal processor U7 and the bus U6, a virtual logic controller is introduced. The virtual logic controller is used to provide virtualized read and write operation logics for the display controller U5 and the internal processor U7.

[0035] Specifically, it will be embodied as a combination of a cache and a monitor. The monitor is used to listen to the read and write operations issued by the display controller U5 and the internal processor U7, and forward the same read and write operations and read and write data to the bus U6. Subsequently, the interaction logic between the bus U6, the DDR controller U8, and the memory is the same as when the virtual logic controller is not added.

[0036] However, when the memory U9 returns the corresponding read and write data through the bus U6, this part of the read and write data will be added to a cache in the virtual logic controller and then forwarded to the display controller U5 and the internal processor U7 for subsequent operations.

[0037] In addition, when the host computer U1 and the internal processor U7 trigger the corresponding reset operation and issue a memory reset instruction, after the virtual logic controller monitors it, the instruction will be isolated by the virtual logic controller and provide the corresponding process for the virtualized memory reset operation, but will not be actually forwarded to the bus U6.

[0038] Through this step, effective isolation of the branch being reset can be achieved, avoiding the problem of resetting the memory U9 and affecting the read and write operations on the other side, ensuring that data transmission is not interrupted during the reset process and the system can operate stably.

[0039] Based on the above architectural adjustments, during actual control, when the host computer or the internal processor reads and writes to the memory, the read and write data is first added to the cache, and then the read and write data is sent via the cache. This step is performed in parallel on the host computers or internal processors on both sides.

[0040] At the same time, monitor the host computer or the internal processor and determine whether a reset operation is triggered. This step does not affect the corresponding read and write operations. Only when a reset operation is triggered, isolate the memory reset instruction output by the host computer or the internal processor being reset to the memory, and at the same time continue to maintain the corresponding read and write operations based on the cache.

[0041] In one embodiment, as Figure 4 shown, step S1 includes: step S11: Read and discriminate the operation instructions input to the bus of the host computer or the internal processor. When it is determined to be a read / write instruction, proceed to step S12; step S12: When the read / write instruction is a read operation, obtain the read data from the memory and write it into the cache, and when the read / write instruction is a write operation, write the write data into the cache in sequence; step S13: From the cache, sequentially transmit the read data to the host computer or the internal processor in the read / write order, or write the write data into the memory in the read / write order.

[0042] Specifically, to achieve the replacement of the original operation logic, in this embodiment, first read and discriminate the operation instructions input to the bus of the host computer or the internal processor. When it is determined to be a read / write instruction, further discriminate this instruction to determine whether it is a read instruction or a write instruction.

[0043] When the read / write instruction is a read operation, obtain the read data from the memory and write it into the cache. During the reading process, first obtain the data at the corresponding address in the memory through the DDR controller and the bus. For each group of data entries, store them in the cache in sequence and establish the corresponding cache index. Then, sequentially send the data in the cache to the display controller of the corresponding host computer or the internal processor in the first-in-first-out order.

[0044] When the read / write instruction is a write operation, obtain the write data from the display controller of the host computer or the internal processor and write it into the cache. During the writing process, for each group of data entries, store them in the cache in sequence and establish the corresponding cache index. Then, sequentially forward the data in the cache to the DDR controller via the bus and then write it to the memory.

[0045] It should be noted that the above-mentioned execution entity is executed through a virtual logic controller. When the host computer and the internal processor perform read and write operations simultaneously, the virtual logic controllers on both sides are used to perform independent parallel operations respectively.

[0046] In one embodiment, when performing step S12, a monitor is also created. The monitor is used to monitor the internal processor or the host computer in step S2.

[0047] Specifically, to effectively monitor the read and write operations of the internal processor or the host computer, in this embodiment, each time the corresponding read and write operation is triggered, a monitor is configured for the read and write operation to monitor the internal processor or the host computer.

[0048] In one embodiment, in step S12, when executing a read and write instruction, a corresponding cache index is constructed for the read data or the write data; in step S13, a first-in-first-out operation is performed according to the cache index.

[0049] Specifically, to achieve better control of the read and write process, in this embodiment, for each triggered read and write instruction, a corresponding cache index is constructed for the read data or the write data respectively. The cache index is created according to the entries of the data and is refreshed in real time according to the data sent out by the cache. Then, when the cache sends out data, a first-in-first-out operation is performed according to the cache index.

[0050] When the read and write instruction is a read operation, the read data is obtained from the memory and written into the cache. During the reading process, first, the data at the corresponding address in the memory is obtained through the DDR controller and the bus. For each group of data entries, they are sequentially stored in the cache, and a corresponding cache index is established. Then, the data in the cache is sequentially sent to the display controller of the corresponding host computer or the internal processor in the order of first-in-first-out.

[0051] When the read and write instruction is a write operation, the write data is obtained from the display controller of the host computer or the internal processor and written into the cache. During the writing process, for each group of data entries, they are sequentially stored in the cache, and a corresponding cache index is established. Then, the data in the cache is sequentially forwarded to the DDR controller through the bus and then written into the memory.

[0052] In one embodiment, step S2 includes: collecting the operation instructions sent by the internal processor or the host computer to the bus through the monitor, and determining whether a reset operation occurs.

[0053] Specifically, to effectively monitor the read and write operations of the internal processor or the host computer, in this embodiment, each time a corresponding read or write operation is triggered, a monitor is first configured for the read or write operation. This monitor is used to monitor the instructions sent by the internal processor or the host computer, and first discriminates the corresponding instructions to determine whether a reset operation has occurred. If so, the instructions are isolated.

[0054] In one embodiment, as Figure 5 shown, step S3 includes: step S31: Isolate the memory reset instruction and determine whether the currently executed operation is a read operation; if so, proceed to step S32; if not, proceed to step S33; step S32: After waiting for the host computer or the internal processor to complete the reset, continue to send read data to the host computer or the internal processor in the read-write order; step S33: Continue to send write data to the memory in the read-write order, and continue to write to the cache after the host computer or the internal processor completes the reset.

[0055] Specifically, to avoid data loss in the memory caused by the reset operation, in this embodiment, when a memory reset instruction is detected, the memory reset instruction is first isolated, and then it is determined whether the currently executing operation is a read operation or a write operation.

[0056] For the read operation, since the corresponding data content has been previously read from the memory and stored in the cache, at this time, this part of the data is retained in the cache, and the corresponding read data is continuously sent from the memory to the cache until the DDR controller finishes sending.

[0057] Then, after waiting for the host computer or the internal processor to complete the reset, continue to send read data to the host computer or the internal processor in the read-write order, and at the same time, then process the remaining data in the memory according to the relevant requirements of the reset, so as to complete the data transmission process.

[0058] For the write operation, since the data to be sent by the host computer or the internal processor has been written into the cache, after the cache isolates the host computer or the internal processor, it continues to write to the DDR controller in turn according to the data entries inside the cache, thus completing the memory write operation.

[0059] If there is still data that has not been written before the reset, continue to write to the cache after the host computer or the internal processor completes the reset, and continue the subsequent process of writing to the memory.

[0060] In one embodiment, before executing step S32 or step S33, it further includes: step A31: In the cache, perform an operation mark on each piece of data for the read or write operation, and start a read-write timer during each transmission operation; step A32: When the read-write timer times out, it is considered that the host computer or the internal processor is in the reset state.

[0061] Specifically, to achieve better transmission continuity, in this embodiment, when an isolation operation is triggered and the process enters the read / write operation relying on the cache, an operation tag is respectively set for each piece of data in the read / write operation, and a read / write timer is started during each transmission operation.

[0062] The operation tag is used to record the corresponding node where the current read / write operation is executed, and the read / write timer is used to determine whether the read / write operation is abnormal.

[0063] When the read / write timer times out, it indicates that the read / write operation is abnormal, which is usually caused by an interruption due to a reset operation.

[0064] Then, in the execution of step S32 or step S33, the interruption point is determined according to the operation tag, and the read / write data is resent to implement the process of resuming data transmission from the breakpoint.

[0065] In one embodiment, during the execution of step S3, it further includes: step A4: when a read / write instruction is issued by the internal processor or the host computer on the other side, the bus operates on the memory and obtains the read / write data.

[0066] Specifically, based on the above settings, since the read / write operations of the host computer and the internal processor are isolated by the virtual logic controller, a better parallel processing effect can be achieved. When the host computer or the internal processor on one side is being reset, if a read / write instruction is issued by the internal processor or the host computer on the other side, the bus can still operate on the memory and obtain the read / write data, and maintain the data without loss.

[0067] A memory includes computer instructions, and when a computer device runs the computer instructions, the above reset isolation method is executed.

[0068] Those of ordinary skill in the art will understand that various aspects of the present invention, or possible implementations of various aspects, can be specifically implemented as a system, a method, or a computer program product. Therefore, various aspects of the present invention, or possible implementations of various aspects, can take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, etc.), or a form combining software and hardware embodiments, which are all collectively referred to as "circuits", "modules", or "systems" here. In addition, various aspects of the present invention, or possible implementations of various aspects, can take the form of a computer program product, which refers to computer instructions stored in a memory.

[0069] The memory can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium includes but is not limited to electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or apparatuses, or any suitable combination of the foregoing, such as random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable read-only memory (CD-ROM).

[0070] The processor in the computer reads the computer instructions stored in the memory, enabling the processor to perform the functional actions specified in each step or combination of steps in the flowchart; generating a device for performing the functional actions specified in each block or combination of blocks in the block diagram.

[0071] It should be understood that the processor in the computer can be understood as being implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components for executing the aforementioned computer instructions.

[0072] The computer instructions can be executed entirely on the user's local computer, partially on the user's local computer, as a separate software package, partially on the user's local computer and partially on a remote computer, or entirely on a remote computer or server. It should also be noted that in certain alternative embodiments, the functions noted in each step in the flowchart or each block in the block diagram may not occur in the order noted in the figure. For example, depending on the functions involved, two consecutive steps or two blocks shown may actually be executed approximately simultaneously, or these blocks may sometimes be executed in the reverse order.

[0073] Of course, in actual applications, the various components in the computer system are coupled together through a bus system. It can be understood that the bus system is used to achieve connection and communication between these components. In addition to the data bus, the bus system also includes a power bus, a control bus, and a status signal bus.

[0074] While the present application contains many specific implementation details, these should not be construed as limiting the scope of any disclosure or the scope of what is claimed, but rather are primarily used to describe the features of specific embodiments of a particular disclosure. Certain features described in multiple embodiments within the present application may also be implemented in combination in a single embodiment. On the other hand, the various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Additionally, although features may operate in certain combinations as described and even be initially claimed as such, one or more features from a claimed combination may in some cases be removed from that combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination.

[0075] Similarly, while configurations are depicted in a particular order in the drawings, this should not be construed as requiring that these configurations be performed or sequentially performed in the particular order shown, or that all illustrated configurations be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of various system modules and components in the described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0076] The above are only preferred embodiments of the present invention, and thus do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be able to realize that any equivalent replacements and obvious changes made by using the specification and illustrated content of the present invention should be included within the protection scope of the present invention.

Claims

1. A reset isolation method for a server baseboard management controller chip, wherein the baseboard management controller chip includes an internal processor and a bus, and the baseboard management controller chip is connected to a host computer and a memory; the host computer and the internal processor read and write the memory through the bus respectively; characterized in that: The reset isolation method includes: step S1: when the host computer or the internal processor reads and writes the memory, the read and write data are first added to the cache, and then the read and write data are sent through the cache; step S2: monitoring the host computer or the internal processor, and turning to step S3 when the host computer or the internal processor triggers a reset operation; step S3: maintaining the read and write operations based on the cache, and isolating the memory reset instructions output to the memory by the host computer or the internal processor that is being reset.

2. The reset isolation method according to claim 1, characterized in that: The step S1 includes: step S11: reading and identifying the operation instructions input into the bus by the host computer or the internal processor, and turning to step S12 when it is determined to be a read-write instruction; step S12: when the read-write instruction is a read operation, obtaining read data from the memory and writing it into the cache, and, when the read-write instruction is a write operation, writing the write data into the cache in sequence; step S13: transmitting the read data from the cache to the host computer or the internal processor in sequence according to the read-write order, or, writing the write data into the memory in sequence according to the read-write order.

3. The reset isolation method according to claim 2, characterized in that: When executing the step S12, a monitor is also created, and the monitor is used to monitor the internal processor or the host computer in the step S2.

4. The reset isolation method according to claim 2, characterized in that: In the step S12, when the read / write instruction is executed, a corresponding cache index is constructed for the read data or the write data; in the step S13, a first-in-first-out operation is performed according to the cache index.

5. The reset isolation method according to claim 3, characterized in that: The step S2 includes: collecting, by the monitor, operation instructions issued by the internal processor or the host computer to the bus, and determining whether a reset operation occurs.

6. The reset isolation method according to claim 2, characterized in that: The step S3 includes: step S31: isolating the memory reset instruction and determining whether the currently executed operation is a read operation; if so, going to step S32; if not, going to step S33; step S32: waiting for the host computer or the internal processor to be reset, and continuing to send the read data to the host computer or the internal processor in accordance with the read-write sequence; step S33: continuing to send the write data to the memory in accordance with the read-write sequence, and continuing to write to the cache after the host computer or the internal processor is reset.

7. The reset isolation method according to claim 6, characterized in that: Before executing step S32 or step S33, the method also includes: step A31: in the cache, marking each data of the read and write operations respectively, and starting the read and write timer at each transmission operation; step A32: when the read and write timer times out, it is considered that the host computer or the internal processor is being reset.

8. The reset isolation method according to claim 7, characterized in that: In executing the step S32 or the step S33, the interruption point is determined according to the operation mark, and the read / write data is resent.

9. The reset isolation method according to claim 1, characterized in that: The process of executing the step S3 also includes: step A4: when the internal processor on the other side or the host computer issues a read / write instruction, the bus operates the memory and obtains the read / write data.

10. A memory comprising computer instructions, characterized in that: When the computer device runs the computer instructions, the reset isolation method according to any one of claims 1 to 9 is executed.

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