Memory device test system

Abstract

A memory device test system comprises a memory device, a test machine, a mainboard and an interface. The tester generates a first control signal corresponding to a test performed on the memory device. The mainboard is coupled to the test machine and generates a second control signal to the memory device in response to the first control signal. The interface is coupled to the test machine, the mainboard and the memory device, and transmits a power signal from the test machine to the memory device via the first conductive path or transmits a power signal from the mainboard to the memory device via the second conductive path in response to a switching signal received from the test machine. The memory device generates an output signal corresponding to the test to the test machine in response to the power supply signal and the second control signal. According to the memory device test system provided by the invention, the intermediary device is provided between the mainboard and the memory device to be tested, and the effect of simplifying the test process of the mainboard needing to be modified is achieved.

Description

Technical Field

[0001] The present disclosure relates to a memory device testing system and a memory device testing method. Specifically, the present disclosure relates to a memory device testing system that provides an interface for additional test signals from an external device. Background Art

[0002] The performance and characteristics of memory devices under various conditions are necessary, and memory devices need to withstand different types of tests. To input specific types of test signals, the circuit between the memory device and the motherboard carrying the memory device needs to be modified. These modification methods include component replacement, such as compensating for inductance, capacitance, or variable resistance in the circuit. However, the form of commercial motherboards is fixed, and any modification will inevitably cause damage to the motherboard. Summary of the Invention

[0003] The present disclosure provides a memory device testing system, including a memory device, a tester, a motherboard, and an intermediary device. The tester generates a first control signal, and the first control signal corresponds to a test to be executed on the memory device. The motherboard is coupled to the tester and is configured to generate a second control signal to the memory device in response to the first control signal. The interface is coupled to the tester, the motherboard, and the memory device, and in response to a switch signal received from the tester, transmits a power signal from the tester to the memory device via a first conduction path, or transmits a power signal from the motherboard to the memory device via a second conduction path, wherein the memory device is configured to generate an output signal corresponding to the test to the tester in response to the power signal and the second control signal.

[0004] In some embodiments, the tester includes a power supply device configured to generate a power signal.

[0005] In some embodiments, the interface includes a first conductive section, a second conductive section, and a connection device. The first conductive section is coupled to the motherboard. The second conductive section is coupled to the memory device. The connection device is disposed between the first conductive section and the second conductive section and electrically connects the first conductive section and the second conductive section in response to the switch signal.

[0006] In some embodiments, the interface further includes a first conducting wire and a second conducting wire. The first conducting wire is coupled between the first conductive section and the motherboard and extends along the X direction in the first layer of the interface. The second conducting wire is coupled between the memory device and the second conductive section and extends along the X direction in the second layer of the interface. The first layer of the interface is located below the second layer of the interface.

[0007] In some embodiments, the connection device includes a switch. The switch conducts in response to the switch signal to turn on the second conduction path.

[0008] In some embodiments, the connection device is turned on to form a second conductive path, and the first conductive section, the second conductive section, and the connection device are included in the second conductive path. The connection device is turned off to form a first conductive path, and the second conductive section is included in the first conductive path.

[0009] In some embodiments, the memory device test system includes an extension card disposed between the motherboard and the interface.

[0010] In some embodiments, the extension card includes a conductive section and a conductive wire. The conductive section is located on the surface of the extension card. The conductive wire is coupled between the conductive section and the motherboard.

[0011] In some embodiments, the memory device transmits an output signal corresponding to the test through the motherboard.

[0012] The present disclosure provides another memory device test system, including a memory device, a tester, and an intermediary device. The tester generates a first control signal, a first power signal, and a switch signal. The first power signal corresponds to a test performed on the memory device. The intermediary device is coupled between the memory device and the tester, generates a second control signal and a second power signal in response to the first control signal, and the intermediary device also transmits the first power signal or the second power signal to the memory device in response to the switch signal. The memory device generates an output signal corresponding to the test to the tester in response to the first power signal, the second control signal, and the second power signal.

[0013] In some embodiments, the intermediary device includes a first conductive section, a second conductive section, a connection device, and a motherboard. The connection device is coupled between the first conductive section and the second conductive section. The motherboard is coupled to the first conductive section.

[0014] In some embodiments, the first conductive section, the second conductive section, and the connection device are included in a first conductive path coupled to the memory device, and the second conductive section is included in a second conductive path coupled to the memory device.

[0015] In some embodiments, the connection device is turned on in response to the switch signal to form a first conductive path for transmitting the second power signal.

[0016] In some embodiments, the connection device is turned off in response to the switch signal to form a second conductive path for transmitting the first power signal.

[0017] In some embodiments, the first control signal, the second control signal, and the output signal are transmitted through the motherboard. Description of the Drawings

[0018] As will be best understood in conjunction with the accompanying drawings, aspects of the present case will be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0019] Figure 1 FIG. is a schematic diagram of a memory device test system in some embodiments.

[0020] Figure 2 In some embodiments, Figure 1 FIG. is an architectural diagram of a partial area of a memory device test system.

[0021] Figure 3 In other embodiments, Figure 1 FIG. is an architectural diagram of a partial area of a memory device test system.

[0022] Figure 4 In other embodiments, Figure 1 FIG. is an architectural diagram of a partial area of a memory device test system.

[0023] Figure 5 In still other embodiments, Figure 1 FIG. is an architectural diagram of a partial area of a memory device test system. DETAILED DESCRIPTION

[0024] Numerous different embodiments or examples are provided below for implementing different features of the provided subject matter. To simplify an embodiment of the present disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, an embodiment of the present disclosure may repeat reference numerals and / or letters in the various examples. For the sake of brevity and clarity, the repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0025] The terms used throughout the specification and claims, unless otherwise specified, generally have the ordinary meaning of each term as used in this field, in the context of the present disclosure, and in the specific context. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in connection with the description of the present disclosure.

[0026] Generally speaking, the terms "comprising" and "including" only imply the inclusion of the steps and elements that are explicitly identified, and these steps and elements do not constitute an exclusive listing. A method or device may also include other steps or elements.

[0027] References throughout this specification to "one embodiment", "an embodiment", or "some embodiments" mean that a particular feature, structure, implementation, or characteristic described in connection with that (or those) embodiment(s) is included in at least one embodiment of the present case. Thus, the phrases "in one embodiment", "in an embodiment", or "in some embodiments" used throughout this specification do not necessarily all refer to the same embodiment. Further, in one or more embodiments, the particular features, structures, implementations, or characteristics may be combined in any suitable manner.

[0028] Furthermore, for ease of description, spatial relative terms such as "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. Such spatial relative terms are intended to encompass different orientations of the device during use or operation as well as the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0029] As used herein, "about", "approximately", "substantially", or "essentially" shall generally refer to any approximation of a given value or range, which varies depending on the various technologies to which it pertains, and the scope thereof shall be consistent with the broadest interpretation understood by those skilled in the art to which it pertains, so as to cover all such modifications and similar constructs. In some embodiments, it shall generally mean within 20% of the given value or range, preferably within 10%, and more preferably within 5%. The numerical quantities given herein are approximate, meaning that the terms "about", "approximately", "substantially", or "essentially" may be inferred if not explicitly stated, or mean other approximations.

[0030] Please refer to Figure 1 。 Figure 1 FIG. is a schematic diagram of a memory device test system 10 in some embodiments. In Figure 1 , the memory device test system 10 includes a tester 110, an intermediary device 115, and a memory device 140. The tester 110 is electrically coupled to the intermediary device 115, and the intermediary device 115 is electrically coupled to the memory device 140. The intermediary device 115 includes a motherboard 120 and an interface 130. The motherboard 120 and the interface 130 are electrically coupled to each other.

[0031] In some embodiments, the motherboard 120 may be implemented as a motherboard including an integrated circuit for power management.

[0032] In some embodiments, the memory device 140 may be implemented as any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), or similar components, or a combination of the above components.

[0033] In some embodiments, the tester 110 generates a control signal CS1, which corresponds to performing a test on the memory device. The tester 110 also transmits the control signal CS1 to the motherboard 120 via the conductive path P0. The motherboard 120 also generates a control signal CS2 in response to the control signal CS1 and transmits it to the memory device 140 via the conductive path P0 to perform a test on the memory device 140. For example, the test includes read and write operations or other operations that test the functions and performance of the memory device 140.

[0034] After the test, the memory device 140 transmits an output signal OUT corresponding to this test to the tester 110 via the motherboard 120 in response to the control signal CS2.

[0035] The tester 110 also generates a test result of the memory device 140 based on the output signal OUT from the memory device 140.

[0036] For example, when the output signal OUT from the memory device 140 does not match the expected result of the performed test, the tester 110 generates a test result indicating that the memory device 140 fails to perform the operation. In some embodiments, in this case, the memory device 140 will be removed for repair. On the contrary, when the output signal OUT matches the expected result, the test result indicates that the memory device 140 meets the specifications.

[0037] In some embodiments, during the test, the supply voltage for operating the memory device 140 is provided via the interface 130, and the interface 130 is coupled to a power supply device 111 in the motherboard 120 or the tester 110. As shown, the tester 110 includes a power supply device 111. The motherboard 120 includes a PMIC 121 (Power Management IC, PMIC). The interface 130 includes endpoints N1, N2, and a connection device 131 coupled between the endpoints N1 and N2. In some embodiments, the connection device 131 includes a switch 132, one end of which is coupled to the endpoint N1 and the other end of which is coupled to the endpoint N2.

[0038] In an embodiment where the memory device 140 obtains a supply voltage via the motherboard 120, the motherboard 120 controls the PMIC 121 to generate a power signal PS1 sent to the memory device 140 according to a control signal CS1. The power signal PS1 is transmitted in a conduction path P2 formed by an endpoint N1, a connection device 131, and an endpoint N2. The tester 110 generates a switching signal SCS to the interface 130 to turn on a switch 132 in the connection device 131. Accordingly, the endpoint N1 is electrically coupled to the endpoint N2, and the power signal PS1 is transmitted to the memory device 140 via the interface 130 to operate the memory device 140 during testing. In some embodiments, the power signal PS1 has a supply voltage VDD (for example, VDD can be 1.9 volts). After testing, in response to the power signal PS1, the memory device 140 transmits an output signal OUT corresponding to this test to the tester 110 via the motherboard 120. Then, the tester 110 generates a test result of the memory device 140 according to the output signal OUT from the memory device 140.

[0039] The test result of the memory device 140 corresponds to the functions and performance shown by the memory device 140 under the operation indicated by the power signal PS1 from the PMIC 121. For example, when the output signal OUT of the memory device 140 does not match the expected result of the executed test, the tester 110 generates a test result indicating that the memory device 140 fails to operate under the conditions (such as the supply voltage VDD). Then, the memory device 140 will be taken out for adjustment. When the output signal OUT matches the expected result, the test result indicates that the memory device 140 meets the specifications.

[0040] In some embodiments where the memory device 140 obtains a supply voltage via a power supply device 111, the tester 110 generates a switching signal SCS to turn off the switch 132 in the interface 130. After the switch 132 is turned off, the power supply device 111 in the tester 110 generates and transmits a power signal PS2 to the memory device 140 via the interface 130. Specifically, the power signal PS2 is transmitted via Figure 1 the conduction path P1 in, which passes through the endpoint N2 on the interface 130.

[0041] The power supply device 111 of the testing machine 110 generates a power signal PS2 to simulate noises (such as voltage surges or voltage ripples) that may occur in electronic components or provide specific voltage values that the PMIC 121 cannot generate. The stability of the memory device 140 is directly tested by the power signal PS2. After the test, the memory device 140 transmits an output signal OUT corresponding to the test to the testing machine 110 via the main board 120 in response to the power signal PS2. Then, the testing machine 110 generates a test result of the memory device 140 based on the output signal OUT from the memory device 140.

[0042] The test result of the memory device 140 corresponds to the stability of the memory device 140 under the operation indicated by the power signal PS2 directly from the power supply device 111. For example, when the output signal OUT from the memory device 140 does not match the expected result of the executed test, the testing machine 110 generates an indication that the memory device 140 fails to operate under this condition (e.g., voltage surge or voltage ripple). Then the memory device 140 will be taken out for improvement. When the output signal OUT matches the expected result, the testing machine 110 generates a test result indicating that the memory device 140 meets the specifications.

[0043] In some methods, the testing method of the memory device involves modifying the circuit on the motherboard. For example, the operator must modify the circuit by cutting off the original circuit path (such as replacing components in the circuit) to provide additional test signals (e.g., signals generated to simulate surge or ripple voltages). In such an arrangement, additional workload is required for modification, and the risk of circuit damage may increase significantly. With the arrangement disclosed herein, the foregoing problems can be addressed using the paths provided by the interface. Ultimately, the operator can input various test signals to the memory device via the paths in the interface without worrying about damaging the circuit.

[0044] Please refer to Figure 2 。 Figure 2 In some embodiments, Figure 1 is an architectural diagram of a partial area of the memory device testing system 10.

[0045] In Figure 2 the main board 120, the PMIC 121, the interface 130, and the memory device 140 are coupled to each other through (metal) solder joints 135. In some Figure 2 embodiments, an extension card 125 is placed between the interface 130 and the main board 120 and is included in Figure 1In the intermediate device 115, it is to provide elasticity for adjusting the structural arrangement of the intermediate device 115. The PMIC 121 is disposed on the motherboard 120. The extension card 125, the interface 130, and the memory device 140 are arranged in the Z direction. The extension card 125 is disposed on the motherboard 120, the interface 130 is disposed on the extension card 125, and the memory device 140 is disposed on the interface 130. The PMIC 121 and the stack formed by the extension card 125, the interface 130, and the memory device 140 are separated from each other by a distance in the X direction.

[0046] Please refer to Figure 2 . In some Figure 2 embodiments, the interface 130 includes conductive lines 210, conductive lines 212, and conductive vias 220. The conductive lines 210 and the conductive lines 212 are in different layers, and these two layers extend in the X direction. The conductive lines 212 are located above the conductive lines 210. The interface 130 includes conductive sections 230 and conductive sections 232, both of which are arranged on the surface of the interface 130. The conductive section 230 is electrically coupled to the conductive line 210 via the conductive via 220, and the conductive section 232 is electrically coupled to the conductive line 212. The connection device 240 is located on the surface of the interface 130 and is between the conductive sections 230 and 232.

[0047] The conductive sections 230 and 232 and the connection device 240 are arranged in the X direction and are located between the PMIC 121 and the stack formed by the extension card 125, the interface 130, and the memory device 140.

[0048] In some embodiments, the conductive section 230 and the conductive section 232 respectively correspond to Figure 1 the endpoints N1 and N2 in Figure 1 . The connection device 240 corresponds to Figure 2 the connection device 131 in

[0049] In some embodiments, the motherboard 120 transmits the control signal CS2 to the memory device 140 and receives the output signal OUT from the memory device 140 via the extension card 125, the solder joints 135, and the interface 130.

[0050] Figure 1The conductive path P0 for transmitting the control signals CS1 and CS2 via the main board 120 corresponds to Figure 2 the direct path DP in (the test machine 110 is not shown in Figure 2 it).

[0051] In the operation of transmitting the power signal PS1 from the PMIC 121 to the memory device 140, the connection device 240 is turned on in response to the switch signal SCS from the test machine 110, so that the conductive section 230 and the conductive section 232 are electrically connected. The connection relationship between the test machine 110 and the connection device 240 is omitted here. Accordingly, the PMIC 121 transmits the power signal PS1 to the memory device 140 via the conductive path P2, and the conductive path P2 includes the solder joint 135, the main board 120, the extension card 125, the conductive wire 210, the conductive via 220, the conductive section 230, the connection device 240, the conductive section 232, and the conductive wire 212.

[0052] In the operation of transmitting the power signal PS2 from the power supply device 111 to the memory device 140, the test machine 110 transmits the switch signal SCS to the connection device 240 to turn off the connection device 240. After the connection device 240 is turned off to electrically isolate the conductive section 232 from the conductive section 230, the power supply device 111 transmits the power signal PS2 to the memory device 140 via the conductive path P1, and the conductive path P1 includes the conductive section 232, the conductive wire 212, and the solder joint 135.

[0053] Please refer to Figure 3 , Figure 3 For, in some other embodiments, Figure 1 the architecture diagram of a partial area of the memory device test system 10.

[0054] According to Figure 2 the embodiments of, as Figure 3 the similar elements in are labeled with the same symbols for easy understanding. For simplicity, the specific operations of the similar elements that have been carefully discussed in the previous paragraphs will be omitted.

[0055] Compared with Figure 2 the embodiments of, the conductive sections 230 and 232 and the connection device 240 are arranged between the PMIC 121 and the memory device 140. In Figure 3 the embodiments of, the conductive sections 230 and 232 and the connection device 240 are arranged on the other side of the interface 130, which provides convenience for the connection between the test machine 110 and the interface 130.

[0056] Please refer to Figure 4 , Figure 4 For, in some other embodiments, Figure 1Architectural diagram of a partial area of the memory device test system 10. According to Figure 2 In the embodiment of Figure 4 Similar elements in

[0057] Figure 4 And Figure 1 The electrical relationship between Figure 2 And Figure 1 Is similar to the electrical relationship between

[0058] Compared with Figure 2 In the embodiment of Figure 4 In the embodiment of Figure 4 As shown, the conductive segments 230 and 232 and the connecting device 240 are arranged in the Z direction and are located between the PMIC 121 and the memory device 140. Specifically, the conductive segment 230 is located on the extension card 125, the conductive segment 232 is located on the interface 130, and the connecting device 240 is located between the extension card 125 and the interface 130.

[0059] Compared with Figure 2 In the embodiment of Figure 4 In the embodiment of

[0060] Please refer to Figure 5 Figure 5 For some other embodiments, Figure 1 Architectural diagram of a partial area of the memory device test system 10. According to Figure 2 In the embodiment of Figure 5 Similar elements in

[0061] Figure 5 And Figure 1 The electrical relationship between Figure 2 And Figure 1 Is similar to the electrical relationship between

[0062] Compared with Figure 4In an embodiment, the conductive segments 230, 232, and the connection device 240 are arranged between the PMIC 121 and the memory device 140. In Figure 5 In an embodiment, the conductive segments 230, 232, and the connection device 240 are arranged on the other side. Specifically, the conductive segment 230 is on the other side of the extension card 125, and the conductive segment 232 is on the other side of the interface 130.

[0063] In summary, the memory device test system in this disclosure provides an intermediary device between the motherboard and the memory device to be tested. Through the above arrangement, additional test signals or test signals that cannot be generated by the PMIC can be input from an external tester via the intermediary device. The arrangement in this disclosure can simplify the test process that requires modifying the motherboard.

[0064] The foregoing outlines the features of several embodiments so that those skilled in the art can better understand aspects of this disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and alterations can be made by those skilled in the art without departing from the spirit and scope of this disclosure.

[0065]

Symbol Description

[0066] 10: Memory device test system

[0067] 110: Tester

[0068] 111: Power supply device

[0069] 115: Intermediary device

[0070] 120: Motherboard

[0071] 121: PMIC

[0072] 125: Extension card

[0073] 130: Interface

[0074] 131: Connection device

[0075] 132: Switch

[0076] 135: Solder joint

[0077] 140: Memory device

[0078] 210, 212: Conductive wires

[0079] 220: Conductive via hole

[0080] 230, 232: Conductive section

[0081] 240: Connecting device

[0082] CS1, CS2: Control signal

[0083] DP: Direct path

[0084] N1, N2: Endpoint

[0085] OUT: Output signal

[0086] P0, P1, P2: Conductive path

[0087] PS1, PS2: Power supply signal

[0088] SCS: Switching signal

[0089] X, Z: Direction.

Claims

1. A memory device testing system, characterized in that: include: Memory device; A tester, configured to generate a first control signal, wherein the first control signal corresponds to a test performed on the memory device; A mainboard coupled to the tester and used to generate a second control signal to the memory device in response to the first control signal; as well as An interface is provided to couple the test machine, the motherboard and the memory device, and is used to transmit a power signal from the test machine to the memory device via a first conductive path in response to a switch signal received from the test machine, or to transmit the power signal from the motherboard to the memory device via a second conductive path, wherein the memory device is used to generate an output signal corresponding to the test to the test machine in response to the power signal and the second control signal.

2. The memory device testing system according to claim 1, wherein: The test machine includes: The power supply device is used to generate the power signal.

3. The memory device testing system according to claim 1, wherein: The interface includes: A first conductive section coupled to the main board; A second conductive segment coupled to the memory device; as well as The connecting device is disposed between the first conductive segment and the second conductive segment and electrically connects the first conductive segment and the second conductive segment in response to the switch signal.

4. The memory device testing system according to claim 3, wherein: The interface also includes: A first conductive line coupled between the first conductive segment and the main board and extending along the X direction in the first layer of the interface; as well as A second conductive line is coupled between the memory device and the second conductive segment and extends along the X direction in the second layer of the interface, wherein the first layer of the interface is located below the second layer of the interface.

5. The memory device testing system according to claim 3, wherein: The connecting device includes a switch, wherein the switch is configured to be turned on in response to the switch signal to open the second conductive path.

6. The memory device testing system according to claim 3, wherein: The connecting device is turned on to form the second conductive path, and the first conductive segment, the second conductive segment and the connecting device are included in the second conductive path, and the connecting device is turned off to form the first conductive path, and the second conductive segment is included in the first conductive path.

7. The memory device testing system according to claim 1, wherein: Also includes: The extension card is placed between the mainboard and the interface.

8. The memory device testing system according to claim 7, wherein: The extension card includes: a conductive segment located on a surface of the extension card; and The conductive wire is coupled between the conductive section and the main board.

9. The memory device testing system according to claim 1, wherein: The memory device is used to transmit the output signal corresponding to the test through the main board.

10. A memory device testing system, characterized in that: Include: Memory device; A tester, for generating a first control signal, a first power signal and a switch signal, wherein the first power signal corresponds to a test performed on the memory device; as well as An intermediary device, coupled between the memory device and the tester, for generating a second control signal and a second power signal in response to the first control signal, and for transmitting the first power signal or the second power signal to the memory device in response to the switch signal; The memory device is used for generating an output signal corresponding to the test to the tester in response to the first power signal, the second control signal and the second power signal.

11. The memory device testing system according to claim 10, wherein: The intermediary device includes: a first conductive segment; a second conductive segment; A connecting device coupled between the first conductive segment and the second conductive segment; and The main board is coupled to the first conductive section.

12. The memory device testing system according to claim 11, wherein: The first conductive segment, the second conductive segment and the connecting device are included in a first conductive path coupled to the memory device, and the second conductive segment is included in a second conductive path coupled to the memory device.

13. The memory device testing system according to claim 12, wherein: The connecting device is turned on in response to the switch signal to form the first conductive path to transmit the second power signal.

14. The memory device testing system according to claim 12, wherein: The connecting device is turned off in response to the switch signal to form the second conductive path to transmit the first power signal.

15. The memory device testing system according to claim 11, wherein: The first control signal, the second control signal and the output signal are transmitted via the main board.

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