Dynamic adjustable multi-core cooperation mechanism and power consumption optimization method and system based on risc-v architecture

Abstract

This invention relates to a dynamically adjustable multi-core collaboration mechanism and power optimization method and system based on the RISC-V architecture, including: 1) Initialization of the dynamically adjustable multi-core collaboration system; including: initializing hardware modules, which include high-performance P-cores, low-power E-cores, a hardware scheduling unit (HSU), and a power management unit (PMU); loading the task queue and marking task characteristics; 2) Core status monitoring; including: the HSU monitoring the core status; and the PMU monitoring voltage and frequency; 3) Dynamic task scheduling; including: allocating tasks to high-performance P-cores or low-power E-cores according to their characteristics; and having idle cores enter low-power mode; 4) Adaptive power saving and task migration. Through dynamic task scheduling and power-saving optimization algorithms, the flexibility and efficiency of the RISC-V multi-core processor are significantly improved.

Description

Technical Field

[0001] This invention relates to the field of multi-core processor technology, and in particular to a dynamic multi-core collaboration and power consumption optimization method based on the RISC-V architecture, specifically including a dynamically adjustable multi-core collaboration mechanism and its application in energy saving and efficient operation. Background Technology

[0002] With the increasing complexity of computing tasks and the continuous growth in demand for high performance and low power consumption, multi-core processor architecture has become a core technology of modern computing devices. Traditional multi-core architectures typically include high-performance cores (P-cores) and high-efficiency cores (E-cores), which work together to handle different workloads, achieving a balance between performance and power consumption. For example, ARM's big.LITTLE technology significantly improves system energy efficiency by dynamically allocating tasks to different cores. However, this technology typically relies on highly specialized instruction sets and hardware designs, making it difficult to flexibly migrate to other open architecture platforms.

[0003] Existing RISC-V multi-core processors lack mature solutions for task collaboration and power consumption optimization. Current multi-core designs in the RISC-V ecosystem are primarily based on Symmetric Multiprocessing (SMP), failing to fully utilize the potential of heterogeneous multi-core processors and lacking the flexibility to schedule tasks to adapt to diverse workloads. Furthermore, traditional RISC-V power optimization relies mainly on static frequency and voltage adjustments (such as DVFS), which are insufficiently responsive under dynamic load changes, resulting in low power efficiency. Moreover, the current RISC-V architecture's Hardware Scheduling Unit (HSU) and Power Management Unit (PMU) have limited functionality, unable to provide fine-grained monitoring and scheduling of multi-core states, and lacking a complete ecosystem standard.

[0004] Therefore, for the RISC-V architecture, using new methods to overcome the shortcomings of existing technologies and improve the performance and energy efficiency of RISC-V multi-core processors has become an urgent problem to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on the RISC-V architecture.

[0006] This invention proposes a dynamically adjustable multi-core collaboration mechanism based on the RISC-V architecture. By innovatively combining hardware monitoring, task scheduling algorithms, and power optimization strategies, and by extending the RISC-V control and status registers, it provides multi-core status monitoring, task load prediction, and dynamic task migration functions, achieving efficient collaboration between heterogeneous multi-cores. Simultaneously, by incorporating lightweight AI algorithms and Dynamic Frequency Voltage Scaling (DVFS) technology, it further optimizes core start-up and frequency control, improving the accuracy and real-time performance of power consumption control. A RISC-V-based hardware scheduling unit (HSU) and power management unit (PMU) are designed to provide real-time acquisition and analysis of core states, forming a complete hardware-software integrated solution.

[0007] Through the implementation of this invention, the RISC-V architecture will possess multi-core collaboration capabilities similar to ARM big.LITTLE technology. At the same time, thanks to its openness and scalability, it will demonstrate strong innovation and practicality in more scenarios (such as the Internet of Things, embedded devices, and high-performance computing).

[0008] This invention also proposes a dynamically adjustable multi-core collaboration mechanism and power optimization system based on the RISC-V architecture;

[0009] Terminology Explanation:

[0010] 1. HSU: The Hardware Scheduler Unit (HSU) is a dedicated hardware module integrated into the processor, responsible for managing task allocation and scheduling in a multi-core processor. The HSU is a crucial component for implementing dynamic multi-core collaboration mechanisms. The HSU can collect real-time data on the operating status of each core, including task execution, power consumption, and temperature. This data is obtained through extended Control and Status Registers (CSRs) and used as the basis for scheduling decisions. Simultaneously, the HSU can dynamically determine whether a task should be allocated to a performance core (P-core) or an energy-efficient core (E-core) based on task characteristics (such as computational intensity and real-time requirements) and the core's current state (such as load, power consumption, and temperature), achieving efficient task load balancing. The HSU works in conjunction with the Power Management Unit (PMU) to dynamically adjust the core's operating frequency, voltage, and start / stop status by analyzing core load trends and task requirements, optimizing the overall system energy efficiency.

[0011] 2. CSR: The Control and Status Register (CSR) is a set of dedicated registers within the processor used to store and manage information related to processor state, configuration, and control. The CSR primarily stores the running state of the processor cores, such as the currently executing task context and performance counter information. This state information provides the basis for task scheduling and system management. Simultaneously, the CSR can record the current core's task running state, such as register contents and the location of the program counter (PC). During task migration, the task context can be saved or restored by accessing the CSR, enabling seamless task switching. The CSR stores core performance counter data, such as the number of instructions executed and cache hit rate. This data helps the Hardware Scheduling Unit (HSU) analyze the current core load and provides a basis for task allocation. Extended CSRs can work in conjunction with the Power Management Unit (PMU) to record core power consumption and temperature information, and control frequency, voltage adjustment, and core start / stop operations through a software interface, achieving real-time power optimization.

[0012] The technical solution of the present invention is as follows:

[0013] Dynamically tunable multi-core collaboration mechanisms and power optimization methods based on RISC-V architecture include:

[0014] 1) Initialization of a dynamically adjustable multi-core cooperative system; including:

[0015] Initialize the hardware module, which includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU.

[0016] Load the task queue and mark task characteristics (priority, real-time requirements, etc.);

[0017] 2) Core status monitoring; including:

[0018] HSU monitors core status (load, power consumption, temperature);

[0019] The power management unit (PMU) monitors voltage and frequency;

[0020] 3) Dynamic task scheduling; including:

[0021] Based on task characteristics, tasks are assigned to either high-performance P-cores or low-power E-cores.

[0022] Idle cores enter low-power mode;

[0023] 4) Adaptive energy saving and task migration;

[0024] Adaptive power saving; including: predicting changes in task load; pre-starting or shutting down the core;

[0025] Task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency.

[0026] Return to step 2) and continue monitoring.

[0027] According to a preferred embodiment of the present invention, the hardware module is initialized using RISC-V boot and interrupt control instructions.

[0028] According to a preferred embodiment of the present invention, loading a task queue and marking task characteristics includes:

[0029] Analyze the current task queue to determine the task priority, load type, and real-time requirements, and store the task characteristics in the task scheduling table.

[0030] According to a preferred embodiment of the present invention, the HSU monitors the core status, which includes load, power consumption, and temperature.

[0031] The PMU periodically collects core status data;

[0032] A step-by-step threshold triggering mechanism is adopted, including:

[0033] When any of the load, power consumption, or temperature indicators exceeds 80% of the threshold for load, power consumption, or temperature, a single indicator warning is issued, and the core status is recorded.

[0034] When two or more metrics exceed the threshold simultaneously, dynamic task scheduling is immediately triggered to migrate tasks or start / stop the core.

[0035] When two or more metrics remain in a low-occupancy state for an extended period, the scheduler will reallocate multiple processor tasks and shut down any excess idle processors.

[0036] According to a preferred embodiment of the present invention, dynamic task scheduling includes: a high-performance P-core or a low-power E-core.

[0037] Dynamic frequency adjustment is applied to the high-performance P-core and low-power E-core, setting independent frequency and voltage for each core. The frequency of the high-load core, i.e. the high-performance P-core, is increased, while the frequency and voltage of the low-load core, i.e. the low-power E-core, are decreased.

[0038] Based on task characteristics and core status, RISC-V scheduling extension instructions are used to implement task allocation; computationally intensive tasks are allocated to high-performance P-cores, lightweight or background tasks are allocated to low-power E-cores, and low-priority tasks are allocated to low-power E-cores or scheduled later.

[0039] Further optimized, the cores are dynamically started and stopped using RISC-V low-power extended instructions; when the load increases, more cores are woken up; when the load decreases, idle cores are shut down and switched to low-power mode.

[0040] According to a preferred embodiment of the present invention, adaptive energy saving includes:

[0041] Based on a lightweight AI model, future load changes are predicted using historical task data, and cores are started or shut down in advance to adapt to the predicted load changes.

[0042] If the current task queue is empty, shut down all high-performance P-cores and keep only one low-power E-core running in low-power mode.

[0043] According to a preferred embodiment of the present invention, task migration includes:

[0044] Task migration is triggered when one of the following conditions is met:

[0045] ① The current core temperature exceeds the set temperature threshold or the current core power consumption exceeds the set power consumption threshold;

[0046] ②The current core load remains either too high or too low;

[0047] ③ The task characteristics do not match the current core type;

[0048] During task migration, extended instructions are used to save the task state to shared memory, and then the task context is restored on the target core.

[0049] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program implementing steps of a dynamically adjustable multi-core collaboration mechanism and power optimization method based on a RISC-V architecture.

[0050] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a dynamically adjustable multi-core collaboration mechanism and power optimization method based on a RISC-V architecture.

[0051] A dynamically tunable multi-core collaboration mechanism and power optimization system based on RISC-V architecture, including:

[0052] The initialization module is configured as follows: dynamic adjustable multi-core collaborative system initialization; including: initializing the hardware module, which includes a high-performance P-core, a low-power E-core, a hardware scheduling unit (HSU), and a power management unit (PMU); loading the task queue and marking task characteristics.

[0053] The core status monitoring module is configured as follows: HSU monitors the core status; Power Management Unit (PMU) monitors voltage and frequency.

[0054] The dynamic task scheduling module is configured to: allocate tasks to high-performance P-cores or low-power E-cores based on task characteristics; idle cores enter low-power mode.

[0055] The adaptive power saving and task migration module is configured as follows: adaptive power saving includes: predicting task load changes; starting or stopping the core in advance; task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency.

[0056] The beneficial effects of this invention are as follows:

[0057] The core innovation of this invention lies in its hardware-software co-design, which significantly improves the flexibility and efficiency of RISC-V multi-core processors through dynamic task scheduling and energy-saving optimization algorithms. The benefits of this invention are multifaceted: it enables rapid response to high-performance tasks and efficient execution of low-power tasks through heterogeneous multi-core task allocation; it reduces energy consumption and extends device battery life through adaptive energy-saving mechanisms; and it enhances the functionality and ecosystem adaptability of the RISC-V architecture through expanded hardware modules and instruction sets, providing an innovative technical solution for embedded devices, the Internet of Things, edge computing, and high-performance computing. Attached Figure Description

[0058] Figure 1 This is a flowchart illustrating the dynamically adjustable multi-core collaboration mechanism and power optimization method based on the RISC-V architecture of this invention.

[0059] Figure 2 This is a schematic diagram illustrating the overall process of the dynamically adjustable multi-core collaboration mechanism and power optimization method based on the RISC-V architecture of this invention. Detailed Implementation

[0060] The present invention will be further defined below with reference to the accompanying drawings and embodiments, but is not limited thereto.

[0061] Example 1

[0062] Dynamically tunable multi-core collaboration mechanism and power optimization method based on RISC-V architecture, such as Figure 1 and Figure 2 As shown, it includes:

[0063] 1) Initialization of the dynamically adjustable multi-core collaborative system; the dynamically adjustable multi-core collaborative system includes a high-performance P-core, a low-power E-core, a hardware scheduling unit (HSU), and a power management unit (PMU); including:

[0064] Initialize the hardware module, which includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU.

[0065] Load the task queue and mark task characteristics (priority, real-time requirements, etc.);

[0066] 2) Core status monitoring; including:

[0067] HSU monitors core status (load, power consumption, temperature);

[0068] The power management unit (PMU) monitors voltage and frequency. Different processors require different voltages and frequencies in different modes. The PMU monitors the current voltage and frequency of each processor and compares it with the target voltage and frequency set by the power management unit (HSU) to achieve real-time monitoring of the processor status.

[0069] 3) Dynamic task scheduling; including:

[0070] Based on task characteristics, tasks are assigned to either high-performance P-cores or low-power E-cores.

[0071] Idle cores enter low-power mode;

[0072] 4) Adaptive energy saving and task migration;

[0073] Adaptive power saving; including: predicting changes in task load (lightweight AI module); pre-starting or shutting down the core;

[0074] Task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency.

[0075] Return to step 2) and continue monitoring.

[0076] Example 2

[0077] The difference between the dynamically adjustable multi-core collaboration mechanism and power optimization method based on RISC-V architecture described in Example 1 and the following is:

[0078] The hardware module is initialized using RISC-V boot and interrupt control instructions.

[0079] P-core stands for Performance Core: It supports high-frequency operation, large cache, and vector instruction set extensions (such as RVV), making it suitable for computationally intensive tasks.

[0080] The core is configured for high-performance mode using extended CSR registers. This mode allows the core to run at a higher frequency while activating all compute units. The initial operating frequency and voltage for the P-core are set via PMU and CSR extension instructions (maintained at a mid-to-high level within its supported range to maximize performance). Caching and prefetching mechanisms are enabled, and the cache prefetcher is configured to provide the ability to preload data for high-performance computing tasks, reducing memory access latency. Hardware acceleration units, such as vector processors and matrix computation accelerators, are enabled to improve the performance of computationally intensive tasks. After initialization, a core self-test is run, and the core enters a standby state.

[0081] E-core is a low-power core (Efficiency Core): optimized for low-frequency and low-voltage operation, supporting only basic instruction sets (such as RV32I or RV64I), suitable for background tasks or lightweight tasks.

[0082] Configure the core to low-power mode using extended CSR registers. This mode allows the core to operate at lower frequencies and voltages while activating specific power-saving features such as dynamic clock gating and power gating. Configure an automatic idle detection mechanism for the E-core to automatically switch to deep sleep mode to further reduce power consumption when the core is idle for an extended period. Set the initial operating frequency and voltage for the P-core using PMU and CSR extended instructions (maintaining them at a low to medium level within their supported range to reduce power consumption). Enable the E-core's L1 cache and limit its size to reduce energy consumption, while enabling the shared L2 cache to support multi-core collaboration. Set a cache coherence protocol to ensure that data shared by the E-core and other cores remains consistent during task migration and collaboration. Activate a lightweight data prefetch mechanism to optimize memory access paths for common background tasks (such as data acquisition or logging) and reduce unnecessary cache accesses. Enable a simplified version of the arithmetic logic unit built into the E-core to focus on low-complexity computational tasks. After initialization, run the core self-test program and enter standby mode.

[0083] The Hardware Scheduling Unit (HSU) is initialized. This unit is responsible for real-time analysis of core status and task allocation, and, in conjunction with extended RISC-V instructions, achieves efficient scheduling signal processing.

[0084] The main hardware modules of the HSU are initialized, including the task queue management unit, task allocation logic circuit, and core status monitoring module. Task queue management is configured, allocating multi-level task queues (high-priority, medium-priority, and low-priority queues) for task scheduling, setting task queue capacity and scheduling policies, and configuring the synchronization mechanism between task queues and shared memory to allow task information to be read and modified by multiple cores. The task scheduling algorithm is initialized, loading a multi-core task scheduling algorithm within the HSU, including a dynamic scheduling strategy based on lightweight AI prediction. Optimization options for the HSU scheduling logic are configured, including task packaging, task decomposition, and dynamic adjustment, ensuring minimal scheduling overhead in core allocation. Multi-core monitoring and status acquisition are configured, activating the HSU's core status monitoring module and acquiring the operating status of each core through extended CSR registers. The communication interface between the HSU and the Power Management Unit (PMU) is configured, enabling the HSU to dynamically adjust the core frequency and voltage (DVFS) according to task allocation requirements. Finally, a self-test is performed, and the system enters standby mode.

[0085] Initialize the power management unit (PMU), which monitors voltage and frequency information and dynamically adjusts the core's power state;

[0086] Activate the PMU's power supply module, set an independent clock signal to provide the PMU with a high-precision and low-latency operating environment; initialize the PMU's low-power mode logic so that it can automatically enter a power-saving state to reduce power consumption when the system load is low; initialize the PMU's multi-core dynamic voltage and frequency control module so that P-cores and E-cores can be configured separately; configure the communication interface with the HSU so that the PMU can receive voltage and frequency adjustment requests sent by the HSU; initialize the PMU's DVFS mapping table to associate the core voltage and frequency configuration with load requirements; initialize the low-power mechanism to support fast switching of core states (high-performance mode, low-power mode, hibernation); finally, perform a self-test and enter standby mode.

[0087] Initialize the shared cache module: Utilize the RISC-V cache coherency protocol to ensure data consistency and efficient communication among multiple cores.

[0088] Load the task queue and mark task characteristics (priority, real-time requirements, etc.); including:

[0089] Analyze the current task queue to determine the task priority, load type (compute-intensive or lightweight), and real-time requirements, and store the task characteristics in the task scheduling table.

[0090] Task priority: Read predefined priority flags (such as operating system kernels, real-time tasks, etc., which usually have higher priority, while ordinary background service tasks have lower priority; priority flags are set by developers during the task definition phase); dynamically adjust the priority by monitoring the task running status in real time (tasks that have not been completed for a long time may need to have their priority increased; sudden high-load real-time tasks (such as audio and video decoding, sensor data processing) will be temporarily set to high priority).

[0091] Load type: Before task allocation, task characteristics are analyzed: Computationally intensive tasks mainly consist of complex algorithms or a large number of floating-point / integer operations, such as image processing, data encryption, and AI inference; Lightweight tasks consume fewer resources and are usually simple logical judgments or short-term input / output tasks, such as sensor data reading and status detection; Task runtime analysis: Tasks with long execution times and high CPU utilization are classified as computationally intensive tasks; Tasks with low resource consumption and frequent entry into idle waiting states are classified as lightweight tasks; The system uses lightweight AI algorithms to predict the load type of the current task by analyzing the historical execution history of the task (such as execution duration and resource consumption patterns).

[0092] Real-time requirements: Task definition phase annotation: During the system design phase, developers annotate the real-time requirements of tasks (hard real-time tasks, such as device control and communication protocol processing; soft real-time tasks, such as audio and video playback and sensor data processing; non-real-time tasks, such as log recording and background calculations); Dynamic adjustment at runtime: If the task latency exceeds a set threshold, its real-time requirements can be upgraded to a higher level; if the task executes quickly and consumes few resources, its real-time requirements can be reduced.

[0093] HSU monitors the core status, which includes load (current instruction execution rate), power consumption (core power consumption obtained through PMU), and temperature (monitored through hardware sensors).

[0094] The PMU periodically collects the core status data, which is then analyzed in real time by the scheduler within the PMU.

[0095] A step-by-step threshold triggering mechanism is adopted, including:

[0096] When any of the load, power consumption, or temperature indicators exceeds 80% of the threshold for load, power consumption, or temperature, a single indicator warning is issued and the core status is recorded; however, task scheduling is not immediately triggered, only the task allocation strategy is optimized.

[0097] When two or more indicators exceed the threshold simultaneously (e.g., load > 80%, power consumption > 80%, temperature > 75℃), dynamic task scheduling is immediately triggered to migrate tasks or start / stop the core. Only when the indicator exceeds the threshold continuously within a certain time window is it considered to have exceeded the threshold, thus eliminating incorrect judgments due to jitter.

[0098] When two or more metrics remain in a low utilization state for an extended period (e.g., multiple processor loads are all <10%, power consumption <10%), the scheduler will reallocate tasks across multiple processors and shut down any redundant idle processors to conserve energy.

[0099] Dynamic task scheduling; including: high-performance P-cores or low-power E-cores

[0100] Dynamic voltage and frequency scaling (DVFS) is applied to the high-performance P-cores and low-power E-cores, assigning independent frequency and voltage to each core. High-load cores (high-performance P-cores) have their frequency increased to improve performance, while low-load cores (low-power E-cores) have their frequency and voltage reduced to save energy. During processor initialization, several P-cores and E-cores are allocated to handle different types of tasks. While P-cores and E-cores cannot be directly switched during operation, DVFS technology can adjust their operating frequency and power consumption to some extent. For example, under low overall load conditions, P-cores can operate at lower frequencies to simulate the energy efficiency characteristics of E-cores; under high overall load conditions, E-cores can increase their frequencies to temporarily improve performance.

[0101] Based on task characteristics and core status, RISC-V scheduling extension instructions are used to implement task allocation; computationally intensive tasks are allocated to high-performance P-cores, lightweight or background tasks are allocated to low-power E-cores, and low-priority tasks are allocated to low-power E-cores or scheduled later.

[0102] Cores are dynamically started and stopped using RISC-V low-power extension instructions (such as WFI); when the load increases, more cores are woken up; when the load decreases, idle cores are shut down and switched to low-power mode. Task migration is triggered when the load on a P-core task is too low or the E-core task requires higher performance.

[0103] Adaptive energy saving; including:

[0104] Based on a lightweight AI model, future load changes are predicted using historical task data, and cores are started or shut down in advance to adapt to the predicted load changes.

[0105] The lightweight AI model employs a simplified shallow neural network structure. Training is completed during the development phase, and runtime only requires loading the pre-trained model weights for rapid inference. The PMU inputs collected data such as load, power consumption, temperature, and task characteristics into the model to predict short-term load change trends and provide optimization suggestions.

[0106] The AI ​​model stores historical load changes over a given time window. By analyzing historical load data (load change trends, periodic characteristics) and current task characteristics (potential for triggering other high-load tasks), it predicts load changes for future time windows. Furthermore, by analyzing task execution cycles, the frequency and duration of load peaks, and the collaborative status of other core components, it predicts load trends for the next time window. Simultaneously, by comparing actual load changes with predictions, it adjusts model parameters (such as decision thresholds or network weights) to improve the accuracy of future predictions.

[0107] If the current task queue is empty, shut down all high-performance P-cores, keeping only one low-power E-core running in low-power mode. This further reduces power consumption.

[0108] Task migration; including:

[0109] Task migration is triggered when one of the following conditions is met:

[0110] ① The current core temperature exceeds the set temperature threshold or the current core power consumption exceeds the set power consumption threshold;

[0111] ② The current core load is consistently too high or too low; to avoid invalid task migrations caused by sudden short-term high occupancy during low-load task operation, this invention uses a time-window-based load assessment mechanism. If the core load consistently exceeds a threshold within the time window, it is marked as exceeding the threshold, triggering a step-by-step threshold triggering mechanism. This effectively reduces the frequency of invalid task migrations and improves the stability and energy efficiency of system scheduling.

[0112] ③ The characteristics of the task do not match the current core type; for example, high-load tasks run on E-core; high real-time tasks (real-time video decoding tasks), short-duration peak tasks (such as short-duration animation rendering triggered by users, which have high demand for processor resources in a short period of time, but the duration is usually very short) are assigned to E-core; low-priority background tasks occupy P-core for a long time, etc.

[0113] During task migration, extended instructions are used to save the task state to shared memory, and then the task context is restored on the target core. This ensures seamless task switching. To guarantee cache consistency, the RISC-V cache coherence protocol is used to maintain data consistency across multiple cores.

[0114] Task status (task data): Register status of the current task in the current kernel (general-purpose registers, program registers, status registers, etc.); memory context (stack pointer, global and local variables, etc.); current task scheduling information; cached data of the current kernel, etc.

[0115] Write the current core's task data to the target core specified by the task migration module to ensure that no critical data or process state is lost when the task continues to execute in the new core.

[0116] Example 3

[0117] A computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the dynamically adjustable multi-core cooperation mechanism and power optimization method based on the RISC-V architecture described in Embodiment 1 or 2.

[0118] Example 4

[0119] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the dynamically adjustable multi-core collaboration mechanism and power optimization method based on the RISC-V architecture described in Embodiment 1 or 2.

[0120] Example 5

[0121] A dynamically tunable multi-core collaboration mechanism and power optimization system based on RISC-V architecture, including:

[0122] The initialization module is configured as follows: dynamic adjustable multi-core collaborative system initialization; including: initializing the hardware module, which includes a high-performance P-core, a low-power E-core, a hardware scheduling unit (HSU), and a power management unit (PMU); loading the task queue and marking task characteristics.

[0123] The core status monitoring module is configured as follows: HSU monitors the core status; Power Management Unit (PMU) monitors voltage and frequency.

[0124] The dynamic task scheduling module is configured to: allocate tasks to high-performance P-cores or low-power E-cores based on task characteristics; idle cores enter low-power mode.

[0125] The adaptive power saving and task migration module is configured as follows: adaptive power saving includes: predicting task load changes; starting or stopping the core in advance; task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency.

Claims

1. A dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture, characterized in that, include: 1) Initialization of a dynamically adjustable multi-core cooperative system; including: Initialize the hardware module, which includes a high-performance core P-core, a low-power core E-core, a hardware scheduling unit HSU, and a power management unit PMU. Load the task queue and mark task characteristics; 2) Core status monitoring; including: HSU monitors core status; The power management unit (PMU) monitors voltage and frequency; 3) Dynamic task scheduling; including: Based on task characteristics, tasks are assigned to either high-performance P-cores or low-power E-cores. Idle cores enter low-power mode; 4) Adaptive energy saving and task migration; Adaptive power saving; including: predicting changes in task load; pre-starting or shutting down the core; Task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency. Return to step 2) and continue monitoring; HSU monitors the core status, which includes load, power consumption, and temperature; The PMU periodically collects core status data; A step-by-step threshold triggering mechanism is adopted, including: When any of the load, power consumption, or temperature indicators exceeds 80% of the threshold for load, power consumption, or temperature, a single indicator warning is issued, and the core status is recorded. When two or more metrics exceed the threshold simultaneously, dynamic task scheduling is immediately triggered to migrate tasks or start / stop the core. When two or more metrics remain in a low-occupancy state for an extended period, the scheduler will reallocate multiple processor tasks and shut down any excess idle processors.

2. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that, The hardware module is initialized using RISC-V boot and interrupt control instructions.

3. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that, Load the task queue and mark task characteristics, including: Analyze the current task queue to determine the task priority, load type, and real-time requirements, and store the task characteristics in the task scheduling table.

4. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that, Dynamic task scheduling; including: high-performance P-cores or low-power E-cores Dynamic frequency adjustment is applied to the high-performance P-core and low-power E-core, setting independent frequency and voltage for each core. The frequency of the high-load core, i.e. the high-performance P-core, is increased, while the frequency and voltage of the low-load core, i.e. the low-power E-core, are decreased. Based on task characteristics and core status, RISC-V scheduling extension instructions are used to implement task allocation; computationally intensive tasks are allocated to high-performance P-cores, lightweight or background tasks are allocated to low-power E-cores; low-priority tasks are allocated to low-power E-cores or scheduled later. The cores are dynamically started and stopped using RISC-V low-power extension instructions; when the load increases, more cores are woken up; when the load decreases, idle cores are shut down and switched to low-power mode.

5. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to claim 1, characterized in that, Adaptive energy saving; including: Based on a lightweight AI model, future load changes are predicted using historical task data, and cores are started or shut down in advance to adapt to the predicted load changes. If the current task queue is empty, shut down all high-performance P-cores and keep only one low-power E-core running in low-power mode.

6. The dynamically adjustable multi-core collaboration mechanism and power consumption optimization method based on RISC-V architecture according to any one of claims 1-5, characterized in that, Task migration; including: Task migration is triggered when one of the following conditions is met: The current core temperature exceeds the set temperature threshold or the current core power consumption exceeds the set power consumption threshold. The current core load is consistently too high or too low; The task characteristics do not match the current core type; During task migration, extended instructions are used to save the task state to shared memory, and then the task context is restored on the target core.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the dynamically adjustable multi-core collaboration mechanism and power optimization method based on the RISC-V architecture as described in any one of claims 1-6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the dynamically adjustable multi-core collaboration mechanism and power optimization method based on the RISC-V architecture as described in any one of claims 1-6.

9. A dynamically adjustable multi-core collaboration mechanism and power optimization system based on RISC-V architecture, used to implement the dynamically adjustable multi-core collaboration mechanism and power optimization method based on RISC-V architecture as described in any one of claims 1-6, characterized in that, include: The initialization module is configured as follows: dynamic adjustable multi-core collaborative system initialization; including: initializing the hardware module, which includes a high-performance P-core, a low-power E-core, a hardware scheduling unit (HSU), and a power management unit (PMU); loading the task queue and marking task characteristics. The core status monitoring module is configured as follows: HSU monitors the core status; Power Management Unit (PMU) monitors voltage and frequency. The dynamic task scheduling module is configured to: allocate tasks to high-performance P-cores or low-power E-cores based on task characteristics; idle cores enter low-power mode. The adaptive power saving and task migration module is configured as follows: adaptive power saving includes: predicting task load changes; starting or stopping the core in advance; task migration includes: saving the task context to shared content, restoring the task context on the target core, and ensuring cache consistency.

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