A hierarchical eSPI controller and its implementation method

Abstract

This invention discloses a hierarchical eSPI controller and its implementation method. The hierarchical eSPI controller chip includes two asynchronous clock domains: an asynchronous master clock domain and an interface clock domain. The hierarchical eSPI controller classifies each channel according to the characteristics of each channel in the eSPI protocol specification and finally converges them into one channel. The transmission order is determined by arbitration. The design hierarchy is clear, the modules are decoupled, and the design is greatly simplified.

Description

Technical Field

[0001] This invention relates to the field of IC integrated circuit design and bus interface, and more particularly to a hierarchical eSPI controller and its implementation method. Background Technology

[0002] With the continuous development of very large-scale integrated circuits, the functions of chips are becoming more centralized and specialized. Various chips work together in the entire electronic product system, each performing its own function. Therefore, the communication bus between chips is indispensable.

[0003] To meet different application needs and scenarios, a series of bus interface standards and specifications have emerged. Common bus interfaces in the embedded field include I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), and USB (Universal Serial Bus).

[0004] In the laptop and server sectors, the mainstream bus interfaces are currently LPC (Low Pin Count Bus Interface) and eSPI (Enhanced Serial Peripheral Interface), used for communication between the CPU (Central Processing Unit) and the EC (Embedded Controller) / BMC (Baseboard Management Controller). The EC is a dedicated system-on-a-chip, typically used in laptops, to assist the CPU in managing low-speed input devices, collecting battery parameters, and controlling motherboard temperature. The BMC, on the other hand, is used in servers and is more powerful than the EC, implementing functions such as autonomous monitoring, logging, recovery control, remote control, and power management.

[0005] Due to the fewer pins and higher speed of LPC, it was quickly adopted and has been used ever since the relevant specifications were released. With the development of technology, LPC has gradually lost its advantages: (1) LPC requires at least 7 and at most 13 signal lines; (2) 3.3V IO (Input / Output) introduces additional chip manufacturing costs; (3) LPC only supports a 33MHz clock and has a maximum bandwidth of only 133Mbps; (4) There are several sideband signal transmissions between the CPU and EC / BMC, which LPC cannot receive in the band.

[0006] Due to the many limitations of LPC, Intel launched the eSPI (Enhanced Serial Peripheral Interface) interface in 2016, which has the following advantages over LPC: (1) It fully reuses the timing and electrical characteristics of the SPI interface, and defines a protocol on this basis to meet the communication needs between the CPU and the EC / BMC; (2) It defines four channels: Peripheral, Virtual Wires, Out of Band Message, and Run-time Flash Access, so that all the sideband signals in LPC are received in the band, requiring only 8 signal lines; (3) It supports a maximum clock speed of 66MHz and a maximum bandwidth of 264Mbps.

[0007] Because the eSPI interface specification was introduced relatively late, it has not yet completely replaced LPC. Currently, most mainstream EC / BMCs support both LPC and eSPI interfaces. Implementing an eSPI communication interface between the CPU and the EC / BMC requires significant time and manpower for in-house development, or the expensive purchase of third-party IP. Summary of the Invention

[0008] The purpose of this invention is to provide a hierarchical eSPI controller and its implementation method. The hierarchical eSPI controller chip includes two asynchronous clock domains: an asynchronous master clock domain and an interface clock domain. The hierarchical eSPI controller classifies each channel according to the characteristics of each channel in the eSPI protocol specification and finally converges them into one channel. The transmission order is determined by arbitration. The design hierarchy is clear, the modules are decoupled, and the design is greatly simplified.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] A hierarchical eSPI controller is characterized by comprising two independent clock domains: a master clock domain and an interface clock domain. The master clock domain and the interface clock domain are synchronized through a cross-clock domain module. The master clock domain is used for upper-layer AXI bus and APB bus interfaces, register configuration, data packaging, and logic control. The interface clock domain is used for the eSPI bus interface, sending upper-layer data according to the protocol specification, and handling error responses on one side of the eSPI interface.

[0011] Furthermore, the master clock domain includes

[0012] The register module contains address-addressable registers used for eSPI controller initialization, interrupt enable, interrupt status acquisition, and also for initiating transmission requests, receiving data, configuring and controlling the independent channel / virtual line interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface information channel;

[0013] Peripheral device channel control module, used for controlling the transmission of peripheral device channels;

[0014] The arbitration module is used for priority arbitration of all transmission channels;

[0015] The APB slave interface processes APB bus transmission requests and enables access to address-addressable register modules.

[0016] The clock and reset module is used to generate the internal clock and reset of the master clock domain and is controlled by the register module.

[0017] The interrupt generation module is used for interrupt handling and generation, and output to the CPU or other modules with interrupt handling capabilities.

[0018] The AXI slave interface processes downlink AXI bus transmission requests from the chip side, interfaces with the peripheral device channel control module, and converts the requests into corresponding eSPI interface peripheral device channel transmissions.

[0019] The AXI main interface processes eSPI requests from the device side to the peripheral device channel, interfaces with the peripheral device channel control module, and converts the requests into the corresponding AXI interface for transmission.

[0020] The AXI interface detection module is used to monitor the transmission on the AXI slave interface and the AXI master interface to prevent the transmission on the AXI master interface and the AXI slave interface from failing to terminate normally due to abnormalities of the external eSPI slave device.

[0021] The status synchronization module is used for status updates returned by eSPI signals, and is responsible for handling errors on the eSPI interface and updating the corresponding status registers;

[0022] The exception handling module is used to handle exception events that require a return, and returns an unsuccessful completion message to the eSPI slave device according to the type of request.

[0023] Furthermore, the interface clock domain also includes

[0024] The serialization / deserialization module serializes transmitted data and deserializes received data according to the bus mode (1x / 2x / 4x) configured in the register.

[0025] The Cyclic Redundancy Check (CR) module is used to generate checksums for downlink message packets and to verify requests and data returned by the eSPI from the device.

[0026] The sampling delay module adjusts the sampling edge of the received data through configuration registers, eliminating delays introduced by I / O interfaces and wiring, and ensuring that the correct data is collected.

[0027] The clock widening module stops the eSPI interface clock output when the RX FIFO is full, thereby reducing the required RX FIFO size and eliminating the limitation that the master clock is greater than or equal to the interface clock domain.

[0028] The protocol state machine module is used to initiate and receive all transmissions and handle errors.

[0029] Furthermore, based on the initiator of the request, the transmission direction from the master device to the slave device is defined as the downlink direction, and the transmission direction from the slave device to the master device is defined as the uplink direction. The register module includes...

[0030] The address addressing register, accessed via the APB bus interface, is used for the configuration of the entire eSPI controller and is responsible for initiating transmissions on all channels except the peripheral device channel.

[0031] TX FIFO is used to store data to be transmitted in the downlink direction;

[0032] The RX FIFO is used to store the data to be received in the uplink direction.

[0033] The control logic state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of configuration / status register transmission requests.

[0034] Furthermore, the peripheral device channel control module includes a downlink module and an uplink transmission module. The downlink module includes...

[0035] The downlink state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of downlink transmission requests.

[0036] Downlink TX FIFO is used to store write transfer data from the AXI slave interface;

[0037] The downlink RX FIFO is used to store data returned from the eSPI slave device by read transfers from the AXI slave interface;

[0038] Upward direction module includes

[0039] The uplink state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of uplink transmission requests.

[0040] The uplink TX FIFO stores the data returned to the eSPI slave device based on the read transfer request initiated by the eSPI slave device.

[0041] The uplink RX FIFO is used to store data corresponding to write transfers initiated by the eSPI slave device.

[0042] Furthermore, the arbitration module includes the following four types of request inputs.

[0043] Register request, used to transmit transfers initiated by the register module;

[0044] Peripheral device interface request, used to transmit data initiated by the peripheral device channel control module;

[0045] An exception handling request is used to transmit data initiated by the exception handling module.

[0046] The prompt signal request is used to transmit the eSPI signal that initiated the transmission.

[0047] The arbitration module determines the order in which requests are initiated on the eSPI interface based on its internal arbitration mechanism.

[0048] Furthermore, the cross-clock domain module includes

[0049] In the ASYNC TX FIFO, after the transmission request of the master clock domain is arbitrated in the downlink direction, the data packet is written into the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from it.

[0050] The ASYNC RX FIFO, after the transmission request of the master clock domain is arbitrated in the uplink direction, unpacks and verifies the transmission on the eSPI bus. If there are no errors, the corresponding data is written into the ASYNC RX FIFO, and the master clock domain retrieves the data from it and distributes it to the corresponding processing module.

[0051] The synchronization module is used to synchronize control signals between the master clock domain and the interface clock domain.

[0052] A method for implementing a hierarchical eSPI controller chip includes the following steps:

[0053] The APB master device is connected to the APB slave interface on the eSPI controller side, the AXI master device is connected to the AXI slave interface on the eSPI controller side, the AXI slave device is connected to the AXI master interface on the eSPI controller side, and the eSPI interface is connected to the external eSPI bus slave device.

[0054] Transmission requests for independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface message channels are initiated through the address addressing register configured in the interface via APB; transmission requests for peripheral device channels are initiated by the peripheral channel control module through the AXI transmission request from the interface; the prompt signal initiated by the eSPI slave device is synchronized to the master clock domain of the eSPI controller and generates a prompt signal transmission request; for uplink read requests initiated by the eSPI slave device, after the protocol state machine module detects an error, it synchronizes the flag signal to the exception handling module, and the exception handling module sends an exception handling module transmission request to the exception handling path according to the current transmission composition packet.

[0055] In the arbitration module, the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests are subject to two-level cyclic arbitration. The arbitration module performs the first-level arbitration on the transmission requests initiated by the register module, and then performs the second-level arbitration on the prompt signal transmission requests initiated by the peripheral device channel control module, exception handling module, and eSPI slave device. The transmission order is determined by the arbitration result.

[0056] After arbitration is successful, transmission begins. For requests initiated by the eSPI controller and requests from the eSPI slave device requiring data return, the upper layer writes the data packet to the ASYNC TX FIFO after arbitration. The link layer sends the packet to the eSPI bus according to the protocol and sets the corresponding status bit based on the response from the eSPI slave device. For requests initiated by the eSPI slave device and requests from the eSPI controller requiring data return, the transmission on the eSPI bus is unpacked and verified after arbitration. If there are no errors, the packet is written to the ASYNC RX FIFO. The upper layer retrieves the data, unpacks it again, and stores the data in the register module or the data memory in the peripheral device channel control module according to the transmission type and packet structure. For abnormal transmission requests, a failure completion message is returned to the eSPI slave device. For prompt signal transmission requests, a status acquisition command is initiated to obtain the status information from the eSPI slave device.

[0057] Furthermore, the transition relationships and conditions between states in the control logic state machine are as follows:

[0058] (1) IDLE state to Load_Data state: Since the virtual line interface request with modifier and the peripheral device message request are in the uplink direction, the parsing of the packet is located in the uplink state machine of the protocol state machine module and the peripheral device channel control module, respectively. After receiving the flag signal, the control logic state machine jumps to the load data state to receive data and the synchronization state.

[0059] (2) IDLE state and xxx_Req state: When a command other than (1) is received in the IDLE state, it will enter the xxx_Req state. This state is the state of receiving a request and waiting for arbitration. If the transmission request in (1) is received in this state, it means that the interface layer is carrying out the corresponding transmission. Then, it returns to the IDLE state and processes the corresponding transmission according to (1). If a high-priority interruption of a low-priority event occurs in this state, it jumps back to the IDLE state and reprocesses the high-priority request.

[0060] (3) xxx_Req state and xxx_Cmd_Send state: In the xxx_Req state, after receiving the arbitration flag, it jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after sending. Otherwise, it enters the Wait_Rsp state and enters the Check_Rsp state after receiving the response.

[0061] (4) Check_Rsp state: If the received response is not an acceptance or there is no data transmission, the transmission ends and enters the CmdCpl state, waiting for state synchronization; for uplink out-of-band message channel and real-time storage access channel requests, it is necessary to enter the Checkt_Cycletype state to check. If the CycleType is correct, the data returned by the eSPI slave device is received in the same way as other commands.

[0062] (5) CmdCpl state: Data loading is complete, Cycletype parsing error occurs, non-accept response is received, no data is transmitted, or in-band reset will enter this state. This state waits for state synchronization to complete, then returns to IDLE and generates the corresponding interrupt, waiting for the next transmission request.

[0063] Furthermore, the transition relationships and conditions between states in the protocol state machine are as follows:

[0064] (1) PRO_IDLE state to PRO_CMD state: After the upper layer requests arbitration, it puts the data into Async TXFIFO. After receiving a non-empty signal, it adjusts to the PRO_CMD state to start processing commands.

[0065] (2) PRO_CMD status: Parsing commands, which are divided into three categories according to command type.

[0066] (a) The reset command (RESET CMD) does not require a response from the eSPI slave device; it directly jumps to the PRO_CPL state.

[0067] (b) Commands without a packet structure directly enter the PRO_TXCRC state;

[0068] (c) For commands with packet structure, enter the PRO_TXPACKET state to continue processing until the Async TX FIFO is empty, then jump to the PRO_TXCRC state;

[0069] (3) PRO_TXCRC state: This state generates a cyclic redundancy check code based on the sent command and packet, outputs it to the serial module, sends it according to the register configuration mode, and enters the PRO_TAR state after the transmission is completed.

[0070] (4) PRO_RSP state: The PRO_TAR phase lasts for two cycles before entering the PRO_RSP state. This state is responsible for parsing the eSPI slave device's response signal and transitioning to the corresponding state below.

[0071] (a) The response is valid and the command does not require a return packet;

[0072] (b) A valid response packet with a return message;

[0073] (c) The waiting period exceeds the set value, or the response is invalid;

[0074] (5) PRO_RXPACKET state: This state parses the returned packet according to the initiated command. If there is an error, it enters the RPO_ERR state; otherwise, it enters the PRO_STS state.

[0075] (6) PRO_ERR state: Errors occur during the operation cycle of the protocol state machine and the error reason is recorded before entering the state. When entering the state, a stateless synchronization flag signal is generated to allow the upper state machine to skip the process of obtaining the eSPI slave device status and then synchronize back to the interface domain to indicate that it can enter the next PRO_CPL state.

[0076] (7) PRO_STS status: Obtain the eSPI slave device status and write it to the Async RX FIFO;

[0077] (8) PRO_CPL: The protocol state machine eventually converges to this state, which is responsible for integrating protocol errors and cyclic redundancy check errors in the transmission process, writing them into the Async RX FIFO according to the encoding, and returning to the PRO_IDLE state after completion.

[0078] By adopting the above technical solution, the present invention has the following beneficial effects:

[0079] 1. The eSPI controller chip design is divided into two asynchronous clock domains, namely the master clock domain and the interface clock domain. This eliminates the clock dependence of different eSPI rate modes on the system bus side. The boundary between the two clock domains is clear, cross-clock domain processing is simple, and metastability risks introduced by different clock domains are avoided.

[0080] 2. The design adopts the mainstream AMBA bus. Based on the traffic bandwidth and protocol requirements, AXI4 and APB buses were selected. Since the bus interface module is not coupled with the internal functional module, the interface is clear and the logic is simple. It can be easily replaced with other bus interfaces without modifying the underlying logic.

[0081] 3. Based on the characteristics of each channel in the eSPI protocol specification, the channels are categorized and ultimately converged. The transmission order is determined by arbitration, resulting in a clear design hierarchy and decoupling between modules, which greatly simplifies the design. A feasible eSPI controller design and implementation scheme is provided, which is easy to implement.

[0082] 4. A two-level arbitration is adopted, with all transmissions related to the register module sharing the same control logic state machine, allowing only one request to be issued at a time. This maintains the independence of the communication paths between the register module and peripheral device interfaces. The arbitration module structure is simpler and easier to implement. Attached Figure Description

[0083] The invention will now be further described with reference to the accompanying drawings.

[0084] Figure 1 This is a topology diagram of a hierarchical eSPI controller chip.

[0085] Figure 2 State transition diagram for control logic state machine.

[0086] Figure 3 This is a diagram showing the state transitions between states in the protocol state machine. Detailed Implementation

[0087] The definitions of the technical terms described in this invention are shown in Table 1.

[0088] Table 1: Definitions of Technical Terms

[0089]

[0090]

[0091] like Figure 1The layered eSPI controller shown includes two independent clock domains: a master clock domain and an interface clock domain. The master clock domain and the interface clock domain are synchronized through a cross-clock domain module. The master clock domain is used for upper-layer AXI bus and APB bus interfaces, register configuration, data packaging, and logic control. The interface clock domain is used for the eSPI bus interface, sending upper-layer data according to the protocol specification, and handling error responses from the interface side.

[0092] Master clock domain includes

[0093] The register module contains address-addressable registers used for eSPI controller initialization, interrupt enable, interrupt status acquisition, and also for initiating transmission requests, receiving data, configuring and controlling the independent channel / virtual line interface channel / out-of-band message channel / real-time storage access channel / peripheral device interface information channel.

[0094] Peripheral device channel control module, used for controlling the transmission of peripheral device channels.

[0095] The arbitration module is used for priority arbitration of all transmission channels.

[0096] The APB slave interface processes APB bus transmission requests and enables access to address-addressable register modules.

[0097] The clock and reset module is used to generate the internal clock and reset of the main clock domain, and is controlled by the register module; the interrupt generation module is used for interrupt processing and generation, and output to the CPU or other modules with interrupt processing capabilities.

[0098] The AXI slave interface processes downlink AXI bus transmission requests from the chip side, interfaces with the peripheral device channel control module, and converts the requests into corresponding eSPI interface peripheral device channel transmissions.

[0099] The AXI main interface processes eSPI requests from the device side to the peripheral device channel, interfaces with the peripheral device channel control module, and converts the requests into corresponding AXI interface transmissions.

[0100] The AXI interface detection module is used to monitor the transmission on the AXI slave interface and the AXI master interface, so as to prevent the transmission on the AXI master interface and the AXI slave interface from failing to terminate normally due to abnormalities of the external eSPI slave device.

[0101] The status synchronization module is used for status updates returned by eSPI signals, and is responsible for handling errors on the eSPI interface and updating the corresponding status registers.

[0102] The exception handling module is used to handle exception events that require a return, and returns an unsuccessful completion message to the eSPI slave device according to the type of request.

[0103] The register module receives signals from the upper-layer APB bus, and the peripheral device channel control module receives signals from the upper-layer AXI bus. The data transmitted by the register module and the peripheral device channel control module are arbitrated by the arbitration module to determine the order of transmission. After arbitration, the protocol state machine module installs the received upper-layer data into the protocol and sends it out through the eSPI bus.

[0104] The interface clock domain includes

[0105] The serialization / deserialization module serializes transmitted data and deserializes received data according to the bus mode configured in the registers.

[0106] The Cyclic Redundancy Check (CR) module is used to generate checksums for downlink message packets and to verify requests and data returned by the eSPI slave device.

[0107] The sampling delay module adjusts the sampling edge of the received data through configuration registers, eliminating delays introduced by I / O interfaces and wiring, and ensuring that the correct data is collected.

[0108] The clock widening module stops the eSPI interface clock output when the RX FIFO is full, thereby reducing the required RX FIFO size and eliminating the limitation that the master clock is greater than or equal to the interface clock domain.

[0109] The protocol state machine module is used to initiate and receive all transmissions and handle errors.

[0110] Based on the request initiator, the transmission direction from the master device to the slave device is defined as the downlink direction, and the transmission direction from the slave device to the master device is defined as the uplink direction. The register module includes...

[0111] The address addressing register, accessed via the APB bus interface, is used for the configuration of the entire eSPI controller and is responsible for initiating transmissions on all channels except the peripheral device channel.

[0112] TX FIFO is used to store data to be transmitted in the downlink direction.

[0113] The RX FIFO is used to store the data to be received in the uplink direction.

[0114] The control logic state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of configuration / status register transmission requests.

[0115] The peripheral device channel control module includes a downlink module and an uplink transmission module. The downlink module includes...

[0116] The downlink state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of downlink transmission requests.

[0117] The downlink TX FIFO is used to store write transfer data from the AXI slave interface.

[0118] The downlink RX FIFO is used to store data returned from the eSPI slave device during read transfers via the AXI slave interface.

[0119] The main mapping relationship between AXI write path and eSPI transmission can be described as follows:

[0120] (1) The signals awaddr and wstrb together determine the starting address of the write transfer.

[0121] (2) The signals awsize, awlen and wstrb together determine the total amount of data written, and the written data is stored in the downlink TXFIFO.

[0122] (3) Based on the starting address of the write transfer and the amount of data, determine the PUT_PC, PUT_IOWR_SHORT or PUTMEMWR32_SHORT command to be mapped.

[0123] (4) The PUT_IOWR_SHORT command needs to wait for the eSPI Slave to respond before returning an AXI interface response. Other commands will return a response after the downlink TX FIFO is empty.

[0124] The main mapping relationship between AXI read signal path and eSPI transmission can be described as follows:

[0125] (1) The signal araddr determines the starting address of the read transfer.

[0126] (2) The signals arsize and arlen together determine the total amount of data to be read.

[0127] (3) Based on the starting address of the read transfer and the amount of data, determine the PUT_NP, PUT_IORD_SHORT or PUTMEMRD32_SHORT command to be mapped.

[0128] (4) After the eSPI interface responds and returns data, it is stored in the downlink RX FIFO.

[0129] (5) Return the AXI interface response.

[0130] Upward direction module includes

[0131] The uplink state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of uplink transmission requests.

[0132] The uplink TX FIFO stores the data returned to the eSPI slave device based on the read transfer request initiated by the eSPI slave device.

[0133] The uplink RX FIFO is used to store data corresponding to write transfers initiated by the eSPI slave device.

[0134] The main mapping relationship between eSPI transmission and AXI master interface write path can be described as follows:

[0135] 1. The eSPI interface sends an alert signal: Alert+PC_AVAIL.

[0136] 2. The eSPI master interface obtains the requested address and data through GET_PC and stores the data in the uplink RX FIFO.

[0137] 3. Generate signals awaddr, awlen, and awstrb based on the address and data volume.

[0138] 4. Once the AXI write channel data is sent, there is no need to wait for a response channel to return before processing new eSPI transmissions.

[0139] The main mapping relationship between eSPI transmission and AXI master interface read path can be described as follows:

[0140] 1. The eSPI interface sends an alert signal: Alert+NP_AVAIL.

[0141] 2. The eSPI main interface obtains the requested address and data volume through GET_NP.

[0142] 3. Generate alignment signals araddr and arlen based on the address and data volume.

[0143] 4. After waiting for the AXI read channel data to return, extract the data according to the requested starting address and data volume, package it into bytes and transmit it, and return the data via PUT_PC+Completion With Data.

[0144] The arbitration module includes the following four types of transmission requests.

[0145] Register request, used to transmit transfers initiated by the register module;

[0146] Peripheral device interface request, used to transmit data initiated by the peripheral device channel control module;

[0147] An exception handling request is used to transmit data initiated by the exception handling module.

[0148] The prompt signal request is used to transmit the eSPI signal that initiated the transmission.

[0149] The arbitration module determines the order in which requests are initiated on the eSPI interface based on its internal arbitration mechanism.

[0150] The arbitration module first arbitrates the transmissions initiated by the register module, and then arbitrates the transmissions initiated by the register module, the peripheral device channel control module, the exception handling module, and the prompt signal.

[0151] Priority is encoded using 2 bits, with smaller values ​​indicating higher priority. The commands included in the various priorities of the first-level arbitration are shown in Table 2, and the priorities of various requests in the second-level arbitration are shown in Table 3.

[0152] Table 2: Priority of various orders in Level 1 arbitration.

[0153]

[0154] Table 3: Priority of various claims in the second-level arbitration.

[0155]

[0156]

[0157] The reasons for priority allocation are as follows:

[0158] 1. Independent commands are global commands and have the highest priority (2'b00).

[0159] 2. Downlink virtual line interface class request, which transmits downlink in-band system events and GPIO, has the highest priority 2'b00.

[0160] 3. Uplink virtual line interface requests: The eSPI interface may have system events or interruptions that require timely handling by the eSPI master interface side, so assign it a higher priority of 2'b01.

[0161] 4. Exception handling is an error event. In order to return the error to the eSPI interface in a timely manner, it is assigned a higher priority of 2'b10.

[0162] 5. Data transmission requests (including peripheral device channel requests / out-of-band message requests / running flash access requests) should be kept at a low priority 2'b11.

[0163] In the arbitration module, a two-level cyclic arbitration is used for the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests. The arbitration module performs the first level of arbitration on the transmission requests initiated by the register module, and then performs the second level of arbitration on the prompt signal transmission requests initiated by the peripheral device channel control module, exception handling module, and eSPI slave device. The transmission order is determined by the arbitration result.

[0164] Priority arbitration mechanism:

[0165] 1. Among different priorities, the one with higher priority is executed first.

[0166] 2. For requests of the same priority, a round-robin arbitration method is used. That is, once a request is initiated and completed, it will be at a disadvantage when competing with other requests of the same priority, in order to avoid a certain type of request being unable to be granted for a long time.

[0167] 3. Before the second-level arbitration results are given, the first-level arbitration with higher priority can interrupt the lower-priority arbitration, and the interruption will not affect the priority order of the same level.

[0168] 4. Once the second-level arbitration is completed, transmission will begin immediately, and no further arbitration or priority interruption requests will be accepted until transmission is complete.

[0169] After arbitration is successful, transmission begins. For requests initiated by the eSPI controller and requests from the eSPI slave device requiring data return, the upper layer writes the data packet to the ASYNC TX FIFO after arbitration. The link layer sends the packet to the eSPI bus according to the protocol and sets the corresponding status bit based on the response from the eSPI slave device. For requests initiated by the eSPI slave device and requests from the eSPI controller requiring data return, the transmission on the eSPI bus is unpacked and verified after arbitration. If there are no errors, the packet is written to the ASYNC RX FIFO. The upper layer retrieves the data, unpacks it again, and stores the data in the register module or the data memory in the peripheral device channel control module according to the transmission type and packet structure. For abnormal transmission requests, a failure completion message is returned to the eSPI slave device. For prompt signal transmission requests, a status acquisition command is initiated to obtain the status information from the eSPI slave device.

[0170] Cross-clock domain modules include

[0171] In the ASYNC TX FIFO, after the transmission request of the master clock domain is arbitrated in the downlink direction, the data packet is written into the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from it.

[0172] The ASYNC RX FIFO, after the transmission request of the master clock domain is arbitrated in the uplink direction, unpacks and verifies the transmission on the eSPI bus. If there are no errors, the corresponding data is written into the ASYNC RX FIFO, and the master clock domain retrieves the data from it and distributes it to the corresponding processing module.

[0173] The synchronization module is used to synchronize control signals between the master clock domain and the interface clock domain.

[0174] A method for implementing a hierarchical eSPI controller chip includes the following steps:

[0175] The APB slave interface connects to the APB bus slave device on the eSPI controller side, the AXI slave interface connects to the AXI bus slave device on the eSPI controller side, the AXI master interface on the eSPI controller side connects to the on-chip AXI bus master device, and the eSPI interface connects to the off-chip eSPI bus slave device.

[0176] Transmission requests for independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface message channels are initiated through the address addressing register configured in the APB interface; transmission requests for peripheral device channels are initiated by the peripheral channel control module through the AXI interface transmission request; the prompt signal initiated by the eSPI slave device is synchronized to the master clock domain of the eSPI controller and generates a prompt signal transmission request; for uplink read requests initiated by the eSPI slave device, after the protocol state machine module detects an error, it synchronizes the flag signal to the exception handling module, and the exception handling module sends an exception handling module transmission request to the exception handling path according to the current transmission composition packet.

[0177] The transition relationships and conditions between states in the control logic state machine are as follows: Figure 2 As shown in the figure. To facilitate understanding of the working principle of the state machine, English labels are used in the figure, and Table 4 explains each state.

[0178] Table 4. Definitions of states in the control logic state machine.

[0179] English status Chinese status IDLE Idle state xxx_Req Received xxx request pending arbitration status xxx_CmdSend Send xxx command status Wait_Rsp Waiting for response status Check_Rsp Check response status Load_data Loading data status Check_Cycletype Check cycletype status CmdCpl Request completion status

[0180] (1) IDLE state to Load_Data state: Since the virtual line interface request with modifier (VW_modifier) ​​and the peripheral device message request (PR_RxMsg) are in the uplink direction, the parsing of the packets is located in the uplink state machine of the protocol state machine module and the peripheral device channel control module, respectively. After receiving the flag signal, the control logic state machine jumps to the Load_data state to receive data and synchronize.

[0181] (2) IDLE state and xxx_Req state: When a command other than (1) is received in the IDLE state (Any Req), it will enter the xxx_Req state. This state is the state of receiving a request and waiting for arbitration. If the transmission request in (1) is received in this state, it means that the interface layer is carrying out the corresponding transmission. Then, it returns to the IDLE state and processes the corresponding transmission according to (1). If a high-priority interruption of a low-priority event occurs in this state, it jumps back to the IDLE state and reprocesses the high-priority request.

[0182] (3) xxx_Req state and xxx_Cmd_Send state: In the xxx_Req state, after receiving the arbitration flag (RG_Grant), it jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after sending. Otherwise (Other CMD), it enters the Wait_Rsp state and enters the Check_Rsp state after receiving the response (Response Received).

[0183] (4) Check_Rsp state: If the received response is not Accept or No Data, the transmission ends and enters the CmdCpl state, waiting for state synchronization; for uplink out-of-band message channel and real-time storage access channel requests (Up OOB / Flash+Accept), it is necessary to enter the Check_Cycletype state to check. If the CycleType is correct, the data returned by the eSPI from the device is received in the same way as other commands.

[0184] (5) CmdCpl state: Data loading is complete (DataLoadDone), Cycletype parsing error, receiving a non-accept response or no data transmission (No Accept or No Data), and in-band reset (InBandReset) will enter this state. This state waits for status synchronization to complete (StatusLdDone), then returns to IDLE and generates the corresponding interrupt, waiting for the next transmission request.

[0185] The transition relationships and conditions between states in the protocol state machine are as follows: Figure 3 As shown in the figure. To facilitate understanding of the working principle of the state machine, English labels are used in the figure, and Table 5 explains each state.

[0186] Table 5 defines the states in the protocol state machine.

[0187]

[0188]

[0189] (1) PRO_IDLE state to PRO_CMD state: After the upper layer requests arbitration, it puts the data into the Async TXFIFO. After receiving the non-empty signal (TX FIFO Not Empty), it adjusts to the PRO_CMD state to start processing commands.

[0190] (2) PRO_CMD status: Parsing commands, which are divided into three categories according to command type.

[0191] (a) The reset command (RESET CMD) does not require a response from the eSPI slave device; it directly jumps to the PRO_CPL state.

[0192] (b) Commands without a packet structure (CMD without TX Packet) directly enter the PRO_TXCRC state;

[0193] (c) For commands with packet structure (CMD with TX Packet), enter the PRO_TXPACKET state to continue processing until Async TX FIFO (TX FIFO Empty) is empty, then jump to the PRO_TXCRC state;

[0194] (3) PRO_TXCRC state: This state generates a cyclic redundancy check code based on the sent command and packet, outputs it to the serial module, and sends it according to the register configuration mode. After the transmission is completed (8-bit CRC Finished), it enters the PRO_TAR state.

[0195] (4) PRO_RSP state: After the PRO_TAR phase lasts for two cycles, it enters the PRO_RSP state, which is responsible for parsing the response signal of the eSPI slave device and jumping to the following corresponding states.

[0196] (a) The response is valid and the command does not require a return packet (Valid Response without RX Packet);

[0197] (b) A valid response with an RX packet;

[0198] (c) The waiting period exceeds the set value, or the response is invalid (Wait Timeout or Invalid Response);

[0199] (5) PRO_RXPACKET state: This state parses the returned packet according to the initiated command. If there is an error (CycleType Error or Length Error), it enters the RPO_ERR state; otherwise (Receive Finish without Error), it enters the PRO_STS state.

[0200] (6) PRO_ERR state: Errors occur during the operation cycle of the protocol state machine and it will enter this state. The reason for the error will be recorded before entering. When entering this state, a stateless synchronization flag signal (NOSTS_SyncBack) is generated. This is used by the upper-layer state machine to skip the process of obtaining the eSPI slave device status and then synchronize back to the interface domain to indicate that it can enter the next PRO_CPL state.

[0201] (7) PRO_STS status: Obtain the eSPI slave device status and write it to the Async RX FIFO;

[0202] (8) PRO_CPL: The protocol state machine eventually converges to this state, which is responsible for integrating protocol errors and cyclic redundancy check errors in the transmission process, writing them into the Async RX FIFO according to the encoding, and returning to the PRO_IDLE state after completion.

[0203] A method for implementing a hierarchical eSPI controller includes an APB master device connected to the eSPI controller's APB slave interface, an AXI master device connected to the eSPI controller's AXI slave interface, an AXI slave device connected to the eSPI controller's AXI master interface, and an eSPI interface connected to an external eSPI bus slave device.

[0204] Transmission requests for independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface message channels are initiated through the address addressing register configured in the APB interface; transmission requests for peripheral device channels are initiated by the peripheral channel control module through the AXI interface transmission request; the prompt signal initiated by the eSPI slave device is synchronized to the master clock domain of the eSPI controller and generates a prompt signal transmission request; for uplink read requests initiated by the eSPI slave device, after the protocol state machine module detects an error, it synchronizes the flag signal to the exception handling module, and the exception handling module sends an exception handling module transmission request to the exception handling path according to the current transmission composition packet.

[0205] In the arbitration module, a two-level cyclic arbitration is used for the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests. The arbitration module performs the first level of arbitration on the transmission requests initiated by the register module, and then performs the second level of arbitration on the prompt signal transmission requests initiated by the peripheral device channel control module, exception handling module, and eSPI slave device. The transmission order is determined by the arbitration result.

[0206] After arbitration is successful, transmission begins. For requests initiated by the eSPI controller and requests from the eSPI slave device requiring data return, the upper layer writes the data packet to the ASYNC TX FIFO after arbitration. The link layer sends the packet to the eSPI bus according to the protocol and sets the corresponding status bit based on the response from the eSPI slave device. For requests initiated by the eSPI slave device and requests from the eSPI controller requiring data return, the transmission on the eSPI bus is unpacked and verified after arbitration. If there are no errors, the packet is written to the ASYNC RX FIFO. The upper layer retrieves the data, unpacks it again, and stores the data in the register module or the data memory in the peripheral device channel control module according to the transmission type and packet structure. For abnormal transmission requests, a failure completion message is returned to the eSPI slave device. For prompt signal transmission requests, a status acquisition command is initiated to obtain the status information from the eSPI slave device.

[0207] The above are merely specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on the present invention to solve essentially the same technical problems and achieve essentially the same technical effects are all covered within the protection scope of the present invention.

Claims

1. A hierarchical eSPI controller, characterized in that: It includes two independent clock domains: a master clock domain and an interface clock domain. The master clock domain and the interface clock domain are synchronized through a cross-clock domain module. The master clock domain is used for upper-layer AXI and APB bus interfaces, register configuration, data packaging, and logic control. The interface clock domain is used for the eSPI bus interface, sending upper-layer data according to the protocol specification and handling error responses on one side of the eSPI interface. The master clock domain includes a register module containing address-addressable registers used for eSPI controller initialization, interrupt enabling, and interrupt status acquisition. It is also used for initiating transmission requests, receiving data, configuring, and controlling transmission requests for independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface information channels. A peripheral device channel control module is used for controlling peripheral device channel transmissions. The arbitration module is used for priority arbitration of all transmission channels; The APB slave interface processes APB bus transmission requests and enables access to address-addressable register modules. The system comprises the following modules: a clock and reset module, used to generate the internal clock and reset within the master clock domain, controlled by the register module; an interrupt generation module, used for interrupt handling and generation, outputting to the CPU or other modules with interrupt handling capabilities; an AXI slave interface, which processes downlink AXI bus transmission requests from the chip side, interfacing with the peripheral device channel control module to convert requests into corresponding eSPI interface peripheral device channel transmissions; an AXI master interface, which processes uplink peripheral device channel requests from the eSPI slave device side, interfacing with the peripheral device channel control module to convert requests into corresponding AXI interface transmissions; an AXI interface detection module, used to monitor transmissions on the AXI slave and AXI master interfaces to prevent transmissions from failing to terminate properly due to external eSPI slave device anomalies; a status synchronization module, used for status updates returned by eSPI slave signals, and responsible for handling errors on the eSPI interface and updating the corresponding status registers; and an exception handling module, used to handle exception events requiring a return, returning an unsuccessful completion message to the eSPI slave device based on the request type. The interface clock domain includes a serial deserialization module, which serializes transmitted data and deserializes received data according to the bus mode configured in the register. The Cyclic Redundancy Check (CR) module generates checksums for downlink message packets and verifies requests and data returned by the eSPI slave device. The sampling delay module adjusts the sampling edge of received data through configuration registers, eliminating delays introduced by I / O interfaces and wiring to ensure correct data acquisition. The clock stretching module stops the eSPI interface clock output when the RX FIFO is full, reducing the required RX FIFO size and eliminating the limitation that the master clock must be greater than or equal to the interface clock domain. The protocol state machine module initiates and receives all transmissions and handles errors. The cross-clock domain module includes an ASYNC TX FIFO. After the transmission request of the master clock domain is arbitrated in the downlink direction, the data packet is written into the ASYNC TX FIFO, and the interface clock domain obtains the data required for packet assembly from it. The ASYNC RX FIFO is used to arbitrate the transmission request of the master clock domain in the uplink direction, unpack and verify the transmission on the eSPI bus, and write the corresponding data into the ASYNC RX FIFO after verification. The master clock domain then retrieves the data from the ASYNC RX FIFO and distributes it to the corresponding processing module. A synchronization module is used to synchronize control signals between the master clock domain and the interface clock domain.

2. The hierarchical eSPI controller according to claim 1, characterized in that: Based on the initiator of the request, the transmission direction from the master device to the slave device is defined as the downlink direction, and the transmission direction from the slave device to the master device is defined as the uplink direction. The register module includes an address addressing register, which is accessed through the APB bus interface and is used for the configuration of the entire eSPI controller and is responsible for initiating the transmission of all channels except the peripheral device channel; and a TX FIFO, which is used to store the data to be sent in the downlink direction. The RX FIFO is used to store the data to be received in the uplink direction. The control logic state machine controls the initiation, arbitration, packet transmission, response reception, and RX data reception of the configuration / status register transmission request.

3. The hierarchical eSPI controller according to claim 1, characterized in that: The peripheral device channel control module includes a downlink module and an uplink transmission module. The downlink module includes a downlink state machine, which controls the initiation, arbitration, packet transmission, response reception, and reception of downlink transmission requests and RX data; and a downlink TX FIFO, which is used to store write transmission data from the AXI slave interface. The downlink RX FIFO stores data returned from the eSPI slave device during read transfers via the AXI slave interface. The uplink module includes an uplink state machine that controls the initiation, arbitration, packet transmission, response reception, and RX data reception of uplink transmission requests. The uplink TX FIFO stores data returned to the eSPI slave device based on read transfer requests initiated by the eSPI slave device. The uplink RX FIFO is used to store data corresponding to write transfers initiated by the eSPI slave device.

4. The hierarchical eSPI controller according to claim 1, characterized in that: The arbitration module includes register requests for transmitting transmissions initiated by the register module; peripheral device interface requests for transmitting transmissions initiated by the peripheral device channel control module; exception handling requests for transmitting transmissions initiated by the exception handling module; and alert signal requests for transmitting transmissions initiated by the eSPI alert signal. The arbitration module determines the order in which requests are initiated on the eSPI interface according to its internal arbitration mechanism.

5. The implementation method of a hierarchical eSPI controller as described in any one of claims 1-4, characterized in that, The process includes the following steps: The APB master device connects to the APB slave interface on the eSPI controller side; the AXI master device connects to the AXI slave interface on the eSPI controller side; the AXI slave device connects to the AXI master interface on the eSPI controller side; and the eSPI interface connects to the off-chip eSPI bus slave device. Transmission requests for independent channels / virtual line interface channels / out-of-band message channels / real-time storage access channels / peripheral device interface message channels are initiated through the address addressing register configured on the APB slave interface. Transmission requests for peripheral device channels are initiated by the peripheral channel control module through the transmission requests of the AXI slave interface. The eSPI synchronizes the alert signal initiated by the device to the master clock domain of the eSPI controller and generates an alert signal transmission request; When an eSPI uplink read request is initiated by the device, the protocol state machine module detects an error and synchronizes the flag signal to the exception handling module. The exception handling module then sends an exception handling module transmission request to the exception handling path based on the current transmission composition packet. In the arbitration module, the input register transmission requests, peripheral device interface transmission requests, exception handling transmission requests, and prompt signal transmission requests are subject to two-level cyclic arbitration. The arbitration module performs the first-level arbitration on the transmission requests initiated by the register module, and then performs the second-level arbitration on the prompt signal transmission requests initiated by the peripheral device channel control module, exception handling module, and eSPI slave device. The transmission order is determined by the arbitration result. After arbitration is successful, transmission begins. For requests initiated by the eSPI controller and requests from the eSPI slave device requiring data return, the upper layer writes the data packet to the ASYNC TX FIFO after arbitration. The link layer sends the packet to the eSPI bus according to the protocol and sets the corresponding status bit based on the response from the eSPI slave device. For requests initiated by the eSPI slave device and requests from the eSPI controller requiring data return, the transmission on the eSPI bus is unpacked and verified after arbitration. If there are no errors, the packet is written to the ASYNC RX FIFO. The upper layer retrieves the data, unpacks it again, and stores the data in the register module or the data memory in the peripheral device channel control module according to the transmission type and packet structure. For abnormal transmission requests, a failure completion message is returned to the eSPI slave device. For prompt signal transmission requests, a status acquisition command is initiated to obtain the status information from the eSPI slave device.

6. The implementation method of a hierarchical eSPI controller according to claim 5, characterized in that: The transition relationships and conditions between control logic state machine states are as follows: (1) IDLE state to Load_Data state: Since the virtual line interface request with modifier and the peripheral device message request are in the uplink direction, the parsing of the packet is located in the uplink state machine of the protocol state machine module and the peripheral device channel control module, respectively. After receiving the flag signal, the control logic state machine jumps to the Load_Data state to receive data and synchronize; (2) IDLE state and xxx_Req state: When a command other than (1) is received in the IDLE state, it will enter the xxx_Req state. This state is the state of receiving a request and waiting for arbitration. If the transmission request in (1) is received in this state, it means that the interface layer is performing the corresponding transmission. Then, it returns to the IDLE state and processes the corresponding transmission according to (1). If a high-priority interruption of a low-priority event occurs in this state, it jumps back to the IDLE state and reprocesses the high-priority request; (3) xxx_Req state and xxx_Cmd_Send state: In the xxx_Req state, after receiving the arbitration flag, it jumps to the xxx_Cmd_Send state. If the command is an in-band reset, the command is completed after the sending is completed. Otherwise, it enters the Wait_Rsp state and enters the Check_Rsp state after receiving a response; (4) Check_Rsp state: If the received response is not an acceptance or there is no data transmission, the transmission ends and enters the CmdCpl state, waiting for state synchronization; For uplink out-of-band message channel and real-time storage access channel requests, it is necessary to enter the Check_Cycletype state for checking. If the CycleType is correct, it will receive the data returned by the eSPI slave device in the same way as other commands; (5) CmdCpl state: Data loading is complete, Cycletype parsing error, receiving a non-accept response or no data transmission, and in-band reset will all enter this state. This state waits for state synchronization to complete, then returns to IDLE and generates a corresponding interrupt, waiting for the next transmission request.

7. The implementation method of a hierarchical eSPI controller according to claim 5, characterized in that: The transition relationships and conditions between states in the protocol state machine are as follows: (1) PRO_IDLE state to PRO_CMD state: After the upper layer requests arbitration, it puts the data into the Async TX FIFO. After receiving a non-empty signal, it adjusts to the PRO_CMD state to start processing commands; (2) PRO_CMD state: Parses commands and classifies them into three categories according to command type: (a) Reset command (RESET CMD) does not require the eSPI slave device to return a response and jumps directly to the PRO_CPL state; (b) Commands without packet structure directly enter the PRO_TXCRC state; (c) Commands with packet structure enter the PRO_TXPACKET state to continue processing until the Async TX FIFO is empty and jumps to the PRO_TXCRC state; (3) PRO_TXCRC state: This state generates a cyclic redundancy check code based on the sent command and packet, outputs it to the serial module, sends it according to the register configuration mode, and enters the PRO_TAR state after sending. (4) PRO_RSP state: After two cycles of the PRO_TAR phase, the PRO_RSP state is entered. This state is responsible for parsing the response signal of the eSPI slave device and jumping to the following corresponding states: (a) The response is valid and the command does not need to return a packet; (b) The response is valid and there is a returned packet; (c) The waiting period exceeds the set value, or the response is invalid; (5) PRO_RXPACKET state: This state parses the returned packet according to the initiated command. If there is an error, it enters the RPO_ERR state; otherwise, it enters the PRO_STS state; (6) PRO_ERR state: Errors occurring during the operation cycle of the protocol state machine will enter this state. The reason for the error will be recorded before entering. Entering this state will generate a stateless synchronization flag signal to allow the upper-layer state machine to skip the process of obtaining the eSPI slave device state and then synchronize back to the interface field to indicate that it can enter the next PRO_CPL state; (7) PRO_STS state: Obtain the eSPI slave device state and write it into the Async RX FIFO; (8) PRO_CPL: The protocol state machine finally converges to this state, which is responsible for integrating the protocol errors and cyclic redundancy check errors in the transmission process. Write the data to the Async RX FIFO according to the encoding, and return to the PRO_IDLE state after completion.

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