A high-efficiency TM-CFAR implementation method based on FPGA

Abstract

The application particularly relates to a high-efficiency TM-CFAR implementation method based on FPGA. The method comprises the following steps: when a CFAR reference unit slides to a current position, determining a current reference unit corresponding to a current detection unit; wherein the current reference unit comprises a first moving-in sample located in a left reference unit, a second moving-in sample located in a right reference unit, and an original sample; comparing each sample in the current reference unit with the first moving-in sample and the second moving-in sample respectively to obtain corresponding current reference unit comparison results; based on the current reference unit comparison results, combining stored historical comparison results to perform data statistics, and updating the sorting results corresponding to each sample in the current reference unit according to the data statistics results; according to the sorting results of each parameter in the current reference unit, screening a target sample by using a preset parameter selection strategy, and calculating a TM-CFAR-based clutter power evaluation result corresponding to the current detection unit by using the target sample.

Description

Technical Field

[0001] This invention relates to the field of radar technology, specifically to a method and apparatus for implementing high-efficiency TM-CFAR based on FPGA, a storage medium, a computer program product, and an electronic device. Background Technology

[0002] In radar signal processing, Constant False Alarm Rate (CFAR) is a commonly used signal processing algorithm. Based on different methods of processing reference cell samples, radar target CFAR processing methods can be divided into Mean Level (ML) CFAR and Ordered Statistical (OS) CFAR. Trimmed Mean (TM) CFAR, as a type of ordered CFAR, offers improved detection performance against uniform clutter backgrounds compared to classic OS-CFAR, while retaining the strong multi-target detection performance of OS-CFAR. TM-CFAR inevitably requires sorting the data within the CFAR reference cell during computation, resulting in high computational complexity. However, there is currently a lack of dedicated optimization methods for TM-CFAR.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This invention provides an efficient TM-CFAR implementation method and apparatus based on FPGA, a storage medium, a computer program product, and an electronic device, which can reduce the computational complexity of the TM-CFAR algorithm in the sorting stage, significantly reduce the consumption of logic resources, and thus overcome the defects existing in the prior art to a certain extent.

[0005] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0006] According to a first aspect of the present invention, an efficient TM-CFAR implementation method based on FPGA is provided, the method comprising:

[0007] When the CFAR reference unit slides to the current position, the current reference unit corresponding to the current detection unit is determined; wherein, the current reference unit includes: a first sample moved in from the left reference unit, a second sample moved in from the right reference unit, and the original sample;

[0008] Each sample in the current reference unit is compared with the first and second samples to obtain the corresponding comparison result of the current reference unit.

[0009] Based on the current reference unit alignment results, data statistics are performed in conjunction with the stored historical alignment results, and the ranking results corresponding to each sample in the current reference unit are updated according to the data statistics results.

[0010] Based on the sorting results of each sample in the current reference unit, target samples are selected using a preset parameter selection strategy, and clutter power assessment results based on TM CFAR for the current detection unit are calculated using the target samples.

[0011] In some exemplary embodiments, the step of comparing each parameter in the current reference unit with the first and second moved-in samples respectively to obtain the corresponding current reference unit comparison result includes:

[0012] Using the comparators corresponding to each parameter in the reference unit, we obtain whether the current parameter is greater than or equal to the comparison results of the first and second moved-in samples;

[0013] Save the comparison results to the comparison result register corresponding to the current sample.

[0014] In some exemplary embodiments, the comparator includes an inlet comparator and an outlet comparator;

[0015] The method further includes:

[0016] The sample in the reference cell entry shift register is compared with all samples in the reference cell shift register using an entry comparator, and the comparison result is stored in the entry comparison result register; wherein, the reference cell entry shift register includes: a left reference cell entry register for storing the sample corresponding to the left reference cell, and a right reference cell entry register for storing the sample corresponding to the right reference cell;

[0017] An exit comparator is used to compare the samples in the reference unit exit shift register with all samples in the reference unit shift register, and the comparison result is stored in the exit comparison result register; wherein, the reference unit exit shift register includes a left reference unit exit register and a right reference unit exit register for storing samples to be shifted out.

[0018] In some exemplary embodiments, the method includes:

[0019] A virtual decimal processor is used to add virtual decimals to the comparison results output by each comparator.

[0020] In some exemplary embodiments, determining the sorting result corresponding to each sample in the current reference unit based on data statistical results includes:

[0021] For each sample in the current reference cell, the incremental statistical method is used to count the number of parameters smaller than the current sample in the current reference cell using the corresponding counter;

[0022] The sorting result of the sample is determined based on the number of parameters, and the sorting result is saved in the count result register.

[0023] In some exemplary embodiments, the sorting result is the sequence number of the parameter;

[0024] The step of filtering target samples based on the sorting results of samples in the current reference unit using a preset parameter selection strategy includes:

[0025] The decision-maker determines whether the current sample should be removed based on its sequence number and outputs the corresponding decision result; the decision result is identified by binary data.

[0026] The target samples to be extracted are determined based on the binary data identifier, and the clutter power assessment results are calculated using the target samples.

[0027] In some exemplary embodiments, the method includes:

[0028] The window of the CFAR reference cell is slidable using a reference cell shift register, and the sample corresponding to the current reference cell is stored.

[0029] According to a second aspect of the present invention, an efficient TM-CFAR implementation device based on FPGA is provided, comprising:

[0030] The data comparison module is used to determine the current reference unit corresponding to the current detection unit when the CFAR reference unit slides to the current position; and to compare each sample in the current reference unit with the first moved-in sample and the second moved-in sample respectively to obtain the corresponding current reference unit comparison result; wherein, the current reference unit includes: the first moved-in sample located in the left reference unit, the second moved-in sample located in the right reference unit, and the original sample;

[0031] The data statistics module is used to perform data statistics based on the current reference unit comparison results and the stored historical comparison results, and to update the ranking results of each sample in the current reference unit according to the data statistics results.

[0032] The clutter power estimation module is used to filter target samples based on the sorting results of each sample in the current reference cell using a preset parameter selection strategy, and to calculate the clutter power evaluation result based on TM CFAR for the current detection cell using the target samples.

[0033] According to a third aspect of the present invention, a storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described FPGA-based high-efficiency TM-CFAR implementation method.

[0034] According to a fourth aspect of the present invention, an electronic device is provided, comprising:

[0035] Processor; and

[0036] Memory for storing the executable instructions of the processor;

[0037] The processor is configured to implement the above-described FPGA-based high-efficiency TM-CFAR implementation method by executing the executable instructions.

[0038] According to a fifth aspect of the present invention, a computer program product is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the above-described efficient TM-CFAR implementation method based on FPGA.

[0039] The efficient TM-CFAR implementation method based on FPGA provided in the embodiments of the present invention requires, when the CFAR reference unit slides to its current position, comparing each sample in the reference unit with the first and second moved-in samples to obtain the corresponding comparison results of the current reference unit. Then, combining this with the historical comparison results corresponding to the samples not moved out of the current reference unit, data statistics are performed, and the sorting results corresponding to each sample in the current reference unit are determined based on the data statistics results. A preset parameter selection strategy is then used to filter target samples, and the clutter power evaluation result corresponding to the current detection unit is calculated using the target samples. By utilizing the comparison results between existing samples, after the CFAR reference unit moves, only the samples newly moved into the reference unit are compared with existing samples, which greatly reduces the computational load of comparison calculations during the sorting process, thereby significantly reducing the computational resource consumption of the CFAR algorithm.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0042] Figure 1The illustration shows a schematic diagram of an efficient TM-CFAR implementation method based on FPGA, an exemplary embodiment of the present invention.

[0043] Figure 2 The diagram illustrates a method flow of an exemplary embodiment of the present invention.

[0044] Figure 3 The diagram illustrates the system configuration corresponding to an efficient TM-CFAR implementation method based on FPGA, an exemplary embodiment of the present invention.

[0045] Figure 4 This schematic diagram illustrates a virtual decimal processing method according to an exemplary embodiment of the present invention.

[0046] Figure 5, including Figures 5a-5d The diagram illustrates a data preparation method process according to an exemplary embodiment of the present invention.

[0047] Figure 6, including Figures 6a-6d This diagram illustrates, in a schematic representation of an exemplary embodiment of the present invention, a data comparison diagram at each stage of a comparison result register operation process.

[0048] Figure 7 The diagram illustrates a system flow for initial data processing according to an exemplary embodiment of the present invention.

[0049] Figure 8 This diagram illustrates a system flow diagram of subsequent data processing according to an exemplary embodiment of the present invention.

[0050] Figure 9 This diagram illustrates the principle of an exemplary embodiment of the present invention for initial data processing based on incremental statistical methods.

[0051] Figure 10 This diagram illustrates the principle of a method for subsequent data processing based on an incremental statistical method, as exemplified by an embodiment of the present invention.

[0052] Figure 11 This schematic diagram illustrates a periodic time series diagram of an incremental statistical method according to an exemplary embodiment of the present invention.

[0053] Figure 12 This schematic diagram illustrates the system framework of another efficient TM-CFAR implementation method based on FPGA, an exemplary embodiment of the present invention.

[0054] Figure 13 This schematic diagram illustrates how the resource usage of a lookup table varies with the number of reference units under different schemes in an exemplary embodiment of the present invention.

[0055] Figure 14This schematic diagram illustrates how the resource usage of different schemes of triggers varies with the number of reference units in an exemplary embodiment of the present invention.

[0056] Figure 15 The schematic diagram illustrates an exemplary embodiment of the present invention: a high-efficiency TM-CFAR implementation device based on an FPGA.

[0057] Figure 16 The diagram illustrates the composition of an electronic device according to an exemplary embodiment of the present invention. Detailed Implementation

[0058] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0059] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0060] In related technologies, CFAR (Constant False Alarm Rate) refers to a technique that maintains a constant false alarm rate during radar target detection. The basic CFAR algorithm requires estimating the noise and interference levels within the detected cell and calculating a decision threshold based on the estimation results. The decision unit determines the presence of a target by comparing the target cell signal with the decision threshold. Classical CFAR algorithms are classified according to their interference level estimation methods, including Mean Level (ML) CFAR, Ordered Statistics (OS) CFAR, and Adaptive CFAR. Mean Level CFAR is characterized by using an averaging method in the local interference power estimation process. Its advantage is good detection performance in uniform clutter backgrounds. However, in multi-target environments and environments with non-uniform interference targets, the presence of interfering targets in the reference cell, which are incorrectly treated as noise in the threshold calculation, raises the detection threshold and ultimately reduces the detection probability. Mean Level CFAR suffers from high detection loss in multi-target and non-uniform interference environments. Based on this, existing technologies have proposed sorted statistical (OS) CFAR detectors. These detectors significantly reduce the impact of interfering targets in the reference cells on interference level estimation by sorting the target values ​​of the reference cells from smallest to largest and selecting the k-th value from them. The trade-off for OS CFAR is a loss in detection performance compared to CA CFAR in a uniform background, especially when k is small. Considering the shortcomings of OS CFAR, existing technologies have proposed the Trimmed-Mean (TM) CFAR algorithm. TM CFAR first sorts the target values ​​of the reference cells, then removes the smallest r1 and largest r2 samples from the sorted results, and then averages the remaining samples to estimate the clutter power level. This method retains the good anti-multi-target interference capability of OS CFAR. Meanwhile, in a uniform clutter background, the detection loss of TM CFAR is between that of CA CFAR and OS CFAR. The following examples illustrate the resource usage of several classic CFARs. Mean-based CFARs are relatively simple to implement because they only require averaging the reference cells, resulting in low computational complexity. Considering the sliding characteristics of the CFAR reference cell, the moving average method is used to calculate the mean. Therefore, the computational resource usage is... For OS-CFAR, one existing FPGA-based OS-CFAR implementation skips the sorting step of OS-CFAR and directly performs CFAR decision using the binary accumulation concept, achieving a parallel pipelined OS-CFAR processing method. Assuming this method is used for one-dimensional CFAR processing, the resource usage for the sorting part is O(N). Commonly used fully parallel sorting networks in FPGAs include odd-even sorting networks, bitonic sorting networks, and AKS sorting networks. These sorting networks can achieve fully parallel pipelined sorting, outputting a set of sorting results in each clock cycle, making them suitable for the TM-CFAR algorithm. For odd-even sorting networks and bitonic sorting networks, their computational resource usage is... For the AKS sorting network, its computational resource usage is... While the AKS algorithm theoretically achieves optimal resource utilization, its resource utilization depth coefficient is extremely large. [5] In typical CFAR applications, the AKS sorting network consumes fewer resources than the odd-even sorting network and the bitonic sorting network. Existing technologies have significantly higher resource consumption. Furthermore, TM-CFAR requires multiple values ​​from the sorting results to estimate clutter power levels, making it impossible to directly utilize the optimization methods proposed in existing technologies.

[0061] To address the shortcomings and deficiencies of existing technologies, this example implementation provides an efficient TM-CFAR implementation method based on FPGA. In existing TM-CFAR algorithm implementations using sorting networks, whenever a CFAR reference cell moves to a new position, the sorting network performs sorting on all data from that reference cell as entirely new input. However, since the CFAR reference cell only moves one target cell at a time, only two data points in the reference cell are new; the remaining data have already been sorted before the CFAR reference cell moves. If the existing sorting results can be fully utilized, and only the data in the newly moved reference cell is sorted after the CFAR reference cell moves, the computational load during the sorting process can be significantly reduced, thereby greatly reducing the computational resource consumption of the CFAR algorithm. Based on this design concept, in this example implementation, the reference... Figure 1 As shown, the efficient TM-CFAR implementation method based on FPGA can specifically include the following steps:

[0062] Step S11: When the CFAR reference unit slides to the current position, determine the current reference unit corresponding to the current detection unit; wherein, the current reference unit includes: a first sample moved in from the left reference unit, a second sample moved in from the right reference unit, and the original sample;

[0063] Step S12: Compare each sample in the current reference unit with the first moved-in sample and the second moved-in sample respectively to obtain the corresponding current reference unit comparison result;

[0064] Step S13: Based on the current reference unit comparison result, perform data statistics by combining the stored historical comparison results, and update the sorting result corresponding to each sample in the current reference unit according to the data statistics result;

[0065] Step S14: Based on the sorting results of each sample in the current reference unit, the target sample is screened using a preset parameter selection strategy, and the clutter power evaluation result based on TM CFAR corresponding to the current detection unit is calculated using the target sample.

[0066] The following will describe in more detail each step of the efficient TM-CFAR implementation method based on FPGA in this example embodiment, with reference to the accompanying drawings and embodiments.

[0067] In this example implementation, an FPGA (Field Programmable Gate Array) is a programmable device that can be programmed to change the structure of its internal circuitry, thereby implementing various logic functions. FPGAs possess high parallel processing capabilities and low latency, making them an ideal platform for high-performance implementation of various radar signal processing algorithms. The time complexity and resource consumption of implementing the CFAR algorithm on an FPGA are considered. Due to the flexibility of FPGA-based algorithm implementations, a trade-off can be struck between time complexity and resource consumption for the same algorithm implementation. Here, the runtime of the FPGA-based CFAR algorithm is specified, thus focusing solely on the algorithm's resource consumption. For example... Figure 2 As shown, the length of the CFAR reference cell is N, and the length of the target cell to be detected is M. When performing CFAR operations in the FPGA, a window sliding operation is performed once per clock cycle. At each new position the window slides to, the CFAR operation outputs a new background clutter power level estimate and a decision threshold. Under these conditions, the time complexity of the CFAR algorithm is O(n log n). The main difference in the implementation of various algorithms lies in the amount of computing resources used.

[0068] Suppose that TM-CFAR uses M clock cycles to complete the reference cell window sliding operation and outputs a CFAR clutter power estimate in each clock cycle. Then TM-CFAR requires a fully parallel sorting network to perform the sorting operation. Commonly used fully parallel sorting networks in FPGAs include odd-even sorting networks, bitonic sorting networks, and AKS sorting networks. These sorting networks can implement fully parallel pipelined sorting, outputting a set of sorting results in each clock cycle, making them suitable for the TM-CFAR algorithm.

[0069] In step S11, when the CFAR reference unit slides to the current position, the current reference unit corresponding to the current detection unit is determined; wherein, the current reference unit includes: a first sample moved in from the left reference unit, a second sample moved in from the right reference unit, and the original sample.

[0070] For example, refer to Figure 2 As shown, when the window slides to the right, when the CFAR reference unit slides to the current position, unit 4 is the current detection unit, and units 3 and 5 are protection units respectively; units 0-2 form the left reference unit, unit 2 is the first sample moved in, and units 0 and 1 are the original samples that were not moved out during this window slide; units 6-8 form the right reference unit, unit 8 is the second sample moved in, and units 6 and 7 are the original samples that were not moved out during this window slide.

[0071] When the CFAR reference element slides to its current position, the current reference element is represented as: For example, refer to Figure 3 The diagram shows the structure when both left and right reference elements have a length of 3. When the reference element length is any N, it can be derived from... Figure 3 The structure shown is obtained through reasonable extrapolation to achieve the corresponding design. When the length of the reference unit increases, only the processing module for the corresponding row needs to be added.

[0072] In step S12, each sample in the current reference unit is compared with the first moved-in sample and the second moved-in sample to obtain the corresponding comparison result of the current reference unit.

[0073] For example, the step of comparing each parameter in the current reference unit with the first shifted sample and the second shifted sample respectively to obtain the corresponding comparison result of the current reference unit includes: using the comparator corresponding to each sample in the reference unit to obtain the comparison result of whether the current sample is greater than or equal to the first shifted sample and the second shifted sample; and saving the comparison result to the comparison result register corresponding to the current sample.

[0074] Specifically, an FPGA-based data comparison module can be provided to compare the data in the reference cell during CFAR operations and save the comparison result to the comparison result register.

[0075] For example, the method includes: using a reference cell shift register to slide a window over the CFAR reference cell and storing the sample corresponding to the current reference cell.

[0076] For example, refer to Figure 3As shown, the reference cell shift register stores the data corresponding to the reference cell in the CFAR operation, i.e., the sample value. This register implements the translation operation of the reference cell in the CFAR operation in the form of a shift register.

[0077] refer to Figure 3 As shown, the comparators are labeled with the data sources and comparison items. Each comparator requires two "greater than" comparisons and two "equal to" comparisons, for a total of four comparisons.

[0078] The comparison result register is responsible for temporarily storing the comparison result output by the comparator. To minimize resource usage, the comparison result register is implemented by configuring the LUT in the FPGA resource SLICEM as a shift register. Since the function of the comparison result register is closely related to the execution process of this invention, its specific structure and function will be described in detail later when introducing the execution flow of this invention.

[0079] For example, the method includes adding a virtual decimal to the comparison results output by each comparator using a virtual decimal processor.

[0080] Specifically, for ease of data processing, subsequent modules expect the data in the reference unit shift registers to be distinct. However, actual radar signals cannot guarantee that the input data will be mutually exclusive. Therefore, a virtual decimal point processor is added here. The principle of the virtual decimal point processor is as follows... Figure 4 As shown. After the comparator output is processed by the virtual decimal point processor, it is equivalent to adding a "decimal part" to the data in the reference unit shift register. For example, the reference... Figure 4 As shown, D2 and D0 in the reference cell shift register are equal and both are 0. After adding a virtual decimal, since 0.4 is greater than 0.0, D2 > D0. Since the virtual decimals are distinct, adding a virtual decimal to the data in the reference cell shift register ensures that the data are distinct.

[0081] If the virtual decimal function is implemented by directly increasing the data width of the reference unit shift register, it will inevitably increase the comparator input data width, thereby increasing computational resource consumption and the number of combinational logic stages. Preferably, to save computational resources, the virtual decimal function is implemented by adding an additional virtual decimal processor after the data comparison is completed. For example, in Figure 2In this approach, we define virtual decimal values ​​as increasing downwards. In the virtual decimal processor, suppose we need to process the relationship between D0 and D2. When the output pin of comparator D0 > D2 is 1, the output pin of the virtual decimal processor corresponding to D0 > D2 is 1, and D2 > D0 is 0. When the output pin of comparator D0 = D2 is 1, considering that the virtual decimal value of D0 is less than D2, the output pin of the virtual decimal processor corresponding to D0 > D2 is 0, and D2 > D0 is 1. The virtual decimal processing for other data follows the same principle.

[0082] As the reference cell length N increases, the data comparison module only needs to add corresponding comparators. For a single comparator, its resource usage does not change with the reference cell length. Therefore, the computational resource usage of the data comparison module is... .

[0083] In step S13, based on the current reference unit comparison result, combined with the stored historical comparison results, data statistics are performed, and the sorting results corresponding to each sample in the current reference unit are updated according to the data statistics results.

[0084] For example, the sorting result corresponding to each sample in the current reference unit is determined based on the data statistics results, including: for each sample in the current reference unit, the incremental statistical method is used to count the number of parameters smaller than the current sample in the current reference unit using the corresponding counter;

[0085] The sorting result of the sample is determined based on the number of parameters, and the sorting result is saved in the count result register.

[0086] For example, using a preset parameter selection strategy to filter target samples includes:

[0087] The decision-maker determines whether the current sample should be removed based on its sequence number and outputs the corresponding decision result; the decision result is identified by binary data.

[0088] The target samples to be extracted are determined based on the binary data identifier, and the clutter power assessment results are calculated using the target samples.

[0089] Specifically, an FPGA-based data statistics module can also be provided to statistically analyze the comparison results output by the data comparison module. Specifically, a counter in a certain row of the data statistics module is responsible for counting all data in the reference cell shift register that are smaller than the data in that row of the reference cell shift register, and storing the statistical result in a count result register. For example, Figure 3Currently, the value of the first row of the reference unit shift register is D1. Therefore, the function of the counter in the first row of the data statistics module is to count the number of data values ​​less than D1 among all data values ​​D3D3', D2D2', and D1D1' in the reference unit shift register. In this embodiment, the statistical result "2" means that there are 2 data values ​​less than D1 in the reference unit shift register. In other words, if the reference unit shift register is sorted from smallest to largest and the index corresponding to the smallest value is set to 0, then the index corresponding to D0 is 2.

[0090] Preferably, to save computational resources, the incremental counting method is used here. Using the incremental counting method reduces the computational complexity of the counter in the data statistics module from... Reduced to This significantly reduces resource consumption. The method will be further illustrated through subsequent examples. Specifically, for the alignment results between samples that have not been removed from the left and right reference units, the historical alignment results of each sample can be obtained through the register corresponding to that sample.

[0091] In this embodiment, the resource usage of the comparison result register is However, the coefficient for this item is relatively small, so its impact on overall resource usage is minimal. Actual test results show that in most CFAR application scenarios, this item's resource consumption does not dominate the overall resource consumption.

[0092] In step S14, target samples are selected based on the sorting results of each sample in the current reference unit using a preset parameter selection strategy, and clutter power evaluation results based on TM CFAR for the current detection unit are calculated using the target samples.

[0093] For example, determining the ranking result corresponding to each sample in the current reference unit based on the data statistical results includes:

[0094] For each sample in the current reference cell, the incremental statistical method is used to count the number of parameters smaller than the current sample in the current reference cell using the corresponding counter;

[0095] The sorting result of the sample is determined based on the number of parameters, and the sorting result is saved in the count result register.

[0096] For example, the sorting result is the sequence number of the sorting parameter;

[0097] The step of filtering target samples based on the sorting results of samples in the current reference unit using a preset parameter selection strategy includes:

[0098] The decision-maker determines whether the current sample should be removed based on its sequence number and outputs the corresponding decision result; the decision result is identified by binary data.

[0099] The target samples to be extracted are determined based on the binary data identifier, and the clutter power assessment results are calculated using the target samples.

[0100] Specifically, an FPGA-based clutter power estimation module can also be provided. This module uses the data sorting index stored in the counting result register and the data value in the reference cell shift register to perform clutter power estimation in CFAR operations. Specifically, in the clutter power estimation module, the decision unit is responsible for determining whether a certain number should be removed when estimating clutter power. When the sorting index of a certain number meets the specified criteria... If the result is zero, it means that the number should not be removed. The corresponding decision result for this number is binary "1", otherwise it is binary "0".

[0101] The decision result register stores the decision result of the decision unit. The bit width of the decision result register is the same as the number of reference cell registers. In the decision result register, each binary bit represents whether the data in the corresponding reference cell shift register should be discarded.

[0102] The data extraction function checks if the decision result is "0"; if it is "0", the corresponding number in the reference cell shift register is set to zero. If it is not "0", it is output as is. The output of the data extractor is the cell within the reference cell that participated in the calculation of clutter power.

[0103] After data extraction, the cells within the reference cell that participated in the clutter power calculation are summed. The summation result is then shifted and averaged to obtain the TM-CFAR estimate of the clutter power.

[0104] When summing using the method of this invention, the total amount of data involved in the summation is N. When summing using a fully parallel sorting network, the total amount of data involved in the summation is... The method of this invention increases the amount of data involved in the summation. However, considering that the summation operation itself has low complexity and is not the main source of complexity for the algorithm, the increase in resource usage due to the added operation is negligible.

[0105] For example, the data processing of the above method may include the following steps:

[0106] Step S1, Data Preparation. Specifically, the data preparation stage involves initial data comparison and initialization of the comparison result register. No clutter power is output during the data preparation stage. (Reference) Figure 3 The diagram illustrates an example of a data preparation process. It is understood that, due to the parallel processing characteristics of FPGAs, although the following steps are described sequentially, they are actually processed in parallel during the actual computation.

[0107] Step S1a: Initialize the reference cell shift register and the comparison result register. Specifically, initializing the reference cell shift register means filling the left and right reference cell shift registers with R / 2-1 target cell values ​​to be referenced. Initializing the comparison result register means filling the comparison result from the reference cell shift register initialization stage into the comparison result register. The initialization of the reference cell shift register and the initialization of the comparison result register are performed simultaneously.

[0108] refer to Figure 5a , Figure 5b The diagram shows the process of initializing the reference cell shift register and the comparison result register during the data preparation phase. Figure 5a In the middle, the left and right reference unit shift registers are shifted into the first data D0D0' respectively. After being processed by the comparator and the virtual fractional processor, the comparison results D0>D0'D0 and D0'>D0'D0 are output. Figure 5b In the middle, the data in the left and right reference cell shift registers are shifted upwards, and the second data D1D1' is shifted in at the same time. The comparison result register stores the comparison results D0>D0'D0 and D0'>D0'D0 generated in the previous clock cycle.

[0109] In this invention, the comparison result register needs to store the comparison result of a certain data in the reference cell shift register with all other data. The resource consumption increases with the length N of the reference cell by a certain scale. To reduce the resource consumption of the comparison result register and make it applicable to more CFAR processing scenarios, this invention implements the comparison result register by configuring the LUT resources in the FPGA as a shift register. The structure of the comparison result register is shown in Figure 6.

[0110] Figure 6 illustrates the structure and operation flow of the comparison result register when N=6. The arrows in the figure indicate the direction of data shifting in the shift registers. Figure 6 only shows the storage process of the data comparison results in the right entry unit register and the left and right reference unit shift registers. The data storage process corresponding to the left entry unit register can be deduced similarly. Note that the bottom layer in the figure does not belong to the comparison result register, but rather represents the data comparison results output by the virtual decimal processor. Therefore, the comparison result register structure shown in the figure consists of two shift registers of length 2 and two shift registers of length 1. Considering the functionality of subsequent modules, the register units shown by the dashed lines in Figure 6 do not need to be implemented; they are drawn here for the sake of symmetry and aesthetics in the module structure. Figures 6a-6c These are schematic diagrams corresponding to stages 0, 1, 2, and 3, respectively.

[0111] Step S1b: Initialize the counting result register. Specifically, after step S1a is completed, the comparison result register and the reference cell shift register stop the translation operation. The left and right reference cell entry registers are then sequentially filled with the values ​​from the first step. For example, Figure 5c The left and right reference cell entry registers were filled with D0' and D0, respectively. Figure 5d The left and right reference cell entry registers are filled with D1' and D1 respectively. In step 1b, each time the reference cell entry register is updated, the virtual decimal processor updates a comparison result. The counter counts these updated comparison results and updates the count result register. Here, the counter uses incremental counting. Specifically, the counter counts the number of binary "1"s in the comparison result output by the virtual decimal processor and adds this number to the count result register. For example, Figure 5c The first row counter adds the count of binary "1"s in the comparison result corresponding to "D0>D0'D0" to the first row count result register. After one clock cycle, Figure 5d The first row counter adds the number of binary "1"s in the comparison result corresponding to "D0>D1'D1" to the first row count result register. The other rows follow the same pattern.

[0112] During the initialization of the technical result register, the value of the comparison result register remains unchanged. In the previous example, the value of the comparison result register will remain unchanged. Figure 6b The state shown.

[0113] Step S2, initial data processing. (See reference) Figure 7 As shown, the calculation of the first clutter power estimate is performed after the data preparation phase is completed.

[0114] Step S2a: Fill the left and right reference cell entry registers. Specifically, fill the left and right reference cell entry registers with the R-th target cell value to be referenced. For example, Figure 7 The left reference cell entry register is filled with D2', and the right reference entry register is filled with D2.

[0115] Step S2b: The comparison result register resumes its shift. Specifically, the comparison result processed by the virtual fractional processor arrives at the input port of the comparison result register. The shift register in the comparison result register resumes its shift and will save the comparison result in the next clock cycle. For example, the comparison result represented by "D2>D2'D2D1'D1 D0'D0" at the input port of the comparison result register in Figure 5 will be saved in the next clock cycle. Figure 7The comparison result register output port has an exit register. In the next clock cycle, the data at the comparison result register output port will be stored in the comparison result register exit register. In actual implementation, this exit register can be implemented using a flip-flop, or by increasing the length of the shift register in the comparison result register.

[0116] Step S2c: Update the counting result register. Specifically, in the data statistics module, the counter updates the counting result register using the same incremental statistics method as in step 1. For example, the first row counter adds the number of binary "1"s in the comparison result corresponding to "D0>D2'D2" to the counting result register. At this time, the counting result register stores the position index of each value in the reference cell shift register in the sorting result.

[0117] Step S2d: Estimate clutter power. Specifically, in the clutter power estimation module, the clutter power at the current location of the CFAR reference cell is estimated based on the value of the current counting result register. The specific calculation method has been given in the functional module description above. For example, Figure 7 The calculation results shown are the clutter power estimation results corresponding to the data in the CFAR reference cell being D0, D0', D1, D1', D2, and D2', respectively.

[0118] Step S3: Subsequent data processing. Specifically, after obtaining the first clutter power estimate in step S2, the CFAR reference cell is shifted one target cell to the right. This operation results in two new data points being added to the CFAR reference cell, while two existing data points are removed. In this method, the two new data points appear at the input ports of the left and right reference cells, respectively.

[0119] Step S3a: Update the left and right reference cell shift registers and input registers. Specifically, the left and right reference cell shift registers are each shifted upwards by one reference cell. Simultaneously, the data from the input ports of the left and right reference cells is saved to the left and right reference cell input registers. For example, Figure 8 In this context, D3 and D3' represent the data newly added to the reference cell shift register, while D0 and D0' represent the data removed from the reference cell.

[0120] Step S3b: Update the comparison result register. Specifically, the comparison result after virtual decimal point processing is saved into the comparison result register. For example... Figure 8As shown, the comparison result at the entry point of the comparison result register is updated to "D3>D3'D3D2'D2D1'D1" and "D3'D3'D3D2'D2D1'D1". The comparison result register moves the comparison results "D2>D2'D2D1'D1?" and "D2'>D2'D2D1'D1?" from the entry point of the previous cycle into the comparison result register. At the same time, the exit register of each row of the comparison result register will save the value at the exit point of the comparison result register. Figure 8 The values ​​of the comparison result register and the output register are “D1>D0'D0?”, “D1'>D0'D0?”, “D2>D0'D0?”, and “D2'>D0'D0?”.

[0121] Step S3c: Update the counting result register. Specifically, a counter in a certain row of the data statistics module is responsible for counting all data in the reference unit shift register that are smaller than the data in that row of the reference unit shift register, and storing the statistical result in the counting result register. Preferably, this number is obtained through incremental statistics. An example is given below. Figure 7 , Figure 8 In the counter structure, the counter in row 0 is isolated here, as shown below. Figure 8 , Figure 9 As shown in Figure 6. A magnified view of the counters in rows 0 and 2 is shown below. Figure 9 As shown. Figure 8 Enlarged view of the counters in rows 0 and 2 as shown below Figure 8 As shown. In Figure 8 and Figure 9 In the previous clock cycle comparison result register, a new register was added to store the comparison result in the previous clock cycle comparison result register 2. Figure 11 for Figure 9 , Figure 10 Timing diagram of the data changes in each register. Figure 7 , Figure 8 The counter and count result register in line 0 are Figure 9 , Figure 10 Figure 11 The counter 0 and the counting result register 0 are in the same register, and the others can be deduced similarly.

[0122] like Figure 8 , Figure 9 , Figure 10 As shown, the virtual decimal processor of this invention outputs the initial data comparison result in clock cycle 0. Clock cycle 1 outputs the first subsequent data comparison. The counting result register stores the initial data statistics result in clock cycle 1 and the first subsequent data statistics result in clock cycle 2. The specific method for performing data statistics in clock cycle 0 has been described in step S2. Figure 10 , Figure 11As shown, in clock cycle 1, virtual fractional processor 0 outputs the comparison result "D1>D3'D3?", and counter result register 2 stores the initial data statistics result of data D1, which is the sequence number of data D1 in the sorting result. In clock cycle 1, counter 0 calculates the sequence number of data D1 in the sorting result, adds the number of binary "1"s in "D1>D3'D3?", and subtracts the number of binary "1"s in "D1>D0'D0?". This result is the sequence number of D1 in the CFAR reference cell sorting result. In clock cycle 2, this sorting result is written to technical result register 0. Similarly, counter 0 can output the sorting result of the 0th row of reference cell data every clock cycle. The above analysis only applies to counter 0; the same logic applies to other row counters.

[0123] By using the incremental counting method, the counter can update the value of the counting result register with only 4 binary bits and the previous value. This property still holds true when the number of reference cells in the CFAR operation changes. Regardless of the reference cell length, the counter only needs to refer to 4 bits of input data and... The bit count result value. Therefore, this method can effectively reduce the combinational logic stages when the counter counts the number of binary "1"s. When the reference cell length is N, the counter bit width is As the reference cell length N increases, the computational complexity and resource consumption of the counter become... .

[0124] Note that the last two rows of counters in the diagram cannot use the incremental counting method when performing binary "1" counts. Specifically, Figure 8 When counting the number of binary "1"s in the comparison results D3>D3'D3D2'D2D1'D1 and D3'>D3'D3D2'D2D1'D1, the incremental counting method cannot be used. Here, it is necessary to count the number of binary "1"s in all bits of the comparison result register. Note that only the last two rows of counters have this characteristic. Therefore, the resource usage of the last two rows of counters, which varies with the length of the CFAR reference cell, remains the same. In summary, the computational resource consumption of the data statistics module is... .

[0125] Step S3d: Estimate clutter power. Specifically, in the clutter power estimation module, the clutter power at the current location of the CFAR reference cell is estimated based on the value of the current counting result register. As an example, the calculation results shown in the figure are the clutter power estimation results corresponding to the data in the CFAR reference cell being D1, D1', D2, D2', D3, and D3', respectively.

[0126] Step S3e: Shift the CFAR reference cell to further complete the data calculation. Specifically, shift the CFAR reference cell one target cell to the right. The two new data points for the CFAR reference cell at the new position appear at the input ports of the left and right reference cells, respectively. Repeat steps one through four of S3 to obtain the clutter power estimate for the CFAR reference cell at the new position. Repeat the above operations until the clutter power estimates for the CFAR reference cell at all positions have been calculated.

[0127] In addition, in some exemplary embodiments, the comparator includes an inlet comparator and an outlet comparator.

[0128] The method further includes: using an entry comparator to compare the parameters in the reference cell entry shift register with all the parameters in the reference cell shift register, and storing the comparison result in an entry comparison result register; wherein, the reference cell entry shift register includes: a left reference cell entry register for storing the parameters corresponding to the left reference cell, and a right reference cell entry register for storing the parameters corresponding to the right reference cell;

[0129] An exit comparator is used to compare the parameters in the reference cell exit shift register with all parameters in the reference cell shift register, and the comparison result is stored in the exit comparison result register; wherein, the reference cell exit shift register includes a left reference cell exit register and a right reference cell exit register for storing the sample to be shifted out.

[0130] Specifically, this scheme further optimizes the comparator and the comparison result register. (Reference) Figure 12 As shown, for the reference cell shift register, the registers at which data is shifted out of the left and right reference cell shift registers are called the left and right reference cell exit registers.

[0131] Comparators are divided into two types: input comparators and output comparators. Each type of comparator is equipped with a corresponding virtual fractional processor. The input comparator compares the data in the reference cell's input shift register with all the data in the reference cell's shift register.

[0132] The added exit comparator compares the data in the reference unit's exit shift register with all the data in the reference unit's shift register. Figure 12 As shown, the comparator represented by the solid line is the input comparator, and the comparator represented by the dashed line is the output comparator. The data in the input reference register of the input comparator includes D2 and D2'; the data in the output reference register of the output comparator includes D0 and D0'.

[0133] By nearly doubling the number of comparators in the data comparison module, the comparison result register no longer requires a large number of intermediate comparison results, thereby eliminating the resource consumption of the data statistics module. project.

[0134] In addition, the newly added export comparator is also equipped with a corresponding virtual decimal processor.

[0135] Furthermore, the comparison result register only stores the output of the virtual decimal processor; it does not need to store historical comparison results and does not require initialization during data processing. Therefore, the resource consumption of the comparison result register can be greatly reduced.

[0136] For example, during data processing, the four binary bits required by the counter come directly from the output of the comparison module. In this case, the counting result register does not need to store all the comparison results, but only needs to temporarily store the four binary bits to improve the module's operating frequency.

[0137] Of the four binary bits that the counter needs to reference, two come from the input comparator, and the other two come from the output comparator. For this scheme, the data processing steps and module input / output timing characteristics are exactly the same as in the first embodiment. An initialization step is required before the CFAR reference cell begins to shift. However, only the counting result register needs to be initialized. The clock cycles required for initialization and the operation timing are exactly the same as in the first embodiment described above.

[0138] For example, the resource usage of a solution implementing TM CFAR using a traditional parallel network is... In comparison, the resource usage of the comparator section in implementing the TM CFAR algorithm in this invention will reach [amount missing]. The overall resource usage does not exceed .

[0139] For example, referring to Table 1, taking N=16 as an example, a detailed comparison table of resource usage between the present invention and the traditional bitonetic sorting network scheme on the XILINX ZYNQ 7100 platform is given.

[0140] Table 1

[0141]

[0142] refer to Figure 13 and Figure 14 As shown in the table, the total resource usage trends of each scheme are presented under different numbers of reference units. These data show that the present invention has significantly lower resource usage compared to the traditional bitonetic sorting network scheme. The table also shows that Scheme 1, compared to Scheme 2, has significantly lower resource usage. It has advantages in all scenarios. Further experiments have demonstrated that, in the application scenarios described in this invention, In this scenario, Scheme 1 is more advantageous than Scheme 2. If BRAM is used to implement the comparison result register, the advantageous range of Scheme 1 can be further extended. However, considering that the reference cell length in the CFAR algorithm is generally small in practical applications, the application value of further extension schemes is relatively low.

[0143] The method provided in this invention utilizes the sliding characteristic in the CFAR operation process and designs a TM CFAR clutter power estimation system based on FPGA. When implementing the TM CFAR algorithm using this method, the resource usage of the comparator section will reach [amount missing]. The overall resource usage does not exceed This significantly reduces resource consumption. Furthermore, the method features a fully parallel pipeline structure, achieving data throughput comparable to traditional fully parallel sorting networks.

[0144] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0145] Further reference Figure 15 As shown, this example implementation also provides an efficient TM-CFAR implementation device 150 based on FPGA, comprising:

[0146] The data comparison module 1501 is used to determine the current reference unit corresponding to the current detection unit when the CFAR reference unit slides to the current position; and to compare each sample in the current reference unit with the first moved-in sample and the second moved-in sample respectively to obtain the corresponding current reference unit comparison result; wherein, the current reference unit includes: the first moved-in sample located in the left reference unit, the second moved-in sample located in the right reference unit, and the original sample;

[0147] The data statistics module 1502 is used to perform data statistics based on the current reference unit comparison results and the stored historical comparison results, and to update the sorting results of each sample in the current reference unit according to the data statistics results.

[0148] The clutter power estimation module 1503 is used to filter target samples based on the sorting results of each sample in the current reference cell using a preset parameter selection strategy, and to calculate the clutter power evaluation result based on TM CFAR corresponding to the current detection cell using the target samples.

[0149] The device 150 can be an FPGA device, and the functional implementation of each module has been explained in detail in the corresponding method embodiments, and will not be repeated here.

[0150] It should be noted that although several modules or units of the device for performing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0151] Figure 16 A schematic diagram of an electronic device suitable for implementing embodiments of the present invention is shown.

[0152] It should be noted that, Figure 16 The electronic device 1000 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0153] like Figure 16 As shown, the electronic device 1000 includes a Central Processing Unit (CPU) 1001, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 1002 or programs loaded from storage section 1008 into Random Access Memory (RAM) 1003. The RAM 1003 also stores various programs and data required for system operation. The CPU 1001, ROM 1002, and RAM 1003 are interconnected via a bus 1004. An Input / Output (I / O) interface 1005 is also connected to the bus 1004.

[0154] The following components are connected to I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to I / O interface 1005 as needed. Removable media 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1010 as needed so that computer programs read from them can be installed into storage section 1008 as needed.

[0155] In particular, according to embodiments of the present invention, the processes described below with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a storage medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by central processing unit (CPU) 1001, it performs various functions defined in the system of this application.

[0156] It should be noted that the storage medium shown in the embodiments of the present invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, wherein computer-readable program code is carried. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0157] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0158] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0159] It should be noted that, as another aspect, this application also provides a storage medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The aforementioned storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments. For example, the electronic device may perform... Figure 1 The steps of the method shown.

[0160] In one embodiment, this application provides a computer program product including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0161] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0162] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.

[0163] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A high-efficiency TM-CFAR implementation method based on FPGA, characterized in that, The method includes: When the CFAR reference unit slides to the current position, the current reference unit corresponding to the current detection unit is determined; wherein, the current reference unit includes: a first sample moved in from the left reference unit, a second sample moved in from the right reference unit, and the original sample; Each sample in the current reference unit is compared with the first and second samples to obtain the corresponding comparison result of the current reference unit. Based on the current reference unit alignment results, data statistics are performed in conjunction with the stored historical alignment results, and the ranking results corresponding to each sample in the current reference unit are updated according to the data statistics results. Based on the sorting results of each sample in the current reference unit, target samples are selected using a preset parameter selection strategy, and clutter power assessment results based on TM CFAR for the current detection unit are calculated using the target samples.

2. The method according to claim 1, characterized in that, The step of comparing each sample in the current reference unit with the first and second moved-in samples respectively to obtain the corresponding current reference unit comparison result includes: Using the comparators corresponding to each sample in the reference unit, obtain the comparison results of whether the current sample is greater than or equal to the first and second samples moved in; Save the comparison results to the comparison result register corresponding to the current sample.

3. The method according to claim 2, characterized in that, The comparator includes an inlet comparator and an outlet comparator; The method further includes: The sample in the reference cell entry shift register is compared with all samples in the reference cell shift register using an entry comparator, and the comparison result is stored in the entry comparison result register; wherein, the reference cell entry shift register includes: a left reference cell entry register for storing the sample corresponding to the left reference cell, and a right reference cell entry register for storing the sample corresponding to the right reference cell; An exit comparator is used to compare the samples in the reference unit exit shift register with all samples in the reference unit shift register, and the comparison result is stored in the exit comparison result register; wherein, the reference unit exit shift register includes a left reference unit exit register and a right reference unit exit register for storing samples to be shifted out.

4. The method according to claim 2 or 3, characterized in that, The method includes: A virtual decimal processor is used to add virtual decimals to the comparison results output by each comparator.

5. The method according to claim 1, characterized in that, The step of determining the sorting result corresponding to each sample in the current reference unit based on the data statistical results includes: For each sample in the current reference cell, the incremental statistical method is used to count the number of parameters smaller than the current sample in the current reference cell using the corresponding counter; The sorting result of the sample is determined based on the number of parameters, and the sorting result is stored in the counting result register.

6. The method according to claim 5, characterized in that, The sorting result is the sequence number of the sample. The step of filtering target samples based on the sorting results of samples in the current reference unit using a preset parameter selection strategy includes: The decision-maker determines whether the current sample should be removed based on its sequence number and outputs the corresponding decision result; the decision result is identified by binary data. The target samples to be extracted are determined based on the binary data identifier, and the clutter power assessment results are calculated using the target samples.

7. The method according to claim 1, characterized in that, The method includes: The window of the CFAR reference cell is slidable using a reference cell shift register, and the sample corresponding to the current reference cell is stored.

8. A high-efficiency TM-CFAR implementation device based on FPGA, characterized in that, The device includes: The data comparison module is used to determine the current reference unit corresponding to the current detection unit when the CFAR reference unit slides to the current position; and to compare each sample in the current reference unit with the first moved-in sample and the second moved-in sample respectively to obtain the corresponding current reference unit comparison result; wherein, the current reference unit includes: the first moved-in sample located in the left reference unit, the second moved-in sample located in the right reference unit, and the original sample; The data statistics module is used to perform data statistics based on the current reference unit comparison results and the stored historical comparison results, and to update the ranking results of each sample in the current reference unit according to the data statistics results. The clutter power estimation module is used to filter target samples based on the sorting results of each sample in the current reference cell using a preset parameter selection strategy, and to calculate the clutter power evaluation result based on TM CFAR for the current detection cell using the target samples.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the efficient TM-CFAR implementation method based on FPGA as described in any one of claims 1 to 7.

10. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the efficient TM-CFAR implementation method based on FPGA as described in any one of claims 1 to 7 by executing the executable instructions.

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