Testing device and operation method thereof
By designing a test device including a first memory unit and a control unit, the problem of cumbersome and inconvenient maintenance of the test integrated circuit memory device in the prior art is solved, and the expansion and maintenance convenience of the test content are achieved.
Patent Information
- Application Number
- CN202410921010.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2024-07-10
- Publication Date
- 2025-05-30
AI Technical Summary
When testing integrated circuits of built-in memory devices, the process of building a test solution is cumbersome, resource consumption is large, failure rate is high, and update and maintenance are inconvenient.
A testing device is designed, including a first memory unit and a control unit. The first memory unit stores a test program, the control unit reads and executes a test program, performs a write read test on the second memory unit, and generates a test result code.
It increases the expansion of test content and file maintenance convenience, reduces additional manual burning and plug-in and pull-out actions, and improves the convenience of use.
Smart Images
Figure CN120072014A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a test device, and particularly to a test device and an operation method thereof. Background Art
[0002] Generally speaking, for an integrated circuit (IC) with a built-in memory device, when testing the memory device, if a straightforward way is adopted to construct a test scheme, that is, adding an external flash memory to a test carrier board and then burning a test code to drive a micro control unit (MCU) for testing, this will make the process of constructing the test scheme cumbersome and resource-consuming. There are problems such as a relatively high failure rate in the construction result of the test scheme and it is not easy to update and maintain the test scheme.
[0003] Therefore, how to effectively design a test device is an important issue at present. Summary of the Invention
[0004] The present invention provides a test device and an operation method thereof, so as to increase the expandability of test content and the convenience of file maintenance, without additional manual burning and plugging actions, and increase the convenience in use.
[0005] The present invention provides a test device, including a first memory unit and a control unit. The first memory unit stores a test program. The control unit has a second memory unit. The control unit reads the test program. The control unit executes the test program to perform a write / read test on the second memory unit to generate a test result code. The first memory unit is built in the control unit, or the first memory unit and the control unit are disposed in an integrated circuit.
[0006] The present invention provides an operation method of a test device, including the following steps. Store a test program through the first memory unit. Provide a control unit having a second memory unit. Read the test program through the control unit. Execute the test program through the control unit to perform a write / read test on the second memory unit to generate a test result code. The first memory unit is built in the control unit, or the first memory unit and the control unit are disposed in an integrated circuit.
[0007] For the test device and the operation method thereof disclosed by the present invention, a test program is stored through the first memory unit, the control unit reads and executes the above test program from the first memory unit, and performs a write / read test on the second memory unit to generate a test result code. In this way, the expandability of test content and the convenience of file maintenance can be increased, without additional manual burning and plugging actions, and the convenience in use can be increased. Description of the Drawings
[0008] Figure 1 Schematic diagram of a test device according to an embodiment of the present invention.
[0009] Figure 2A is Figure 1 Schematic diagram of the setting relationship between the first memory unit and the control unit of
[0010] Figure 2B is Figure 1 Another schematic diagram of the setting relationship between the first memory unit and the control unit of
[0011] Figure 3 Flowchart of an operation method of a test device according to an embodiment of the present invention.
[0012] Figure 4 is Figure 3 Detailed flowchart of step S308 of
[0013] Figure 5 Flowchart of an operation method of a test device according to another embodiment of the present invention.
[0014] Reference Numerals in the Drawings
[0015] 100: Test device
[0016] 110: First memory unit
[0017] 120: Control unit
[0018] 130: Second memory unit
[0019] 140: Testing machine
[0020] 150: Integrated circuit
[0021] S302~S308, S402~S406, S502~S504: Steps Detailed Description of the Invention
[0022] In the following embodiments listed, the same reference numerals will be used to represent the same or similar elements or components.
[0023] Figure 1 Schematic diagram of a test device according to an embodiment of the present invention. Please refer to Figure 1 , the test device 100 may include a first memory unit 110 and a control unit 120.
[0024] The first memory unit 110 stores a test program. In some embodiments, the first memory unit 110 may be a non-volatile memory (NVM), such as a flash memory or other suitable memory, but the embodiments of the present invention are not limited thereto. In some embodiments, the above test program is in the form of a test pattern file, for example.
[0025] In some embodiments, the first memory unit 110 may be an embedded memory. That is to say, the first memory unit 110 may be built into the control unit 120, as Figure 2A shown. Or, in some embodiments, the first memory unit 110 and the control unit 120 may be disposed in an integrated circuit (IC) 150, as Figure 2B shown. In addition, the first memory unit 110 may be a memory encapsulated inside the integrated circuit 150 through multi-chip package (MCP) technology. In this way, the expandability of test content and the convenience of file maintenance can be increased, without the need for additional manual programming and plugging / unplugging operations.
[0026] The control unit 120 may be coupled to the first memory unit 110. Further, the control unit 120 may be coupled to the first memory unit 110 through a serial peripheral interface (SPI), so that the control unit 120 can access data, instructions, etc. from / to the first memory unit 110 through this serial peripheral interface.
[0027] In this embodiment, the control unit 120 may have a second memory unit 130. That is to say, the second memory unit 130 may be a memory built into the control unit 120. In addition, the second memory unit 130 may provide a temporary storage space for data and instructions during the operation of the control unit 120. Moreover, the second memory unit 130 can also access data and instructions from / to the control unit 120 through the serial peripheral interface.
[0028] In some embodiments, the second memory unit 130 may be a volatile memory (VM), such as a random access memory (RAM), but the embodiments of the present invention are not limited thereto. In addition, the control unit 120 may be a microcontroller, but the embodiments of the present invention are not limited thereto.
[0029] In this embodiment, the control unit 120 can access the first memory unit 110 to read the test program stored in the first memory unit 110 from the first memory unit 110. Then, the control unit 120 can execute the above test program to perform a write / read test on the second memory unit 130 to generate a test result code. That is, the control unit 120 can load the test program read from the first memory unit 110 into the second memory unit 130 and execute it, so that the control unit 120 can perform a write / read test on the second memory unit 130 according to the test instructions of the above test program to generate a corresponding test result code.
[0030] In some embodiments, the above test program may include the address of the second memory unit 130, the write data corresponding to the address, and the preset data. In this embodiment, assume that the address of the second memory unit 130 is, for example, 0xD000 to 0xEFFF, the write data corresponding to the addresses 0xD000 to 0xEFFF is, for example, 0x5AA5, and the preset data is, for example, 0x5AA5. That is, when the control unit 120 executes the above test program, the control unit 120 can obtain the address 0xD000 to 0xEFFF of the second memory unit 130, the write data 0x5AA5 corresponding to the addresses 0xD000 to 0xEFFF, and the preset data 0x5AA5 from the test program.
[0031] Then, the control unit 120 can write the write data corresponding to the addresses 0xD000 to 0xEFFF to the addresses 0xD000 to 0xEFFF of the second memory unit 130 according to the addresses 0xD000 to 0xEFFF of the second memory unit 130. Then, the control unit 120 can read the read data corresponding to the above addresses 0xD000 to 0xEFFF from the above addresses 0xD000 to 0xEFFF. In this embodiment, the read data may be the same as or different from the write data, for example, 0x5AA5 or not 0x5AA5.
[0032] After that, the control unit 120 can compare the read data corresponding to the above addresses 0xD000 to 0xEFFF with the preset data 0x5AA5 to generate a test result code. That is, the control unit 120 can confirm whether the read data corresponding to the above addresses 0xD000 to 0xEFFF is the same as the preset data 0x5AA5 to generate a corresponding test result code.
[0033] For example, when the control unit 120 confirms that the read data corresponding to the above addresses 0xD000 to 0xEFFF is the same as the preset data 0x5AA5, the control unit 120 can generate a test result code such as "1111", indicating that the result of the write-read test of the second memory unit 130 is "pass". When the control unit 120 confirms that at least one of the read data corresponding to the above addresses 0xD000 to 0xEFFF is different from the preset data 0x5AA5, the control unit 120 can generate a test result code such as "0000", indicating that the result of the write-read test of the second memory unit 130 is "fail". In addition, the above test result codes of "1111" or "0000" are an implementation example of the present invention and are not used to limit the form of the embodiments of the present invention. The user can adjust the test result code generated by the control unit 120 according to their needs.
[0034] In addition, in some embodiments, after the control unit 120 generates the test result code, that is, after the test of the test device 100 is completed, the control unit 120 can clear the test program of the first memory unit 110 to meet the subsequent needs of updating or expanding the test, so as to increase the convenience of use.
[0035] In some embodiments, the test device 100 further includes a tester 140. The tester 140 can be coupled to the first memory unit 110 and the control unit 120. Further, the tester 140 can be coupled to the first memory unit 110 and the control unit 120 through a general-purpose input output (GPIO) interface, so that the tester 140 can output and receive signals and data with the first memory unit 110 and / or the control unit 120 through this general-purpose input output interface.
[0036] In this embodiment, the tester 140 can provide a test program and control the control unit 120 to write the test program into the first memory unit 110, so that the first memory unit 110 stores the above test program. In addition, the tester 140 can receive the test result code generated by the control unit 120 and generate a test result according to the above test result code. In this embodiment, the test result can include pass or fail.
[0037] For example, when the test machine 140 receives the test result code "1111" generated by the control unit 120, the test machine 140 can generate a test result of "Test Passed". Then, the test machine 140 can display this "Test Passed" test result, enabling the user to know that the test result of the second memory unit 130 is "Test Passed". When the test machine 140 receives the test result code "0000" generated by the control unit 120, the test machine 140 can generate a test result of "Test Failed". Then, the test machine 140 can display this "Test Failed" test result, enabling the user to know that the test result of the second memory unit 130 is "Test Failed".
[0038] In the overall operation of the test device 100, first, the user can operate the test machine 140 to cause the test machine 140 to provide a test program. Then, the test machine 140 can transmit the test program to the control unit 120 and control the control unit 120 to write the test program into the first memory unit 110 so that the first memory unit 110 stores the test program.
[0039] After that, the control unit 120 can read out the test program stored in the first memory unit 110 from the first memory unit 110. Then, the control unit 120 can load the read test program into the second memory unit 130 and execute it. Then, the control unit 120 can obtain the addresses 0xD000 - 0xEFFF of the second memory unit 130, the write data 0x5AA5 corresponding to the addresses 0xD000 - 0xEFFF, and the preset data 0x5AA5 from the test program.
[0040] Next, the control unit 120 can perform a write and read test on the second memory unit 130. That is, the control unit 120 can write the write data corresponding to the addresses 0xD000 - 0xEFFF into the addresses 0xD000 - 0xEFFF of the second memory unit 130 according to the addresses 0xD000 - 0xEFFF of the second memory unit 130. After that, the control unit 120 can read the read data corresponding to the addresses 0xD000 - 0xEFFF from the above addresses 0xD000 - 0xEFFF.
[0041] Next, the control unit 120 can compare the read data corresponding to the addresses 0xD000 - 0xEFFF with the preset data 0x5AA5 to confirm whether the read data is the same as the preset data 0x5AA5 and generate a corresponding test result code.
[0042] When the control unit 120 confirms that the read data corresponding to the above addresses 0xD000 to 0xEFFF is the same as the preset data 0x5AA5, the control unit 120 can generate a test result code such as "1111", indicating that the write-read test result of the second memory unit 130 is "test passed". Then, the control unit 120 can transmit this "1111" test result code to the tester 140 and clear the test program of the first memory unit 110. After that, the tester 140 can generate a "test passed" test result based on this "1111" test result code and display this "test passed" test result.
[0043] On the other hand, when the control unit 120 confirms that at least one of the read data corresponding to the above addresses 0xD000 to 0xEFFF is different from the preset data 0x5AA5, the control unit 120 can generate a test result code such as "0000", indicating that the write-read test result of the second memory unit 130 is "test failed". Then, the control unit 120 can transmit this "0000" test result code to the tester 140 and clear the test program of the first memory unit 110. After that, the tester 140 can generate a "test failed" test result based on this "0000" test result code and display this "test failed" test result.
[0044] Figure 3 It is a flowchart of an operation method of a test device according to an embodiment of the present invention. In step S302, a test program is stored in the first memory unit. In step S304, a control unit is provided, which has a second memory unit. In step S306, the control unit reads the test program. In step S308, the control unit executes the test program to perform a write-read test on the second memory unit to generate a test result code. In this embodiment, the first memory unit is, for example, built into the control unit, or the first memory unit and the control unit are, for example, provided on an integrated circuit.
[0045] In some embodiments, the test program, for example, includes the address of the second memory unit, the write data corresponding to the address, and the preset data. Additionally, the test program is, for example, in the form of a pattern file.
[0046] Figure 4 is Figure 3 A detailed flowchart of step S308. In step S402, the control unit writes the write data corresponding to the address to the address of the second memory unit according to the address of the second memory unit. In step S404, the control unit reads the read data corresponding to the above address from the above address. In step S406, the control unit compares the read data with the preset data to generate a test result code.
[0047] Figure 5 A flowchart of an operation method of a test device according to another embodiment of the present invention. In this embodiment, steps S302 to S308 are the same as or similar to steps S302 to S308 of Figure 3 and reference can be made to the description of the embodiment of Figure 3 , so details are not described herein again. In step S502, a test program is provided by a test machine, and the control unit is controlled to write the test program into the first memory unit. In step S504, the test result code is received by the test machine, and a test result is generated based on the test result code.
[0048] In summary, for the test device and its operation method disclosed by the present invention, the test program is stored in the first memory unit, the control unit reads the above test program from the first memory unit and executes the above test program to perform a write / read test on the second memory unit to generate a test result code, wherein the first memory unit is built in the control unit, or the first memory unit and the control unit are disposed on an integrated circuit. Additionally, in this embodiment, a test program is further provided by the test machine, and the control unit is controlled to write the test program into the first memory unit, and the test result code is received and a test result is generated based on the test result code. In this way, the expandability of test content and the convenience of file maintenance can be increased without additional manual programming and plugging / unplugging operations, and the convenience in use is also increased.
[0049] Although the present invention is disclosed as above with embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art within the technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the foregoing claims.
Claims
1. A testing device, characterized in that: include: A first memory unit storing a test program; as well as A control unit having a second memory unit, wherein the control unit reads the test program, executes the test program, and performs a write-read test on the second memory unit to generate a test result code; The first memory unit is built into the control unit, or the first memory unit and the control unit are arranged in an integrated circuit.
2. The testing device according to claim 1, characterized in that: The test program includes an address of the second memory unit, a write data corresponding to the address and a preset data.
3. The testing device according to claim 2, characterized in that: The control unit writes the write data corresponding to the address to the address of the second memory unit according to the address of the second memory unit, reads a read data corresponding to the address from the address, and compares the read data with the preset data to generate the test result code.
4. The testing device according to claim 1, characterized in that: The test program is in the form of a pattern file.
5. The testing device according to claim 1, characterized in that: Also includes: A test machine provides the test program, controls the control unit to write the test program into the first memory unit, receives the test result code, and generates a test result according to the test result code.
6. A method for operating a testing device, characterized in that: include: A test program is stored in a first memory unit; Providing a control unit having a second memory unit; reading the test program by the control unit; Executing the test program through the control unit to perform a write-read test on the second memory unit to generate a test result code; The first memory unit is built into the control unit, or the first memory unit and the control unit are arranged in an integrated circuit.
7. The operating method of the testing device according to claim 6, characterized in that: The test program includes an address of the second memory unit, a write data corresponding to the address and a preset data.
8. The operating method of the testing device according to claim 7, characterized in that: The step of executing the test program by the control unit to perform the write-read test on the second memory unit to generate the test result code includes: The control unit writes the write data corresponding to the address into the address of the second memory unit according to the address of the second memory unit; The control unit reads a read data corresponding to the address from the address; and The control unit compares the read data with the preset data to generate the test result code.
9. The operating method of the testing device according to claim 6, characterized in that: The test program is in the form of a pattern file.
10. The operating method of the testing device according to claim 6, characterized in that: Also includes: Providing the test program through a test machine, and controlling the control unit to write the test program into the first memory unit; and The test result code is received by the test machine, and a test result is generated according to the test result code.