Semiconductor processing technology and technology integrated cavity
By adopting an integrated process cavity in the semiconductor processing process, the continuous progress of CVD, PVD and Etch processes in the same cavity is solved, and the problems of high space occupation and low efficiency in the prior art are achieved, and efficient and low-cost semiconductor processing is achieved.
Patent Information
- Application Number
- CN202510288403.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-05-30
AI Technical Summary
In the existing semiconductor processing technology, the through-silicon technology (TSV) and glass through-silicon technology (TGV) processes require three independent cavity, resulting in high space occupation and cost, while frequent wafer transfers lead to inefficiency.
A semiconductor processing technology and process integrated cavity are adopted, and three processes (CVD, PVD, Etch) are implemented in the same process cavity. Through the shading component and contaminant cleaning steps, the continuity and efficiency of the process steps are achieved.
The process space is compressed, the number of wafer transfers is reduced, processing efficiency is improved, costs are reduced, and the target surface is kept clean.
Smart Images
Figure CN120072634A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor processing, and in particular to a semiconductor processing technology and a process integrated chamber. Background Art
[0002] In the power semiconductor processing technology, especially in the Through-Silicon Via (TSV) technology and the Through-Glass Via (TGV) technology, the process steps of etching (Etch), Chemical Vapor Deposition (CVD), and Physical Vapor Deposition (PVD) are sequentially performed on the wafer. These three processes require three independent chambers. The three independent chambers not only occupy more space but also have higher costs. In the continuous process, the wafers need to be continuously transferred among the three independent chambers, resulting in low efficiency. Summary of the Invention
[0003] Aiming at the deficiencies in the prior art, the present invention provides a semiconductor processing technology and a process integrated chamber. The three processes are implemented in the same process chamber, which compresses the required process space and eliminates the need for frequent wafer transfer. It can not only perform a single process step alone but also sequentially and continuously implement different sequences of process steps. Considering the compatibility of the three processes, this process also involves wafer masking and contaminant cleaning steps. The technical solution adopted by the present invention is as follows: A semiconductor processing technology, the process comprising: S1: Feeding the wafer into the process chamber; S2: Introducing a reaction gas into the process chamber to perform Process A. When there are process residues on the target surface after Process A is completed, masking the wafer, cleaning the residues on the target surface, and after the cleaning is completed, exposing the wafer; and / or, Introducing a reaction gas into the process chamber to perform Process B. When there are process residues on the target surface after Process B is completed, masking the wafer, cleaning the residues on the target surface, and after the cleaning is completed, exposing the wafer; and / or, Introducing a reaction gas into the process chamber to perform Process C. When there are process residues on the target surface after Process C is completed, masking the wafer, cleaning the residues on the target surface, and after the cleaning is completed, exposing the wafer; S3: Withdrawing the wafer from the process chamber.
[0004] Further, Process A is one of CVD, PVD, and Etch.
[0005] Further, Process B is one of CVD, PVD, and Etch.
[0006] Further, Process C is one of CVD, PVD, and Etch.
[0007] Further, the method for cleaning the residues on the target surface is as follows: introducing a reaction gas into the process chamber, inputting power to the target, and cleaning the residues on the target surface by means of PVD.
[0008] A semi-process integrated chamber includes: A process chamber for providing a process environment for the semiconductor processing technology; A shielding component for covering or exposing the wafer.
[0009] Further, a magnetic module, a target, a wafer stage, an RF shielding plate, and PIN pins are arranged in the process chamber; The magnetic module, the target, and the wafer stage are arranged at intervals from top to bottom in the process chamber; The target is electrically connected to a CVD power supply and a PVD power supply respectively. An air path channel is arranged in the target, and process gas diverges downward from the target through the air path channel; RF metal sheets and ESC metal sheets are arranged at intervals up and down in the wafer stage, and the wafer stage can approach or move away from the target in the vertical direction; The RF shielding plate is located below the magnetic module and completely covers the magnetic module; The PIN pins are located in the process chamber and can penetrate the wafer stage; when the wafer stage approaches the target, the PIN pins are recessed into the wafer stage, and the wafer is placed on the wafer stage; when the wafer stage moves away from the target, the PIN pins protrude from the wafer stage, and the wafer is placed on the PIN pins.
[0010] Further, the shielding component includes: A shielding plate having a first working position and a second working position; A shielding chamber communicating with the process chamber; A displacement driving member for driving the shielding plate to switch between the first working position and the second working position; Wherein, when the shielding plate is in the first working position, the shielding plate is located in the shielding chamber, the wafer stage is opposite to the shielding plate, and the shielding plate covers the wafer; when the shielding plate is in the second working position, the shielding plate is located in the process chamber, the shielding plate covers the wafer stage, the wafer stage is separated from the shielding plate, and the shielding plate exposes the wafer.
[0011] Further, a position detecting member is arranged in the shielding chamber. When the shielding plate is in the first working position, the position detecting member senses the shielding plate.
[0012] Further, An intake pipe connected to the air path channel is arranged on the process chamber, and the intake end of the intake pipe is configured with a plurality of intake branches; and / or, A target coolant channel is provided inside the target, and the end of the target coolant channel is used to configure a target coolant connector.
[0013] Advantages of the present invention: The three processes are implemented in the same process chamber. Not only can a certain process step be carried out individually, but also different sequential process steps can be achieved sequentially and continuously. It also involves wafer shielding and contaminant cleaning steps to keep the surface of the target clean. The integrated chamber structure compresses the required process space, eliminates the need for frequent wafer transfer, saves floor space, avoids temperature difference fluctuations caused by frequent wafer transfer, and improves wafer processing efficiency. Description of the Drawings
[0014] Figure 1 It is a schematic diagram of the structural composition of the process chamber.
[0015] Figure 2 It is a sectional view of the process chamber from a half-sectional perspective.
[0016] Figure 3 It is a schematic diagram of the structure of the target coolant channel.
[0017] Figure 4 It is a schematic diagram of the structural composition of the shielding component.
[0018] Figure 5 It is a sectional view of the wafer stage from a half-sectional perspective.
[0019] Figure 6 It is an assembly drawing of the ceramic seat, RF wire harness, ESC wire harness, and ventilation pipe.
[0020] In the figure: 10 - process chamber, 10a - vacuum pumping port, 10b - wafer inlet / outlet, 10c - PIN socket, 11 - magnetic module, 12 - target, 121 - gas path channel, 122 - target coolant channel, 13 - wafer stage, 131 - ceramic seat, 131a - RF metal sheet, 131b - ESC metal sheet, 131c - stage coolant channel, 131d - inert gas channel, 131e - groove, 131f - air outlet hole, 131g - bump, 132 - RF wire harness, 133 - ESC wire harness, 134 - stage coolant connector, 135 - ventilation pipe, 14 - RF shielding plate, 15 - inlet pipe, 16 - PIN pin, 17 - CVD power supply, 18 - PVD power supply, 19 - target coolant connector, 20 - shielding component, 210 - shielding plate, 220 - shielding chamber, 230 - position detection part, 240 - displacement driving part. Detailed Embodiments
[0021] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0022] This application first proposes a semiconductor processing technology, and the technology includes: S1: Feed the wafer into the process chamber 10; S2: Introduce a reaction gas into the process chamber 10 to perform Process A. When there are process residues on the surface of the target 12 after Process A is completed, cover the wafer, clean the residues on the surface of the target, and after cleaning is completed, expose the wafer; and / or, Introduce a reaction gas into the process chamber 10 to perform Process B. When there are process residues on the surface of the target 12 after Process B is completed, cover the wafer, clean the residues on the surface of the target, and after cleaning is completed, expose the wafer; and / or, Introduce a reaction gas into the process chamber 10 to perform Process C. When there are process residues on the surface of the target 12 after Process C is completed, cover the wafer, clean the residues on the surface of the target, and after cleaning is completed, expose the wafer; S3: Withdraw the wafer from the process chamber 10.
[0023] It is easy to understand that within the process chamber 10, several process forms such as Process A, Process B, Process C, Process A + Process B, Process A + Process C, Process B + Process C, and Process A + Process B + Process C can be realized. Therefore, when the three processes are implemented in the same process chamber, not only can a certain process step be carried out alone, but also process steps in different sequences can be realized sequentially and continuously, which compresses the required process space and eliminates the need to frequently transfer the wafer, effectively improving the wafer processing efficiency.
[0024] In one embodiment, Process A is one of CVD, PVD, and Etch; Process B is one of CVD, PVD, and Etch; Process C is one of CVD, PVD, and Etch.
[0025] As the first specific embodiment of the semiconductor processing technology, step S2 only includes Process A, and Process A is the Etch process. Therefore, the specific process of the semiconductor processing technology is as follows: S1: Feed the wafer into the process chamber 10; S2: Introduce a reaction gas into the process chamber 10 to perform the Etch process; S3: Withdraw the wafer from the process chamber 10.
[0026] As the second specific embodiment of the semiconductor processing technology, step S2 includes process A + process B, where process A is the CVD process and process B is the PVD process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into process chamber 10; S2: Introduce reaction gas into process chamber 10 to perform the CVD process. When there are process residues on the surface of target 12 after the CVD process is completed, cover the wafer, clean the residues on the surface of the target. After the cleaning is completed, expose the wafer; Introduce reaction gas into process chamber 10 to perform the PVD process; S3: Withdraw the wafer from process chamber 10.
[0027] As the third specific embodiment of the semiconductor processing technology, step S2 includes process A + process B, where process A is the PVD process and process B is the CVD process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into process chamber 10; S2: Introduce reaction gas into process chamber 10 to perform the PVD process; Introduce reaction gas into process chamber 10 to perform the CVD process; S3: Withdraw the wafer from process chamber 10.
[0028] As the fourth specific embodiment of the semiconductor processing technology, step S2 includes process A + process C, where process A is the Etch process and process B is the PVD process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into process chamber 10; S2: Introduce reaction gas into process chamber 10 to perform the Etch process. When there are process residues on the surface of target 12 after the Etch process is completed, cover the wafer, clean the residues on the surface of the target. After the cleaning is completed, expose the wafer; Introduce reaction gas into process chamber 10 to perform the PVD process; S3: Withdraw the wafer from process chamber 10.
[0029] As the fifth specific embodiment of the semiconductor processing technology, step S2 includes process A + process C, where process A is the PVD process and process B is the Etch process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into process chamber 10; S2: Introduce reaction gas into process chamber 10 to perform the PVD process; Introduce reaction gas into process chamber 10 to perform the Etch process; S3: Withdraw the wafer from process chamber 10.
[0030] According to the above second to fifth embodiments, only when CVD or Etch is performed first and then PVD is carried out, is it necessary to cover the wafer and clean the residues on the surface of the target 12 to keep the surface of the target 12 clean and ensure the efficiency of PVD.
[0031] As the sixth specific embodiment of the semiconductor processing technology, step S2 includes process A + process B + process C, where process A is the CVD process, process B is the Etch process, and process C is the PVD process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into the process chamber 10; S2: Introduce reaction gas into the process chamber 10 to perform the CVD process; Introduce reaction gas into the process chamber 10 to perform the Etch process. When there are process residues on the surface of the target 12 after the Etch process is completed, cover the wafer, clean the residues on the surface of the target, and after the cleaning is completed, expose the wafer; Introduce reaction gas into the process chamber 10 to perform the PVD process; S3: Withdraw the wafer from the process chamber 10.
[0032] As the seventh specific embodiment of the semiconductor processing technology, step S2 includes process A + process B + process C, where process A is the PVD process, process B is the CVD process, and process C is the Etch process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into the process chamber 10; S2: Introduce reaction gas into the process chamber 10 to perform the PVD process; Introduce reaction gas into the process chamber 10 to perform the CVD process; Introduce reaction gas into the process chamber 10 to perform the Etch process; S3: Withdraw the wafer from the process chamber 10.
[0033] As the eighth specific embodiment of the semiconductor processing technology, step S2 includes process A + process B + process C, where process A is the Etch process, process B is the PVD process, and process C is the CVD process. Therefore, the semiconductor processing technology process is specifically as follows: S1: Feed the wafer into the process chamber 10; S2: Introduce reaction gas into the process chamber 10 to perform the Etch process. When there are process residues on the surface of the target 12 after the Etch process is completed, cover the wafer, clean the residues on the surface of the target, and after the cleaning is completed, expose the wafer; Introduce reaction gas into the process chamber 10 to perform the PVD process; Introduce reaction gas into the process chamber 10 to perform the CVD process; S3: Withdraw the wafer from the process chamber 10.
[0034] As the ninth specific embodiment of the semiconductor processing technology, step S2 includes Process A + Process B + Process C, where Process A is the Etch process, Process B is the CVD process, and Process C is the PVD process. Therefore, the specific semiconductor processing technology process is as follows: S1: Feed the wafer into process chamber 10; S2: Introduce reaction gas into process chamber 10 to perform the Etch process; Introduce reaction gas into process chamber 10 to perform the PVD process. When there are process residues on the surface of the target 12 after the PVD process is completed, cover the wafer, clean the residues on the surface of the target, and after the cleaning is completed, expose the wafer; Introduce reaction gas into process chamber 10 to perform the CVD process; S3: Withdraw the wafer from process chamber 10.
[0035] In the above semiconductor processing technology, the method for cleaning the residues on the surface of the target 12 is: introduce reaction gas into process chamber 10 and input power to the target 12, and clean the residues on the surface of the target by the PVD method.
[0036] Please refer to the attached Figure 1 - attached Figure 6 This application also proposes a semi-process integrated chamber, including: a process chamber 10 for providing a process environment for the above semiconductor processing technology; a shielding component 20 for covering or exposing the wafer. The above processing technology cooperates with the structures of the process chamber 10 and the shielding component 20 to complete different process steps of the wafer in the process chamber 10.
[0037] The specific structure of the process chamber 10 is as follows: a magnetic module 11, a target 12, a wafer stage 13, an RF shielding plate 14, and PIN pins 16 are arranged in the process chamber 10; the magnetic module 11, the target 12, and the wafer stage 13 are arranged at intervals from top to bottom in the process chamber 10; the target 12 is electrically connected to a CVD power supply 17 and a PVD power supply 18 respectively, and an air passage 121 is arranged in the target 12, and process gas diverges downward from the target 12 through the air passage 121; RF metal sheets 131a and ESC metal sheets 131b are arranged at intervals up and down in the wafer stage 13, and the wafer stage 13 can move closer to or away from the target 12 in the vertical direction; the RF shielding plate 14 is located below the magnetic module 11 and completely covers the magnetic module 11; the PIN pins 16 are located in the process chamber 10 and can penetrate the wafer stage 13; when the wafer stage 13 moves closer to the target 12, the PIN pins 16 are recessed into the wafer stage 13, and the wafer is placed on the wafer stage 13; when the wafer stage 13 moves away from the target 12, the PIN pins 16 protrude from the wafer stage 13, and the wafer is placed on the PIN pins 16.
[0038] First, please refer to the attached Figure 1 and the attached Figure 2 , a vacuum pumping port 10a and a wafer inlet / outlet 10b are provided on the process chamber 10; the vacuum pumping port 10a is used to connect to a vacuum pump to form a vacuum inside the process chamber 10, providing a vacuum environment for the three processes of CVD, PVD, and Etch. The height of the wafer inlet / outlet 10b corresponds to that of the wafer stage 13. Thus, when the wafer stage 13 moves away from the target 12, the wafer is seated on the PIN pins 16, and the wafer can enter and exit the process chamber 10 through the wafer inlet / outlet 10b.
[0039] Second, please refer to the attached Figure 2 , the outlet of the gas path channel 121 on the target 12 is a number of air holes evenly distributed at the bottom of the target 12. The process gases required for the three processes of CVD, PVD, and Etch diverge uniformly downward from the above-mentioned air holes.
[0040] In one embodiment, the CVD power supply 17 and the PVD power supply 18 are respectively located on the upper and lower sides of the target 12 and are installed on the side of the process chamber 10. The CVD power supply 17 and the PVD power supply 18 are simultaneously connected to a 400 kHz / 13.56 MHz frequency mixing matcher. The wafer stage 13 is connected to a 27 MHz / 2 MHz power supply, or is connected to a 27 MHz / 2 MHz power supply and a 400 kHz / 13.56 MHz frequency mixing matcher; since only one of the processes of CVD, PVD, and Etch can be carried out in the process chamber 10 at the same time, using the same frequency mixing matcher can save costs and improve control accuracy. The structures of the magnetic module 11, the target 12, and the PIN pins 16 can be arranged with reference to the prior art and will not be elaborated here.
[0041] In this embodiment, the CVD process is briefly described as follows: The CVD power supply 17 is connected to the metal plate on the back (i.e., the upper surface) of the target 12. The reaction gas required for CVD is introduced into the gas path channel 121. An electric field is generated by the RF metal thin plate 131a to ionize gas molecules or atoms to form plasma. The reaction gas collides with the plasma to generate a large number of active free radicals, which react and form a film on the surface of the wafer.
[0042] In this embodiment, the PVD process is briefly described as follows: The PVD power supply 18 energizes the target 12 through a 400 kHz / 13.56 MHz frequency mixing matcher matching network. The reaction gas (argon gas) required for PVD is introduced through the gas path channel 121. The magnetic module 11 enables electrons to move in a circular motion on the surface of the target in an approximate cycloid form. The movement path of the electrons is confined within the plasma region near the surface of the target, and a large number of Ar are ionized in this region to bombard the target 12, improving the metal atom deposition efficiency; the RF shielding plate 14 is grounded so that the induced current can be conducted away through the RF shielding plate 14 to shield the interference of the power supply on the magnetic module 11; without the RF shielding plate 14, the induced electric field of the RF energy will affect the magnetic module 11, thereby affecting wafer processing.
[0043] In a specific embodiment, the RF shielding plate 14 covers the target 12 and is connected to the process chamber 10 through a bolt connection process.
[0044] In this embodiment, the Etch process is briefly described as follows: The reaction gas required for Etch is introduced through the gas path channel 121. The RF metal sheet 131a generates an electric field to ionize gas molecules or atoms to form plasma. The ions and free radicals in these plasmas are accelerated under the action of the electric field and bombard the surface of the wafer.
[0045] In one embodiment, as shown in the appendix Figure 2 The process chamber 10 is provided with an intake pipe 15 connected to the gas path channel 121, and the intake end of the intake pipe 15 is configured with a plurality of intake branches. In fact, sharing a gas path channel 121 for the three process selections can simplify the structural design of the target 12. For example, the intake pipe 15 can directly select a four-way pipe joint, and one of the joints is threadedly connected to the inlet of the gas path channel 121.
[0046] In one embodiment, as shown in the appendix Figure 2 and the appendix Figure 3 The target 12 is internally provided with a target cooling channel 122, and the end of the target cooling channel 122 is used to configure a target coolant joint 19. The target coolant joint 19 is connected to an external water cooling system, and the cooling water circulates inside and outside the target 12 along the target cooling channel 122 to cool the target 12. The path shape of the target cooling channel 122 is arranged according to the actual situation and is not limited to the path in the appendix Figure 3 shown.
[0047] The specific structure of the shielding assembly 20 is as follows: the shielding assembly 20 includes: a shielding plate 210, having a first working position and a second working position; a shielding cavity 220, which is connected to the process cavity 10; wherein, when the shielding plate 210 is in the first working position, the shielding plate 210 is located in the shielding cavity 220, the wafer stage 13 is opposite to the shielding plate 210, and the shielding plate 210 covers the wafer; when the shielding plate 210 is in the second working position, the shielding plate 210 is located in the process cavity 10, the shielding plate 210 covers the wafer stage 13, the wafer stage 13 is separated from the shielding plate 210, and the shielding plate 210 exposes the wafer.
[0048] It should be noted that the shielding assembly 20 plays a very important role in the process chamber 10. Because during the CVD and Etch processes, the deposits will adhere to the surface of the target material 12 and contaminate the target material 12. Therefore, if the PVD process is performed after the CVD and Etch, the shielding plate 210 is moved from the first working position to the second working position, so that the shielding plate 210 shields the wafer, and then the target material 12 is bombarded with argon ions for a period of time to clean the contaminants on the surface of the target material, and then the shielding plate 210 is moved from the second working position to the first working position to continue the PVD process steps.
[0049] Furthermore, when the shielding plate 210 is in the second working position, the axis thereof coincides with the axis of the wafer stage 13 , and the circular area of the shielding plate 210 is larger than the circular area of the wafer, so that the shielding plate 210 completely shields the wafer.
[0050] In order to realize the automatic switching of the position of the shielding plate 210, as shown in the attached Figure 2 and 4 As shown, the shielding assembly 20 further includes a displacement driving member 240, and the displacement driving member 240 is used to drive the shielding plate 210 to switch between the first working position and the second working position.
[0051] For example, the displacement drive 240 is a linear cylinder (not shown), which is arranged along the radial direction (i.e., horizontal direction) of the process chamber 10. The output end of the linear cylinder is connected to the edge of the baffle plate 210. The baffle plate 210 is driven to translate in the horizontal plane through the extension and retraction of the output end of the linear cylinder, thereby switching its position back and forth between the process chamber 10 and the baffle chamber 220.
[0052] For another example, the displacement driving member 240 is a rotary cylinder, which is arranged along the axial direction (i.e., the vertical direction) of the process chamber 10, and the output end of the rotary cylinder is connected to the surface of the baffle plate 210, and the axis of the baffle plate 210 is eccentrically arranged with the axis of the output end of the rotary cylinder. The baffle plate 210 is driven to swing in an arc in the horizontal plane through the telescopic rotation of the output end of the rotary cylinder, thereby switching its position back and forth between the process chamber 10 and the baffle chamber 220.
[0053] For another example, the displacement driving member 240 is a driving motor, which is arranged along the axial direction (i.e., the vertical direction) of the process chamber 10. The output end of the driving motor is connected to the surface of the shielding plate 210, and the axis of the shielding plate 210 is eccentrically arranged with the axis of the output end of the driving motor. By the forward and reverse rotation of the output end of the driving motor, the shielding plate 210 is driven to swing in an arc in the horizontal plane, so as to realize the switching of its position back and forth between the process chamber 10 and the shielding chamber 220.
[0054] In one embodiment, as shown in the attached Figure 2 and the attached Figure 4 figure, the shielding chamber 220 is detachably connected to the process chamber 10. By disassembling the shielding chamber 220, the shielding plate 210 is more closely exposed, which is convenient for replacing or maintaining the shielding plate 210 and cleaning the surface of the shielding plate 210. In another embodiment, the shielding chamber 220 and the process chamber 10 are of an integral structure; the integration of the process chamber 10 and the shielding chamber 220 will be more convenient for mold design, and the integral formed structure has higher strength.
[0055] In a specific embodiment, the shielding chamber 220 is of a crescent structure, and its end is configured as a rectangular frame. The rectangular surface is attached to the side wall of the process chamber 10 and fixed by bolts, so as to realize the detachable connection between the shielding chamber 220 and the process chamber 10; under this structure, the displacement distance of the shielding plate 210 is small, and part of the space of the process chamber 10 can be utilized, thereby reducing the use of the external space of the process chamber 10 and making the overall structure more compact.
[0056] In one embodiment, as shown in the attached Figure 2 and the attached Figure 4 figure, a position detection member 230 is arranged in the shielding chamber 220. When the shielding plate 210 is in the first working position, the position detection member 230 senses the shielding plate 210. The position detection member 230 is specifically a position sensor, and its signal transmitting end and signal receiving end are respectively on the upper and lower surfaces of the shielding chamber 220. When the shielding plate 210 enters the shielding chamber 220 and separates the signal transmitting end and the signal receiving end, the position detection member 230 sends a signal that the shielding plate 210 is in place to the control system.
[0057] In the present application, please refer to the attached Figure 2 and the attached Figure 5, the upper part of the wafer stage 13 is configured as a ceramic base 131, and the RF metal thin plate 131a and the ESC metal thin plate 131b are respectively embedded in the ceramic base 131. Utilizing the insulating property of the ceramic base 131, the RF metal thin plate 131a and the ESC metal thin plate 131b are embedded in the ceramic base 131 in parallel and at intervals, so that the RF metal thin plate 131a and the ESC metal thin plate 131b do not interfere with each other and short circuits are avoided. The RF metal thin plate 131a is energized to provide RF power to meet the requirements of PVD, CVD, and Etch processes, and the ESC metal thin plate 131b realizes the electrostatic adsorption function to fix the wafer on the surface of the wafer stage 13. In addition, a heating wire is provided inside the wafer stage 13 for heating the wafer.
[0058] Further, in order to concentrate the wire harness arrangement of the wafer stage 13 for convenient wire harness arrangement, please refer to the attached Figure 5 and the attached Figure 6 , the RF metal thin plate 131a is connected to the RF wire harness 132, the ESC metal thin plate 131b is connected to the ESC wire harness 133, and one end of the RF wire harness 132 and one end of the ESC wire harness 133 respectively extend out from below the wafer stage 13.
[0059] In one embodiment, as shown in the attached Figure 5 and the attached Figure 6 , an inert gas channel 131d is provided inside the ceramic base 131, the inert gas channel 131d is connected to a ventilation pipe 135, and a groove 131e is provided at the top of the ceramic base 131. A number of air outlet holes 131f communicating with the inert gas channel 131d are distributed in the groove 131e. By introducing hot inert gas (argon gas) through the ventilation pipe 135, the inert gas flows from the inert gas channel 131d to the groove 131e, uniformly contacts the surface of the wafer along the groove 131e, and finally enters the process chamber 10 from the edge of the wafer, and the surface of the wafer is heated by heat exchange.
[0060] In a specific embodiment, the surface of the ceramic base 131 has a number of bumps 131g. When the wafer is placed on the ceramic base 131, it is supported by the bumps 131g, ensuring a certain gap between the wafer and the groove 131e. In this structure, even if the coverage area of the groove 131e is smaller than the circular area of the wafer, it will not affect the smooth divergence of the inert gas to the edge of the wafer and its departure from the ceramic base 131.
[0061] In one embodiment, as shown in the attached Figure 5 and the attached Figure 6As shown, a stage cooling channel 131c is provided inside the ceramic base 131, and the end of the stage cooling channel 131c is used to configure a stage coolant joint 134. The stage coolant joints 134 at both ends of the stage cooling channel 131c are connected to a cooling water system to realize the internal and external circulation of cooling water in the stage cooling channel 131c, and the wafer stage 13 is cooled by heat exchange.
[0062] In one embodiment, please refer to the attached Figure 2 , a PIN pin base 10c is provided at the bottom inside the process chamber 10, and the PIN pin 16 is installed on the PIN pin base 10c; specifically, the inner diameter of the PIN pin base 10c is smaller than the diameter of the wafer stage 13. The PIN pin base 10c not only facilitates the positioning of the installation position of the PIN pin 16, but also can limit the lowest displacement point of the wafer stage 13.
[0063] In summary, the required process space is compressed and there is no need to transfer wafers frequently. It can not only perform a certain process step alone, but also sequentially and continuously implement process steps in different orders, achieving continuous high efficiency, low cost, and low space occupancy. In the TSV and TGV processes, it can sequentially and continuously implement Etch, CVD, and PVD, and is compatible and adapted to the TSV and TGV process flows.
[0064] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and are not restrictive. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.
Claims
1. A semiconductor processing technology, characterized in that: The process comprises: S1: Wafer is fed into the process chamber; S2: introducing reaction gas into the process chamber to perform process A. When process A is completed and process residues exist on the surface of the target material, covering the wafer and cleaning the residues on the surface of the target material. After cleaning, exposing the wafer; and / or, Introducing reaction gas into the process chamber to perform process B. When process B is completed and process residues exist on the surface of the target material, covering the wafer, cleaning the residues on the surface of the target material, and exposing the wafer after cleaning; and / or, A reaction gas is introduced into the process chamber to perform a C process. When the C process is completed and there are process residues on the surface of the target material, the wafer is covered and the residues on the surface of the target material are cleaned. After the cleaning is completed, the wafer is exposed; S3: The wafer evacuates the process chamber.
2. The semiconductor processing method according to claim 1, wherein: The A process is one of CVD, PVD and Etch.
3. The semiconductor processing method according to claim 1, wherein: The B process is one of CVD, PVD, and Etch.
4. The semiconductor processing method according to claim 1, wherein: The C process is one of CVD, PVD, and Etch.
5. The semiconductor processing process according to claim 1, characterized in that: The method of cleaning the residues on the surface of the target material is: introducing reaction gas into the process chamber, inputting power to the target material, and cleaning the residues on the surface of the target material by a PVD method.
6. A semi-process integrated chamber, characterized in that: include: A process chamber (10), used for providing a process environment for the semiconductor processing process according to any one of claims 1 to 5; The shielding component (20) is used to cover or expose the wafer.
7. The semi-process integrated chamber according to claim 6, characterized in that: The process chamber (10) is provided with a magnetic module (11), a target material (12), a wafer carrier (13), an RF shielding plate (14), and a PIN needle (16); The magnetic module (11), the target material (12), and the wafer carrier (13) are arranged in the process chamber (10) from top to bottom at intervals; The target material (12) is electrically connected to a CVD power supply (17) and a PVD power supply (18), respectively; a gas path channel (121) is arranged inside the target material (12), and a process gas is emitted toward the bottom of the target material (12) via the gas path channel (121); An RF metal sheet (131a) and an ESC metal sheet (131b) are arranged in an upper and lower interval in the wafer carrier (13), and the wafer carrier (13) can approach or move away from the target material (12) in a vertical direction; The RF shielding plate (14) is located on the lower side of the magnetic module (11) and completely covers the magnetic module (11); The PIN needle (16) is located in the process chamber (10) and is capable of penetrating the wafer carrier (13); when the wafer carrier (13) is close to the target material (12), the PIN needle (16) is hidden in the wafer carrier (13), and the wafer is seated on the wafer carrier (13); when the wafer carrier (13) is away from the target material (12), the PIN needle (16) extends out of the wafer carrier (13), and the wafer is seated on the PIN needle (16).
8. The semi-process integrated chamber according to claim 7, characterized in that: The shielding component (20) comprises: The shielding plate (210) has a first working position and a second working position; A shielding chamber (220) communicated with the process chamber (10); A displacement driving member (240) used for driving the shielding plate (210) to switch between a first working position and a second working position; When the shielding plate (210) is in the first working position, the shielding plate (210) is located in the shielding cavity (220), the wafer carrier (13) is opposite to the shielding plate (210), and the shielding plate (210) covers the wafer; when the shielding plate (210) is in the second working position, the shielding plate (210) is located in the process cavity (10), the shielding plate (210) covers the wafer carrier (13), the wafer carrier (13) is separated from the shielding plate (210), and the shielding plate (210) exposes the wafer.
9. The semi-process integrated chamber according to claim 8, characterized in that: A position detection component (230) is provided in the shielding cavity (220), and when the shielding plate (210) is in the first working position, the position detection component (230) senses the shielding plate (210).
10. The semi-process integrated chamber according to claim 7, characterized in that: The process chamber (10) is provided with an air intake pipe (15) connected to the air passage (121), and an air intake end of the air intake pipe (15) is configured as a plurality of air intake branches; and / or, A target material cooling channel (122) is provided inside the target material (12), and an end of the target material cooling channel (122) is used to configure a target material cooling liquid connector (19).