Semiconductor structure and manufacturing method of semiconductor structure

Abstract

The invention provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure comprises a first lead frame, a chip, a second lead frame and a plastic packaging layer. The first lead frame comprises a first conductive part and at least one first pin connected with the first conductive part. The chip is mounted on the first conductive part and comprises a first surface and a second surface which are opposite to each other, the first surface is provided with a first electrode, and the second surface is provided with a second electrode; the first lead frame comprises a first conductive part and at least one first pin connected with the first conductive part, the first surface faces the first conductive part, the first electrode is electrically connected with the first conductive part, the second lead frame comprises a second conductive part and at least one second pin connected with the second conductive part, and the second conductive part is located on the side, away from the first conductive part, of the chip and electrically connected with the second electrode. The plastic packaging layer packages the first lead frame, the chip and the second lead frame, the surface, away from the chip, of the first conductive part and the surface, away from the chip, of the second conductive part are exposed out of the plastic packaging layer, and at least parts of the first pin and the second pin are exposed out of the plastic packaging layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Common semiconductor package structures, such as chip package structures, include chips, lead frames, bonding wires, and plastic encapsulation layers. The lead frame includes a base island and pins located on the side of the base island. The chip is mounted on the base island, and electrodes provided on the surface of the chip away from the base island are electrically connected to the lead frame through bonding wires. The plastic encapsulation layer encapsulates the chip, the lead frame, and the bonding wires, and the surface of the base island away from the chip is exposed from the plastic encapsulation layer for heat dissipation.

[0003] The existing semiconductor structure has the problem of poor heat dissipation effect, which affects the performance of the semiconductor structure. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor structure and a manufacturing method thereof.

[0005] In a first aspect of the embodiments of this application, a semiconductor structure is provided. The semiconductor structure includes:

[0006] A first lead frame, including a first conductive part and at least one first pin, the first pin being located on the side of the first conductive part and connected to the first conductive part;

[0007] A chip, mounted on the first conductive part; the chip includes opposite first and second surfaces, a first electrode is provided on the first surface, and a second electrode is provided on the second surface; the first surface faces the first conductive part, and the first electrode is electrically connected to the first conductive part;

[0008] A second lead frame, including a second conductive part and at least one second pin, the second pin being located on the side of the second conductive part and connected to the second conductive part; the second conductive part is located on the side of the chip away from the first conductive part and is electrically connected to the second electrode;

[0009] A plastic encapsulation layer, encapsulating the first lead frame, the chip, and the second lead frame, the surfaces of the first conductive part away from the chip and the second conductive part away from the chip are respectively exposed from the plastic encapsulation layer, and at least part of the first pin and the second pin are exposed from the plastic encapsulation layer.

[0010] In one embodiment, the second pin extends towards the first conductive part, and the end of the first pin away from the surface of the second conductive part, the end of the second pin away from the surface of the second conductive part, and the surface of the first conductive part away from the second conductive part are in the same plane; or,

[0011] The first pin extends towards the second conductive part, and the end of the first pin, the end of the second pin, and the surface of the second conductive part away from the first conductive part are in the same plane, with the end of the first pin being away from the surface of the first conductive part and the end of the second pin being away from the surface of the first conductive part.

[0012] In one embodiment, two second electrodes are provided on the second surface. The second conductive part includes a first sub-conductive part and a second sub-conductive part which are spaced apart. The first sub-conductive part and the second sub-conductive part are respectively electrically connected to different second electrodes. The semiconductor structure further includes a conductive structure between the first sub-conductive part and the second electrode, and a conductive structure between the second sub-conductive part and the second electrode. The material of the conductive structure is solder. The first sub-conductive part and the second sub-conductive part are respectively welded to the conductive structure.

[0013] In one embodiment, the distance between the first sub-conductive part and the second sub-conductive part is greater than or equal to 500 μm.

[0014] In one embodiment, two second electrodes are provided on the second surface. The second conductive part includes a first sub-conductive part and a second sub-conductive part which are spaced apart. The second lead frame includes a plurality of second pins. The second lead frame further includes a first connection part and a second connection part. The first connection part is located between the plurality of second pins and the first sub-conductive part, and is respectively connected to the plurality of second pins and the first sub-conductive part. The arrangement direction of the plurality of second pins connected to the first connection part is parallel to the extension direction of the first connection part. The second connection part is located between the plurality of second pins and the second sub-conductive part, and is respectively connected to the plurality of second pins and the second sub-conductive part. The arrangement direction of the plurality of second pins connected to the second connection part is parallel to the extension direction of the second connection part.

[0015] In the extension direction of the first connection part, the size of the first connection part is greater than the size of the first sub-conductive part; in the extension direction of the second connection part, the size of the second connection part is greater than the size of the second sub-conductive part; or, in the extension direction of the first connection part, the size of the first sub-conductive part is greater than or equal to the size of the first connection part; in the extension direction of the second connection part, the size of the second sub-conductive part is greater than or equal to the size of the second connection part.

[0016] In one embodiment, the orthographic projection of the chip on the surface of the first conductive part facing the chip entirely falls on the first conductive part, and the area of the surface of the first conductive part facing the chip is greater than the area of the orthographic projection of the chip on the surface of the first conductive part facing the chip.

[0017] In a second aspect of the embodiments of the present application, a manufacturing method of a semiconductor structure is provided. The manufacturing method includes:

[0018] Providing a first lead frame, the first lead frame including a first conductive portion and at least one first lead, the first lead being located at a side portion of the first conductive portion and connected to the first conductive portion;

[0019] Mounting a chip on the first conductive portion; the chip includes an opposite first surface and a second surface, the first surface is provided with a first electrode, and the second surface is provided with a second electrode; the first surface faces the first conductive portion, and the first electrode is electrically connected to the first conductive portion;

[0020] Providing a second lead frame, the second lead frame including a second conductive portion and at least one second lead, the second lead being located at a side portion of the second conductive portion and connected to the second conductive portion; disposing the second conductive portion on a side of the chip away from the first lead frame, and electrically connecting the second conductive portion to the second electrode;

[0021] Forming a plastic encapsulation layer, the plastic encapsulation layer encapsulating the first lead frame, the chip, and the second lead frame, a surface of the first conductive portion away from the chip and a surface of the second conductive portion away from the chip are exposed from the plastic encapsulation layer, and at least a part of the first lead and the second lead are exposed from the plastic encapsulation layer.

[0022] In one embodiment, two second electrodes are provided on the second surface, and the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion that are spaced apart; before or after mounting the chip on the first conductive portion, the manufacturing method further includes: respectively providing a conductive structure on each of the second electrodes, and the material of the conductive structure is solder;

[0023] The disposing the second conductive portion on a side of the chip away from the first lead frame and electrically connecting the second conductive portion to the second electrode includes:

[0024] Disposing the second conductive portion on a side of the chip away from the first lead frame, and respectively soldering the first sub-conductive portion and the second sub-conductive portion to the conductive structure.

[0025] In one embodiment, after forming the encapsulation layer, the method for manufacturing the semiconductor structure further includes: bending the first pin and the second pin so that the second pin extends toward the first conductive portion, and the end of the first pin is away from the surface of the second conductive portion, the end of the second pin is away from the surface of the second conductive portion, and the surface of the first conductive portion away from the second conductive portion are in the same plane; or,

[0026] After forming the encapsulation layer, the method for manufacturing the semiconductor structure further includes: bending the first pin and the second pin so that the first pin extends toward the second conductive portion, the end of the first pin is away from the surface of the first conductive portion, the end of the second pin is away from the surface of the first conductive portion, and the surface of the second conductive portion away from the first conductive portion are in the same plane.

[0027] In one embodiment, two second electrodes are provided on the second surface, and the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion arranged at intervals; the second lead frame includes a plurality of second pins; the second lead frame further includes a first connection portion and a second connection portion; the first connection portion is located between the second pin and the first sub-conductive portion and is connected to the plurality of second pins and the first sub-conductive portion respectively, and the arrangement direction of the plurality of second pins connected to the first connection portion is parallel to the extension direction of the first connection portion; the second connection portion is located between the second pin and the second sub-conductive portion and is connected to the plurality of second pins and the second sub-conductive portion respectively, and the arrangement direction of the plurality of second pins connected to the second connection portion is parallel to the extension direction of the second connection portion;

[0028] In the extension direction of the first connection portion, the size of the first connection portion is larger than the size of the first sub-conductive portion; in the extension direction of the second connection portion, the size of the second connection portion is larger than the size of the second sub-conductive portion; or, in the extension direction of the first connection portion, the size of the first sub-conductive portion is larger than or equal to the size of the first connection portion; in the extension direction of the second connection portion, the size of the second sub-conductive portion is larger than or equal to the size of the second connection portion.

[0029] The main technical effects achieved by the embodiments of the present application are:

[0030] In the semiconductor structure and the manufacturing method of the semiconductor structure provided by the embodiments of the present application, the first conductive part of the first lead frame is electrically connected to the first electrode of the chip, and the first pin connected to the first conductive part leads out the signal of the first electrode of the chip; the second conductive part of the second lead frame is electrically connected to the second electrode of the chip, and the second pin connected to the second conductive part leads out the signal of the second electrode of the chip; by using two lead frames to lead out the first electrode and the second electrode of the chip, bonding wires are not required, and problems such as poor soldering of the bonding wires, drawing of the bonding wires, and damage to the chip during the bonding process can be avoided, which helps to improve the quality of the semiconductor structure; by setting the surfaces of the first conductive part away from the chip and the second conductive part away from the chip to expose the plastic package layer respectively, both the first conductive part and the second conductive part can dissipate heat, that is, both opposite side surfaces of the semiconductor structure can dissipate heat, which helps to improve the heat dissipation performance of the semiconductor structure. Description of the Drawings

[0031] Figure 1 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application;

[0032] Figure 2 is a cross-sectional view of a semiconductor structure provided by another exemplary embodiment of the present application;

[0033] Figure 3 is a cross-sectional view of the first lead frame provided by an exemplary embodiment of the present application;

[0034] Figure 4 is a cross-sectional view of the second lead frame provided by an exemplary embodiment of the present application;

[0035] Figure 5 is a top view of the chip provided by an exemplary embodiment of the present application;

[0036] Figure 6 is Figure 5 the bottom view of the chip shown;

[0037] Figure 7 is a top view of the semiconductor structure provided by an exemplary embodiment of the present application;

[0038] Figure 8 is Figure 7 the bottom view of the semiconductor structure shown;

[0039] Figure 9 is a top view of a partial structure of the semiconductor structure provided by an exemplary embodiment of the present application;

[0040] Figure 10 is a cross-sectional view of the second lead frame provided by another exemplary embodiment of the present application;

[0041] Figure 11It is a top view of a partial structure of a semiconductor structure provided by another exemplary embodiment of the present application;

[0042] Figure 12 It is a top view of a semiconductor structure provided by still another exemplary embodiment of the present application;

[0043] Figure 13 It is a flowchart of a manufacturing method of a semiconductor structure provided by an exemplary embodiment of the present application;

[0044] Figure 14 It is a partial cross-sectional view of a first intermediate structure of a semiconductor structure provided by an exemplary embodiment of the present application;

[0045] Figure 15 It is a partial cross-sectional view of a second intermediate structure of a semiconductor structure provided by an exemplary embodiment of the present application;

[0046] Figure 16 It is a partial cross-sectional view of a third intermediate structure of a semiconductor structure provided by an exemplary embodiment of the present application;

[0047] Figure 17 It is a partial cross-sectional view of a fourth intermediate structure of a semiconductor structure provided by an exemplary embodiment of the present application. Specific Embodiments

[0048] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0049] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0050] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0051] The following will, with reference to the accompanying drawings, elaborate on some embodiments of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0052] Embodiments of the present application provide a semiconductor structure. As Figure 1 and Figure 2 shown, the semiconductor structure includes a first lead frame 10, a second lead frame 20, a chip 30, and a plastic encapsulation layer 60.

[0053] As Figure 3 shown, the first lead frame 10 includes a first conductive portion 11 and at least one first pin 12. The first pin 12 is located at a side of the first conductive portion 11 and is connected to the first conductive portion 11. As Figure 4 shown, the second lead frame 20 includes a second conductive portion 21 and at least one second pin 22. The second pin 22 is located at a side of the second conductive portion 21 and is connected to the second conductive portion 21. As Figure 5 and Figure 6 shown, the chip 30 includes opposite first and second surfaces 31 and 32. A first electrode 311 is provided on the first surface 31, and a second electrode 321 is provided on the second surface 32.

[0054] Referring again to Figure 1 and Figure 2 , the chip 30 is mounted on the first conductive portion 11; the first surface 31 faces the first conductive portion 11, and the first electrode 311 is electrically connected to the first conductive portion 11; the second conductive portion 21 of the second lead frame 20 is located on a side of the chip 30 away from the first conductive portion 11 and is electrically connected to the second electrode 321; the plastic encapsulation layer 60 encapsulates the first lead frame 10, the chip 30, and the second lead frame 20. Combining Figure 7 with Figure 8 , the surfaces of the first conductive portion 11 away from the chip 30 and the second conductive portion 21 away from the chip 30 are respectively exposed from the plastic encapsulation layer 60, and at least part of the first pin 12 and the second pin 22 are exposed from the plastic encapsulation layer 60.

[0055] In the semiconductor structure provided by the embodiment of the present application, the first conductive part of the first lead frame is electrically connected to the first electrode of the chip, and the first pin connected to the first conductive part leads out the signal of the first electrode of the chip; the second conductive part of the second lead frame is electrically connected to the second electrode of the chip, and the second pin connected to the second conductive part leads out the signal of the second electrode of the chip; by using two lead frames to lead out the first electrode and the second electrode of the chip, there is no need to use bonding wires, which can avoid problems such as cold soldering, bonding wire drawing, and damage to the chip during the bonding process when using bonding wires, and help to improve the quality of the semiconductor structure; by arranging the surface of the first conductive part away from the chip and the surface of the second conductive part away from the chip to expose the plastic sealing layer respectively, the first conductive part and the second conductive part can both dissipate heat, that is, the two opposite sides of the semiconductor structure can both dissipate heat, which helps to improve the heat dissipation performance of the semiconductor structure.

[0056] In one embodiment, Figure 4 As shown, two second electrodes 322 and 323 are disposed on the second surface of the chip 30 , and the second electrode 322 is spaced from the second electrode 323 .

[0057] In some embodiments, the first electrode 311 is a drain electrode, one of the second electrode 322 and the second electrode 323 is a source electrode, and the other is a gate electrode. The area of ​​the first electrode 311 may be greater than that of the second electrodes 322 and 323 .

[0058] In one embodiment, Figures 1 to 3 As shown, the first lead frame 10 includes a plurality of first pins 12, which are located on the same side of the first conductive portion 11 and arranged in parallel; the first pins 12 are in a zigzag shape, and the ends of the first pins 12 away from the first conductive portion 11 are straight portions.

[0059] In one embodiment, Figures 1 to 3 As shown, the first lead frame 10 also includes a connecting structure 13, which is located on one side of the first conductive part 11 and connected to the connecting structure 13, and each of the first pins 12 is respectively connected to a side of the connecting structure 13 away from the first conductive part 11; the connecting structure 13 can be tilted relative to the first conductive part 11.

[0060] In one embodiment, Figure 1 , Figure 2 and Figure 4 As shown, the second lead frame 20 includes a plurality of second pins 22, which are located on the same side of the second conductive portion 21 and arranged in parallel; the second pins 22 are in a zigzag shape, and the ends of the second pins 22 away from the second conductive portion 21 are straight portions.

[0061] In one embodiment, Figure 4As shown, the second conductive part 21 includes a first sub-conductive part 211 and a second sub-conductive part 212 which are spaced apart. The second lead frame 20 further includes a first connection part 23 and a second connection part 24. The first connection part 23 is located between the plurality of second pins 22 and the first sub-conductive part 211, and is respectively connected to the plurality of second pins 22 and the first sub-conductive part 211. The arrangement direction of the plurality of second pins 22 connected to the first connection part 23 is parallel to the extension direction of the first connection part 23. The second connection part 24 is located between the plurality of second pins 22 and the second sub-conductive part 212, and is respectively connected to the plurality of second pins 22 and the second sub-conductive part 212. The arrangement direction of the plurality of second pins 22 connected to the second connection part 24 is parallel to the extension direction of the second connection part 24. The extension direction of the first connection part 23 and the extension direction of the second connection part 24 may be the same.

[0062] As Figure 9 shown, the first sub-conductive part 211 is electrically connected to the second electrode 322, and the second sub-conductive part 212 is electrically connected to the second electrode 323. The second pins 22 connected to the first sub-conductive part 211 lead out the signals of the second electrode 322, and the second pins 22 connected to the second sub-conductive part 212 lead out the signals of the second electrode 323.

[0063] In one embodiment, as Figure 1 shown, the second pin 22 extends towards the first conductive part 11. The end of the first pin 12, the end of the second pin 22 away from the surface of the second conductive part 21, and the surface of the first conductive part 11 away from the second conductive part 21 are in the same plane. With such an arrangement, when the semiconductor structure is connected to the circuit board, the ends of the first pin 12 and the second pin 22 are connected to the pins of the circuit board, and the surface of the first conductive part 11 away from the second conductive part 21 can be in contact with the circuit board. The heat generated by the semiconductor structure is conducted to the circuit board through the first conductive part 11 and then conducted to the external environment by the circuit board.

[0064] In another embodiment, as Figure 2As shown, the first pin 12 extends towards the second conductive part 21, and the end of the first pin 12, the end of the second pin 22 away from the surface of the first conductive part 11, and the surface of the second conductive part 21 away from the first conductive part 11 are in the same plane. With such an arrangement, when the semiconductor structure is connected to the circuit board, the ends of the first pin 12 and the second pin 22 are connected to the pins of the circuit board, and the surface of the second conductive part 21 away from the first conductive part 11 can be in contact with the circuit board. The heat generated by the semiconductor structure is conducted to the circuit board through the second conductive part 21 and then conducted to the external environment by the circuit board.

[0065] In one embodiment, as Figure 1 and Figure 2 shown, the semiconductor structure further includes an adhesive layer 40 located between the first conductive part 11 and the chip 30, and the material of the adhesive layer 40 is a conductive material. With such an arrangement, the first surface 31 of the chip 30 can be fixed on the first conductive part 11 through the adhesive layer 40, and the first electrode 311 of the chip 30 is electrically connected to the first conductive part 11 through the adhesive layer 40. In some embodiments, the material of the adhesive layer 40 can be cured solder paste or silver paste.

[0066] In one embodiment, as Figure 1 , Figure 2 and Figure 9 shown, the semiconductor structure further includes a conductive structure 50 located between the first sub-conductive part 211 and the second electrode 322, and a conductive structure 50 located between the second sub-conductive part 212 and the second electrode 323. The material of the conductive structure 50 is solder; the first sub-conductive part 211 and the second sub-conductive part 212 are respectively soldered to the conductive structure 50. By providing the conductive structure 50 and the material of the conductive structure 50 being solder, it is convenient to fix the first sub-conductive part 211 and the second sub-conductive part 212 of the second lead frame 20 to the chip 30, and it can ensure that the first sub-conductive part 211 and the second sub-conductive part 212 are respectively electrically connected to the corresponding second electrodes 321; the second conductive part can be soldered to the conductive structure by using a single reflow soldering process without the need for a second reflow soldering, which can avoid poor soldering caused by oxidation of the second conductive part during the second reflow soldering. In some embodiments, the solder may include metallic tin.

[0067] Further, the distance between the first sub-conductive part 211 and the second sub-conductive part 212 is greater than or equal to 500 μm. With such an arrangement, it can be avoided that the distance between the first sub-conductive part 211 and the second sub-conductive part 212 is too close, so that when they are soldered to the conductive structure 50, a short circuit problem may occur between the first sub-conductive part 211 and the second sub-conductive part 212 due to the flow of the solder.

[0068] In one embodiment, as Figure 4 shown, in the extending direction of the first connecting portion 23, the size of the first connecting portion 23 is larger than the size of the first sub-conductive portion 211; in the extending direction of the second connecting portion 24, the size of the second connecting portion 24 is larger than the size of the second sub-conductive portion 212. With such a setting, the gap between the first sub-conductive portion 211 and the second sub-conductive portion 212 can be set to be relatively large, which is more helpful for avoiding the problem that the first sub-conductive portion 211 and the second sub-conductive portion 212 are short-circuited due to the flow of solder when the first sub-conductive portion 211 and the second sub-conductive portion 212 are welded to the conductive structure 50.

[0069] In another embodiment, as Figure 10 and Figure 11 shown, in the extending direction of the first connecting portion 23, the size of the first sub-conductive portion 211 is larger than or equal to the size of the first connecting portion 23; in the extending direction of the second connecting portion 24, the size of the second sub-conductive portion 212 is larger than or equal to the size of the second connecting portion 24. With such a setting, as Figure 12 shown, the area of the first sub-conductive portion 211 and the area of the second sub-conductive portion 212 are relatively large, and further, the area of the first sub-conductive portion 211 and the second sub-conductive portion 212 exposed from the encapsulation layer 60 is relatively large, which is helpful for improving the heat dissipation performance of the semiconductor structure. Figure 10 and Figure 11 shown in the embodiment, in the extending direction of the first connecting portion 23, the size of the first sub-conductive portion 211 is equal to the size of the first connecting portion 23, and the size of the second sub-conductive portion 212 is equal to the size of the second connecting portion 24.

[0070] In one embodiment, as Figure 9 shown, the orthographic projection of the chip 30 on the surface of the first conductive portion 11 facing the chip 30 entirely falls on the first conductive portion 11, and the area of the surface of the first conductive portion 11 facing the chip 30 is larger than the area of the orthographic projection of the chip 30 on the surface of the first conductive portion 11 facing the chip 30. With such a setting, it can not only ensure a good supporting effect of the first conductive portion 11 on the chip 30, but also make the area of the first conductive portion 11 relatively large, which is helpful for improving the heat dissipation performance of the semiconductor structure.

[0071] The embodiment of the present application also provides a manufacturing method of a semiconductor structure. As Figure 13 shown, the manufacturing method includes the following steps 110 to 140.

[0072] In step 110, a first lead frame is provided, the first lead frame including a first conductive portion and at least one first pin, the first pin being located at a side portion of the first conductive portion and connected to the first conductive portion.

[0073] In one embodiment, the first lead frame further includes a first frame body and connecting ribs, the first conductive portion and the first pin being located within the first frame body, and the first conductive portion and the first pin being connected to the first frame body through the connecting ribs respectively.

[0074] In step 120, a chip is mounted on the first conductive portion; the chip includes an opposite first surface and a second surface, the first surface being provided with a first electrode, and the second surface being provided with a second electrode; the first surface faces the first conductive portion, and the first electrode is electrically connected to the first conductive portion.

[0075] In one embodiment, before the above step 120, the manufacturing method of the semiconductor structure further includes: coating an adhesion layer on the first conductive portion, the material of the adhesion layer being a conductive material.

[0076] Through this step, a first intermediate structure as shown in Figure 14 can be obtained. As shown in Figure 14 , an adhesion layer 70 is coated on the first conductive portion 11. In some embodiments, the adhesion layer 70 can be silver paste or solder paste. After the chip is mounted on the adhesion layer 70, the silver paste or solder paste is cured, and thus the chip 30 can be fixed on the first conductive portion 11.

[0077] In one embodiment, as shown in Figure 4 , the second conductive portion 21 includes a first sub-conductive portion 211 and a second sub-conductive portion 212 which are spaced apart; as shown in Figure 5 , two second electrodes 321 are provided on the second surface 32 of the chip 30. Before or after the step of mounting the chip on the first conductive portion, the manufacturing method further includes: respectively providing a conductive structure on each of the second electrodes, the material of the conductive structure being solder.

[0078] Through this step, a second intermediate structure as shown in Figure 15 can be obtained. As shown in Figure 15 , a conductive structure 50 is provided on the second surface of the chip 30. Specifically, the conductive structure 50 is located on the second electrode 321 of the second surface 32, and at least one conductive structure is provided on each of the second electrodes 321. The conductive structure 50 can be a conductive ball.

[0079] In step 130, a second lead frame is provided, the second lead frame including a second conductive part and at least one second pin, the second pin being located at a side of the second conductive part and connected to the second conductive part; the second conductive part is disposed on a side of the chip away from the first lead frame, and the second conductive part is electrically connected to the second electrode.

[0080] In one embodiment, the second lead frame further includes a second frame body and connecting ribs, the second conductive part and the second pins being located within the second frame body, and the second conductive part and the second pins being connected to the second frame body through the connecting ribs respectively.

[0081] In one embodiment, as Figure 4 and Figure 10 shown, the second conductive part 21 includes a first sub-conductive part 211 and a second sub-conductive part 212 which are spaced apart; the second lead frame 20 includes a plurality of the second pins 22; the second lead frame 20 further includes a first connection part 23 and a second connection part 24. The first connection part 23 is located between the second pins 22 and the first sub-conductive part 211, and is connected to the plurality of second pins 22 and the first sub-conductive part 211 respectively, and the arrangement direction of the plurality of second pins 22 connected to the first connection part 23 is parallel to the extending direction of the first connection part 23. The second connection part 24 is located between the second pins 22 and the second sub-conductive part 212, and is connected to the plurality of second pins 22 and the second sub-conductive part 212 respectively, and the arrangement direction of the plurality of second pins 22 connected to the second connection part 24 is parallel to the extending direction of the second connection part 24.

[0082] Further, as Figure 4 shown, in the extending direction of the first connection part 23, the size of the first connection part 23 is greater than the size of the first sub-conductive part 211; in the extending direction of the second connection part 24, the size of the second connection part 24 is greater than the size of the second sub-conductive part 212. Or, as Figure 10 shown, in the extending direction of the first connection part 23, the size of the first sub-conductive part 211 is greater than or equal to the size of the first connection part 23; in the extending direction of the second connection part 24, the size of the second sub-conductive part 212 is greater than or equal to the size of the second connection part 24.

[0083] In one embodiment, the step of disposing the second conductive part on a side of the chip away from the first lead frame and electrically connecting the second conductive part to the second electrode includes the following process: disposing the second conductive part on a side of the chip away from the first lead frame, and welding the first sub-conductive part and the second sub-conductive part to the conductive structure respectively.

[0084] The third intermediate structure as shown in Figure 16 can be obtained through step 130. As shown in Figure 16 , the second conductive part 21 is welded to the conductive structure 50.

[0085] In step 140, a molding compound layer is formed, which encapsulates the first lead frame, the chip and the second lead frame. The surfaces of the first conductive part away from the chip and the second conductive part away from the chip are exposed from the molding compound layer, and the first pin and the second pin are partially exposed from the molding compound layer.

[0086] The fourth intermediate structure as shown in Figure 17 can be obtained through this step. As shown in Figure 17 , the molding compound layer 60 encapsulates the first lead frame 10, the second lead frame 20 and the chip 30. The surfaces of the first conductive part 11 away from the chip 30 and the second lead frame 20 away from the chip 30 are exposed from the molding compound layer 30; the parts of the first pin 12 and the second pin 22 exposed from the molding compound layer 30 are flat.

[0087] In one embodiment, the material of the molding compound layer 30 can be polymer resin, resin composite material, polymer composite material, etc. For example, the molding compound layer 30 can be a resin with fillers, and the fillers can be inorganic particles. The molding compound layer 30 can be formed by injection molding, compression molding, transfer molding or other methods.

[0088] In one embodiment, before the step of forming the molding compound layer, some pretreatment steps can be performed, such as chemical cleaning, plasma cleaning and other steps, to remove the impurities on the exposed surfaces of the chip, the first lead frame and the second lead frame, so that the molding compound layer can be more closely connected to the chip, the first lead frame and the second lead frame, and there will be no delamination or cracking phenomenon.

[0089] In one embodiment, after the step of forming the molding compound layer, the manufacturing method of the semiconductor structure further includes the following steps: cutting the connecting bars of the first lead frame to separate the first conductive part and the first pin from the first frame body; cutting the connecting bars of the second lead frame to separate the second conductive part and the second pin from the second frame body.

[0090] In one embodiment, after the step of forming the molding compound layer, the manufacturing method of the semiconductor structure further includes the following steps: bending the first pin and the second pin so that the second pin extends towards the first conductive part, and the end of the first pin away from the surface of the second conductive part, the end of the second pin away from the surface of the second conductive part and the surface of the first conductive part away from the second conductive part are in the same plane.

[0091] Through this step, a semiconductor structure as shown in Figure 1 can be obtained.

[0092] In another embodiment, after the step of forming the encapsulation layer, the manufacturing method of the semiconductor structure further includes the following steps: bending the first lead and the second lead so that the first lead extends towards the second conductive part, and the end of the first lead is away from the surface of the first conductive part, the end of the second lead is away from the surface of the first conductive part, and the surface of the second conductive part away from the first conductive part are in the same plane.

[0093] Through this step, a semiconductor structure as shown in Figure 2 can be obtained.

[0094] In the embodiments provided in the present application, only the case where the second surface of the chip 30 is provided with two electrodes and the second conductive part of the second lead frame includes two sub-conductive parts is taken as an example for introduction. In other embodiments, it may be that the first surface of the chip 30 is provided with two electrodes and the first conductive part of the first lead frame includes two sub-conductive parts.

[0095] The embodiments of the semiconductor structure provided in the embodiments of the present application and the embodiments of the manufacturing method of the semiconductor structure belong to the same inventive concept. For the description of relevant details and beneficial effects, reference can be made to each other, and details will not be repeated here.

[0096] It should be noted that in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Moreover, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Additionally, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Like reference numerals throughout the specification indicate like elements.

[0097] Those skilled in the art will readily conceive of other embodiments of the present application upon considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are to be considered as exemplary only, and the true scope and spirit of the present application are pointed out by the following claims.

[0098] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A semiconductor structure, characterized in that, the semiconductor structure includes: A first lead frame, including a first conductive portion and at least one first lead, the first lead being located on a side portion of the first conductive portion and connected to the first conductive portion; A chip mounted on the first conductive portion; the chip includes opposite first and second surfaces, a first electrode is provided on the first surface, and a second electrode is provided on the second surface; the first surface faces the first conductive portion, and the first electrode is electrically connected to the first conductive portion; A second lead frame, including a second conductive portion and at least one second lead, the second lead being located on a side portion of the second conductive portion and connected to the second conductive portion; the second conductive portion is located on a side of the chip away from the first conductive portion and is electrically connected to the second electrode; A plastic encapsulation layer encapsulating the first lead frame, the chip, and the second lead frame, surfaces of the first conductive portion away from the chip and the second conductive portion away from the chip are respectively exposed from the plastic encapsulation layer, and at least part of the first lead and the second lead are exposed from the plastic encapsulation layer.

2. The semiconductor structure according to claim 1, characterized in that, the second lead extends towards the first conductive portion, an end surface of the first lead away from the second conductive portion, an end surface of the second lead away from the second conductive portion, and a surface of the first conductive portion away from the second conductive portion are in the same plane; or, the first lead extends towards the second conductive portion, an end surface of the first lead away from the first conductive portion, an end surface of the second lead away from the first conductive portion, and a surface of the second conductive portion away from the first conductive portion are in the same plane.

3. The semiconductor structure according to claim 1, characterized in that, two of the second electrodes are provided on the second surface, the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion arranged at intervals, the first sub-conductive portion and the second sub-conductive portion are respectively electrically connected to different second electrodes; the semiconductor structure further includes a conductive structure located between the first sub-conductive portion and the second electrode, and a conductive structure located between the second sub-conductive portion and the second electrode, the material of the conductive structure is solder; the first sub-conductive portion and the second sub-conductive portion are respectively welded to the conductive structure.

4. The semiconductor structure according to claim 3, characterized in that, the distance between the first sub-conductive portion and the second sub-conductive portion is greater than or equal to 500 μm.

5. The semiconductor structure according to claim 1, characterized in that, The second surface is provided with two of the second electrodes, and the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion that are spaced apart; the second lead frame includes a plurality of the second pins; the second lead frame further includes a first connection portion and a second connection portion; the first connection portion is located between the plurality of second pins and the first sub-conductive portion, and is respectively connected to the plurality of second pins and the first sub-conductive portion, and the arrangement direction of the plurality of second pins connected to the first connection portion is parallel to the extension direction of the first connection portion; the second connection portion is located between the plurality of second pins and the second sub-conductive portion, and is respectively connected to the plurality of second pins and the second sub-conductive portion, and the arrangement direction of the plurality of second pins connected to the second connection portion is parallel to the extension direction of the second connection portion; In the extension direction of the first connection portion, the size of the first connection portion is greater than the size of the first sub-conductive portion; in the extension direction of the second connection portion, the size of the second connection portion is greater than the size of the second sub-conductive portion; or, in the extension direction of the first connection portion, the size of the first sub-conductive portion is greater than or equal to the size of the first connection portion; in the extension direction of the second connection portion, the size of the second sub-conductive portion is greater than or equal to the size of the second connection portion.

6. The semiconductor structure according to claim 1, wherein, The orthographic projection of the chip on the surface of the first conductive portion facing the chip entirely falls on the first conductive portion, and the area of the surface of the first conductive portion facing the chip is greater than the area of the orthographic projection of the chip on the surface of the first conductive portion facing the chip.

7. A manufacturing method of a semiconductor structure, wherein, The manufacturing method includes: Providing a first lead frame, the first lead frame includes a first conductive portion and at least one first pin, and the first pin is located at a side portion of the first conductive portion and is connected to the first conductive portion; Mounting the chip on the first conductive portion; the chip includes an opposite first surface and a second surface, the first surface is provided with a first electrode, and the second surface is provided with a second electrode; the first surface faces the first conductive portion, and the first electrode is electrically connected to the first conductive portion; Providing a second lead frame, the second lead frame includes a second conductive portion and at least one second pin, and the second pin is located at a side portion of the second conductive portion and is connected to the second conductive portion; arranging the second conductive portion on a side of the chip away from the first lead frame, and electrically connecting the second conductive portion to the second electrode; Forming a plastic encapsulation layer, the plastic encapsulation layer encapsulates the first lead frame, the chip and the second lead frame, the surface of the first conductive portion away from the chip and the surface of the second conductive portion away from the chip are exposed from the plastic encapsulation layer, and at least a part of the first pin and the second pin are exposed from the plastic encapsulation layer.

8. The manufacturing method of a semiconductor structure according to claim 7, wherein, The second surface is provided with two of the second electrodes, and the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion arranged at intervals; before or after mounting the chip on the first conductive portion, the manufacturing method further includes: respectively disposing a conductive structure on each of the second electrodes, and the material of the conductive structure is solder; The step of disposing the second conductive portion on a side of the chip away from the first lead frame and electrically connecting the second conductive portion to the second electrode includes: Disposing the second conductive portion on a side of the chip away from the first lead frame, and respectively soldering the first sub-conductive portion and the second sub-conductive portion to the conductive structure.

9. The manufacturing method of the semiconductor structure according to claim 7, wherein, after forming the encapsulation layer, the manufacturing method of the semiconductor structure further includes: performing a bending process on the first pin and the second pin, such that the second pin extends toward the first conductive portion, and the surfaces of the end portions of the first pin away from the second conductive portion, the surfaces of the end portions of the second pin away from the second conductive portion, and the surface of the first conductive portion away from the second conductive portion are in the same plane; or, after forming the encapsulation layer, the manufacturing method of the semiconductor structure further includes: performing a bending process on the first pin and the second pin, such that the first pin extends toward the second conductive portion, and the surfaces of the end portions of the first pin away from the first conductive portion, the surfaces of the end portions of the second pin away from the first conductive portion, and the surface of the second conductive portion away from the first conductive portion are in the same plane.

10. The manufacturing method of the semiconductor structure according to claim 7, wherein, the second surface is provided with two of the second electrodes, and the second conductive portion includes a first sub-conductive portion and a second sub-conductive portion arranged at intervals; the second lead frame includes a plurality of the second pins; the second lead frame further includes a first connection portion and a second connection portion; the first connection portion is located between the second pins and the first sub-conductive portion, and is respectively connected to the plurality of second pins and the first sub-conductive portion, and the arrangement direction of the plurality of second pins connected to the first connection portion is parallel to the extending direction of the first connection portion; the second connection portion is located between the second pins and the second sub-conductive portion, and is respectively connected to the plurality of second pins and the second sub-conductive portion, and the arrangement direction of the plurality of second pins connected to the second connection portion is parallel to the extending direction of the second connection portion; In the extending direction of the first connecting portion, the size of the first connecting portion is larger than the size of the first sub-conductive portion; in the extending direction of the second connecting portion, the size of the second connecting portion is larger than the size of the second sub-conductive portion; or, in the extending direction of the first connecting portion, the size of the first sub-conductive portion is larger than or equal to the size of the first connecting portion; in the extending direction of the second connecting portion, the size of the second sub-conductive portion is larger than or equal to the size of the second connecting portion.

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