Lead frame and semiconductor structure

Abstract

The invention provides a lead frame and a semiconductor structure. The lead frame comprises a frame body and at least one connecting unit located in the frame body. The connecting unit comprises a base island and a plurality of first pins located on the side portion of the base island. The first pins and the base islands are arranged at intervals. The first pin comprises a bonding part, a first connecting part and a first terminal part which are connected in sequence; the first connecting part is located on one side of the bonding part away from the base island. The first terminal part is located on one side of the first connecting part away from the base island. The first pin is provided with a first opening, and the first opening is only located in the first connecting part. The semiconductor structure comprises a lead frame, a chip, a plurality of bonding wires and a plastic packaging layer. The lead frame comprises a base island and a plurality of first pins, the first pins are provided with first holes, and the first holes are only located in the first connecting parts. The chip is attached to the base island, and a first electrode is arranged on the side, away from the base island, of the chip. The bonding wire is respectively bonded with the first electrode and the bonding part. The plastic packaging layer packages the chip, the bonding wire and the lead frame, and the first terminal part is exposed out of the plastic packaging layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a lead frame and a semiconductor structure. Background Art

[0002] Common semiconductor packaging structures generally include a lead frame, a chip, bonding wires, and a plastic encapsulation layer. The lead frame includes a base island and a plurality of pins. The chip is mounted on the base island, and the electrodes of the chip are electrically connected to the pins through bonding wires. The plastic encapsulation layer encapsulates the lead frame, the chip, and the bonding wires, and a part of the structure of the pins is exposed from the plastic encapsulation layer.

[0003] The current-carrying capacity of the existing semiconductor packaging structure is relatively low, which is not conducive to the development of semiconductor packaging structures towards high-power devices. Summary of the Invention

[0004] Embodiments of this application provide a lead frame and a semiconductor structure.

[0005] According to the first aspect of the embodiments of this application, a lead frame is provided. The lead frame includes a frame body and at least one connection unit located within the frame body. The connection unit includes:

[0006] A base island;

[0007] A plurality of first pins located on the side of the base island, the plurality of first pins being spaced apart from the base island. The first pins include a bonding portion, a first connection portion, and a first terminal portion that are sequentially connected. The bonding portion is used for bonding with a bonding wire. The first connection portion is located on the side of the bonding portion away from the base island, and the first terminal portion is located on the side of the first connection portion away from the base island. The first pin is provided with a first opening, and the first opening is only located in the first connection portion.

[0008] In one embodiment, the depth of the first opening is less than the thickness of the first pin.

[0009] In one embodiment, the ratio range of the depth of the first opening to the thickness of the first pin is 35% to 60%.

[0010] In one embodiment, in the length direction of the first pin, the ratio range of the size of the first opening to the total size of the bonding portion and the first connection portion is 20% to 40%; and / or,

[0011] In the width direction of the first pin, the minimum value of the size of the first opening is the minimum size of the etching process, and the maximum value is less than the width of the first connection portion; and / or,

[0012] The plurality of first pins are located on the same side of the base island, and the bonding portions of at least two of the first pins are connected; and / or,

[0013] The width of the first connection portion is equal to the width of the first terminal portion.

[0014] In one embodiment, the connection unit further includes a plurality of second pins. The plurality of second pins include a second connection portion and a second terminal portion located on a side of the second connection portion away from the base island. The second connection portion is directly connected to the base island; the second pin is provided with a second opening, and the second opening is only located in the second connection portion.

[0015] In one embodiment, the depth of the second opening is less than the thickness of the second pin; and / or,

[0016] In the length direction of the second pin, the ratio of the size of the second opening to the total size of the second connection portion ranges from 50% to 100%; and / or,

[0017] In the width direction of the second pin, the minimum value of the size of the second opening is the minimum size of the etching process, and the maximum value is less than the width of the second connection portion; and / or,

[0018] The width of the second connection portion is the same as the width of the second terminal portion.

[0019] According to a second aspect of the embodiments of the present application, a semiconductor structure is provided. The semiconductor structure includes:

[0020] A lead frame, the lead frame includes a base island and a plurality of first pins located on the side of the base island. The plurality of first pins are spaced apart from the base island; the first pin includes a bonding portion, a first connection portion, and a first terminal portion that are sequentially connected; the first connection portion is located on a side of the bonding portion away from the base island, and the first terminal portion is located on a side of the first connection portion away from the base island; the first pin is provided with a first opening, and the first opening is only located in the first connection portion;

[0021] A chip mounted on the base island, and a first electrode is provided on a side of the chip away from the base island;

[0022] A plurality of bonding wires, one end of the bonding wire is bonded to the first electrode, and the other end is bonded to the bonding portion;

[0023] A plastic encapsulation layer encapsulates the chip, the bonding wire, the base island, the bonding portion, and the first connection portion. The plastic encapsulation layer fills the first opening, and the first terminal portion exposes the plastic encapsulation layer.

[0024] In one embodiment, the depth of the first opening is less than the thickness of the first pin; and / or,

[0025] In the length direction of the first pin, the ratio of the size of the first opening to the total size of the bonding portion and the first connecting portion ranges from 20% to 40%; and / or,

[0026] In the width direction of the first pin, the minimum value of the size of the first opening is the minimum size of the etching process, and the maximum value is less than the width of the first connecting portion; and / or,

[0027] The width of the first connecting portion is equal to the width of the first terminal portion.

[0028] In one embodiment, the lead frame further includes a plurality of second pins. The second pins include second connecting portions and second terminal portions located on the side of the second connecting portions away from the base island. The second connecting portions are directly connected to the base island; the second pins are provided with second openings, and the second openings are only located in the second connecting portions; a second electrode is provided on the side of the chip facing the base island, and the second electrode is electrically connected to the base island;

[0029] The encapsulation layer encapsulates the second connecting portions, the encapsulation layer fills the second openings, and the second terminal portions are exposed from the encapsulation layer.

[0030] In one embodiment, the depth of the second opening is less than the thickness of the second pin; and / or,

[0031] In the length direction of the second pin, the ratio of the size of the second opening to the total size of the second connecting portion ranges from 50% to 100%; and / or,

[0032] In the width direction of the second pin, the minimum value of the size of the second opening is the minimum size of the etching process, and the maximum value is less than the width of the second connecting portion; and / or,

[0033] The width of the second connecting portion is the same as the width of the second terminal portion.

[0034] The main technical effects achieved by the embodiments of the present application are:

[0035] The lead frame and semiconductor structure provided by the embodiments of the present application, by providing a first opening on the first lead, the encapsulant in the semiconductor structure including the lead frame fills the first opening, which can increase the contact area between the encapsulant and the lead frame, thereby increasing the bonding force between the encapsulant and the lead frame, and can increase the path for dust and moisture to invade the chip, which helps to prevent dust and moisture from invading the chip inside the semiconductor structure through the gap between the encapsulant and the lead frame, improving the reliability of the semiconductor structure; since the first opening is only provided on the first connection portion of the first lead, compared with the solution of providing the first opening on the bonding portion, it can avoid the reduction of the area of the bonding portion for welding with the bonding wire due to the setting of the first opening, and thus can increase the number of bonding wires connecting the electrodes of the chip to the bonding portion, improving the current-carrying capacity of the semiconductor structure, which is beneficial to the development of the semiconductor packaging structure towards high-power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a top view of a connection unit of a lead frame provided by an exemplary embodiment of the present application;

[0037] Figure 2 is a schematic structural diagram of a semiconductor structure provided by an exemplary embodiment of the present application;

[0038] Figure 3 is a three-dimensional structural diagram of a semiconductor structure provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0040] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0041] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".

[0042] The following will, with reference to the accompanying drawings, elaborate on some embodiments of this application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0043] An embodiment of this application provides a lead frame. The lead frame includes a frame body and at least one connecting unit located within the frame body, and each connecting unit 10 is respectively connected to the frame body. As Figure 1 shown, the connecting unit 10 includes a base island 11 and a plurality of first pins 12 located on the side of the base island 11. The plurality of first pins 12 are spaced apart from the base island 11. The first pin 12 includes a bonding portion 121, a first connecting portion 122, and a first terminal portion 123 that are sequentially connected. Among them, the bonding portion 121 is used for bonding with a bonding wire, the first connecting portion 122 is located on the side of the bonding portion 121 away from the base island 11, and the first terminal portion 123 is located on the side of the first connecting portion 122 away from the base island 11. The first pin 12 is provided with a first opening 124, and the first opening 124 is only located in the first connecting portion 122.

[0044] When the lead frame provided by the embodiment of this application is used in a semiconductor structure, the semiconductor structure may be as Figure 2 and Figure 3 shown. As Figure 2 and Figure 3 shown, the semiconductor structure includes a lead frame 10, a chip 20, a bonding wire 30, and a molding compound layer 40. The bonding portion 121 and the first connecting portion 122 of the first pin 12 are encapsulated by the molding compound layer 40, and the molding compound layer 40 fills the first opening 124; the first terminal portion 123 is exposed from the molding compound layer 40, and the first terminal portion 123 is used for connection with an external structure.

[0045] The lead frame provided by the embodiment of the present application has a first opening provided on the first lead. In the semiconductor structure including the lead frame, the encapsulation layer fills the first opening, which can increase the contact area between the encapsulation layer and the lead frame, thereby increasing the bonding force between the encapsulation layer and the lead frame. Moreover, it can increase the path for dust and moisture to invade the chip, helping to prevent dust and moisture from invading the chip inside the semiconductor structure through the gap between the encapsulation layer and the lead frame, and improving the reliability of the semiconductor structure. Since the first opening is only provided on the first connection portion of the first lead, compared with the solution of providing the first opening on the bonding portion, it can avoid the reduction of the area of the bonding portion used for welding with the bonding wire, and thus can increase the number of bonding wires connecting the electrodes of the chip to the bonding portion, improving the current-carrying capacity of the semiconductor structure, which is beneficial to the development of semiconductor packaging structures towards high-power devices.

[0046] In one embodiment, in the length direction of the first lead 12, the size of the first opening 124 may be substantially the same as the size of the first connection portion 122. The portion of the first lead 12 on the side facing the base island 11 of the first opening 124 can be all used for bonding with the bonding wire, and the portion of the first lead 12 on the side away from the base island 11 of the first opening 124 can be all exposed from the encapsulation layer to serve as the first terminal portion 123 connected to the external structure. The edge of the first opening 124 away from the base island 11 and the edge of the encapsulation layer 40 on the same side can be flush.

[0047] In one embodiment, the frame body is annular, and each connecting unit 10 is located within the space enclosed by the frame body. For example, the frame body can be square annular.

[0048] In one embodiment, the lead frame includes a plurality of connecting units 10, and the plurality of connecting units 10 can be arranged along the length direction of the frame body.

[0049] In one embodiment, the base island 11 and the first lead 12 are respectively connected to the frame body. The end of the terminal portion 123 of the lead 12 away from the base island 11 can be directly connected to the frame body, and the side portion of the base island 11 can be connected to the frame body through connecting ribs.

[0050] In one embodiment, as Figure 1 shown, the plurality of leads 12 are located on the same side of the base island 11.

[0051] In one embodiment, as Figure 1As shown, the lead frame 10 further includes a plurality of first connection structures 14, and the first terminal portions 123 of adjacent first pins 12 are connected to each other through the first connection structures 14. By providing the first connection structures 14, the plurality of first pins 12 are connected into an integral structure, which can improve the strength of the lead frame and avoid the region of the first pins 12 between the two end portions sagging under the action of gravity due to the excessive length of the first pins 12, which affects the quality of the formed semiconductor structure. As Figure 2 shown, in the prepared semiconductor structure, the first connection structures 14 are removed.

[0052] In one embodiment, the first opening 124 is formed by an etching process. The etching process can be a wet etching process or a dry etching process. Compared with the solution of forming a groove on the first connection portion 122 of the first pin 12 by a punching process, the solution of forming the first opening 124 by an etching process can set the depth of the first opening 124 to be larger. Then, the setting of the first opening 124 can effectively improve the bonding force between the encapsulation layer and the lead frame, and there is no need to set an opening or a groove on the bonding portion 121 to further improve the bonding force between the encapsulation layer and the lead frame, which helps to increase the bonding area of the bonding portion 121.

[0053] In one embodiment, as Figure 1 shown, the depth of the first opening 124 is less than the thickness of the first pin 12. With such a setting, compared with the solution where the first opening 124 penetrates through the first pin 12, it can be avoided that the setting of the first opening 124 results in low strength of the first pin 12 and too large resistance of the pin 12, which affects the current-carrying capacity of the semiconductor structure where the lead frame is located.

[0054] Furthermore, the ratio range of the depth of the first opening 124 to the thickness of the first pin 12 is 35% to 60%. With such a setting, it can be avoided that the depth of the first opening 124 is too small and the setting of the first opening 124 cannot effectively improve the bonding force between the encapsulation layer and the lead frame, and it can also be avoided that the depth of the first opening 124 is too large, resulting in low strength of the first pin 12 and too large resistance of the first pin 12, which affects the current-carrying capacity of the semiconductor structure where the lead frame is located. In some embodiments, the ratio of the depth of the first opening 124 to the thickness of the first pin 12 can be, for example, 35%, 40%, 45%, 50%, 55%, 60%, etc.

[0055] In one embodiment, in the length direction of the first pin 12, the ratio of the size of the first opening 124 to the total size of the bonding portion 121 and the first connecting portion 122 ranges from 20% to 40%. When the length of the first pin 12 and the length of the first terminal portion 123 are fixed, the total size of the bonding portion 121 and the first connecting portion 122 in the length direction of the first pin 12 is a fixed value. The setting of the above numerical range can prevent the ratio from being too large, resulting in too small a size of the bonding portion 121 and a small area of the bonding portion 121 for bonding with the bonding wire; it can also prevent the ratio from being too small and the size of the first opening 124 from being too small, so that the setting of the first opening 124 cannot effectively improve the bonding force between the plastic package layer and the lead frame.

[0056] In one embodiment, in the width direction of the first pin 12, the minimum value of the size of the first opening 124 is the minimum size of the etching process, and the maximum value is less than the width of the first connecting portion 122.

[0057] In one embodiment, as Figure 1 shown, the multiple first pins 12 are located on the same side of the base island 11, and the bonding portions 121 of at least two of the first pins 12 are connected. With such a setting, the total area of the bonding portions 121 of the connected multiple first pins 12 can be increased. Compared with the bonding portions 121 of the multiple first pins 12 being arranged at intervals, a larger welding area can be provided for bonding with the bonding wire, that is, more bonding wires can be arranged in the semiconductor structure to electrically connect the chip to the first pins 12, and the current-carrying capacity of the semiconductor structure can be further improved.

[0058] Further, as Figure 1 shown, among the multiple first pins 12, the bonding portions 121 of at least two adjacent first pins 12 are arranged at intervals. With such a setting, the spaced-apart bonding portions 121 can be electrically connected to different electrodes of the chip respectively, avoiding short circuits between different electrodes of the chip.

[0059] In one embodiment, the width of the first connecting portion 122 is equal to the width of the first terminal portion 123. When forming a semiconductor structure based on a lead frame, the position of the edge of the encapsulation layer fluctuates, that is, the boundary line between the first connecting portion 122 and the first terminal portion 123 shifts. If the widths of the first connecting portion 122 and the first terminal portion 123 are different, it may cause the width of the region near the encapsulation layer and the region far from the encapsulation layer in the part of the first lead 12 exposed from the encapsulation layer to be different. If the width of the region near the encapsulation layer in the part of the first lead 12 exposed from the encapsulation layer is greater than the width of the region far from the encapsulation layer, when welding the semiconductor structure formed based on the lead frame to a circuit board, the part of the first lead 12 near the encapsulation layer may contact the structure in the circuit board due to its large width, thus resulting in a short - circuit problem. By setting the width of the first connecting portion 122 to be equal to the width of the first terminal portion 123, the width of the part of the first lead 12 exposed from the encapsulation layer can be made the same, avoiding the above - mentioned problem.

[0060] In one embodiment, as Figure 1 shown, the connection unit 10 further includes a plurality of second leads 13. The plurality of second leads 13 include a second connecting portion 131 and a second terminal portion 132 located on the side of the second connecting portion 131 away from the base island 11. The second connecting portion 131 is directly connected to the base island 11; the second lead 13 is provided with a second opening 133, and the second opening 133 is only located in the second connecting portion 131. By providing the second connecting portion 131, the second connecting portion 131 can be electrically connected to the electrode of the chip facing the base island 11 through the base island 11, leading out the electrode of the chip facing the base island 11; by providing the second opening 133 located in the second connecting portion 131 on the second lead 13, the contact area between the encapsulation layer and the lead frame can be increased, thereby enhancing the bonding force between the two, and the path for dust and moisture to invade the chip can be increased, which helps to reduce the invasion of dust and moisture into the chip inside the semiconductor structure through the gap between the encapsulation layer and the lead frame, improving the reliability of the semiconductor structure.

[0061] As Figure 2 and Figure 3 shown, when the lead frame is used for a semiconductor structure, the second connecting portion 131 of the second lead 13 is covered by the encapsulation layer 40, and the second terminal portion 132 is exposed from the encapsulation layer 40 for electrical connection with an external structure.

[0062] In one embodiment, the second opening 133 is formed by an etching process. The etching process can be a wet etching process or a dry etching process. Compared with the scheme of forming a groove on the second connecting portion 131 of the second lead 13 by a punching process, the scheme of forming the first opening 124 by an etching process can set the depth of the second opening 133 to be larger, thereby effectively enhancing the bonding force between the encapsulation layer and the lead frame.

[0063] In one embodiment, the depth of the second opening 133 is less than the thickness of the second pin 13. With such a setting, compared with the solution where the second opening 133 penetrates through the second pin 13, it is possible to avoid the problems that the strength of the second pin 13 is low due to the setting of the second opening 133 and the resistance of the second pin 13 is too large, which affects the current-carrying capacity of the semiconductor structure where the lead frame is located.

[0064] Furthermore, the ratio of the depth of the second opening 133 to the thickness of the second pin 13 ranges from 35% to 60%. With such a setting, it is possible to avoid the situation where the depth of the second opening 133 is too small, and the setting of the second opening 133 cannot effectively improve the bonding force between the plastic encapsulation layer and the lead frame. It is also possible to avoid the situation where the depth of the second opening 133 is too large, resulting in low strength of the second pin 13 and too large resistance of the second pin 13, which affects the current-carrying capacity of the semiconductor structure where the lead frame is located. In some embodiments, the ratio of the depth of the second opening 133 to the thickness of the second pin 13 can be, for example, 35%, 40%, 45%, 50%, 55%, 60%, etc.

[0065] In one embodiment, in the width direction of the second pin 13, the ratio of the size of the second opening 133 to the size of the second connecting portion 131 ranges from 50% to 100%. With such a setting, it is possible to avoid the situation where the above ratio is too small, and the setting of the second opening 133 cannot effectively improve the bonding force between the plastic encapsulation layer and the lead frame. It is also possible to avoid the situation where the depth of the second opening 133 is too large, resulting in low strength of the second pin 13 and too large resistance of the second pin 13, which affects the current-carrying capacity of the semiconductor structure where the lead frame is located. In some embodiments, the ratio of the size of the second opening 133 to the size of the second connecting portion 131 can be, for example, 50%, 60%, 70%, 80%, 90%, 100%, etc.

[0066] In one embodiment, in the width direction of the second pin 13, the minimum value of the size of the second opening 133 is the minimum size of the etching process, and the maximum value is less than the width of the second connecting portion 131.

[0067] In one embodiment, the width of the second connecting portion 131 is equal to the width of the second terminal portion 132. When forming a semiconductor structure based on a lead frame, the position of the edge of the encapsulation layer fluctuates, that is, the boundary line between the second connecting portion 11 and the second terminal portion 132 shifts. If the widths of the second connecting portion 131 and the second terminal portion 132 are different, it may cause the widths of the regions near and far from the encapsulation layer in the portion of the second lead 13 exposed from the encapsulation layer to be different. If the width of the region of the portion of the second lead 13 exposed from the encapsulation layer near the encapsulation layer is greater than the width of the region far from the encapsulation layer, when welding the semiconductor structure formed based on the lead frame to a circuit board, the portion of the second lead 13 near the encapsulation layer may contact the structure in the circuit board due to its large width, thereby causing a short - circuit problem. By setting the width of the second connecting portion 131 to be equal to the width of the second terminal portion 132, the widths of the portions of the second lead 13 exposed from the encapsulation layer can be made the same, avoiding the above - mentioned problem.

[0068] In one embodiment, as Figure 1 shown, the second connecting portions 131 of adjacent second leads 13 are arranged at intervals, and the second terminal portions 132 of adjacent second leads 13 are arranged at intervals. The connecting unit 10 further includes a plurality of second connecting structures 15, and the second terminal portions 132 of adjacent second leads 13 are connected by the second connecting structures 15. By providing the second connecting structures 15, the plurality of second leads 13 are connected into an integral structure, which can improve the strength of the lead frame and avoid the region of the second lead 13 between the two end portions sagging under the action of gravity due to the excessive length of the second lead 13, thereby affecting the quality of the formed semiconductor structure. In the prepared semiconductor structure, the second connecting structures 15 are removed.

[0069] The embodiment of the present application further provides a semiconductor structure. As Figure 2 and Figure 3 shown, the semiconductor structure includes a lead frame, a chip 20, a plurality of bonding wires 30, and an encapsulation layer 40.

[0070] The lead frame includes a connection unit 10, the unit 10 includes a base island 11 and a plurality of first pins 12 located on the side of the base island 11, and the plurality of first pins 12 are spaced apart from the base island 11. The first pin 12 includes a bonding portion 121, a first connection portion 122, and a first terminal portion 123 that are sequentially connected. The first connection portion 122 is located on a side of the bonding portion 121 away from the base island 11, and the first terminal portion 123 is located on a side of the first connection portion 122 away from the base island 11. The first pin 12 is provided with a first opening 124, and the first opening 124 is only located in the first connection portion 122. The chip 20 is mounted on the base island 11, and a first electrode 21, 22 is provided on a side of the chip 20 away from the base island 11. One end of the bonding wire 30 is bonded to the first electrode 21, 22, and the other end is welded to the bonding portion 121. The encapsulation layer 40 encapsulates the chip 20, the bonding wire 30, the base island 11, the bonding portion 121, and the first connection portion 122. The encapsulation layer 40 fills the first opening 124, and the first terminal portion 123 is exposed from the encapsulation layer 40.

[0071] In one embodiment, the first electrode 21 and the second electrode 22 are respectively connected to different first pins 12 through different bonding wires, and the first pins 12 electrically connected to the first electrode 21 and the second electrode 22 are spaced apart.

[0072] In one embodiment, the depth of the first opening 124 is less than the thickness of the first pin 12.

[0073] Further, the ratio of the depth of the first opening 124 to the thickness of the first pin 12 ranges from 35% to 60%.

[0074] In one embodiment, in the length direction of the first pin 12, the ratio of the size of the first opening 124 to the total size of the bonding portion 121 and the first connection portion 122 ranges from 20% to 40%.

[0075] In one embodiment, in the width direction of the first pin 12, the minimum value of the size of the first opening 124 is the minimum size of the etching process, and the maximum value is less than the width of the first connection portion 122.

[0076] In one embodiment, as Figure 2 and Figure 3 shown, the plurality of first pins 12 are located on the same side of the base island 11, and the bonding portions 121 of at least two of the first pins 12 are connected.

[0077] In one embodiment, as Figure 2 and Figure 3As shown, the first terminal portion 123 of the first pin 12 is bent-shaped.

[0078] In one embodiment, the width of the first connection portion 122 is equal to the width of the first terminal portion 123.

[0079] In one embodiment, as Figure 2 and Figure 3 shown, the lead frame further includes a plurality of second pins 13. The plurality of second pins 13 include a second connection portion 131 and a second terminal portion 132 located on a side of the second connection portion 131 away from the base island 11. The second connection portion 131 is directly connected to the base island 11. The second pin 13 is provided with a second opening 133, and the second opening 133 is only located in the second connection portion 131. A second electrode is provided on a side of the chip 20 facing the base island 11, and the second electrode is electrically connected to the base island 11. The encapsulation layer 40 encapsulates the second connection portion 131, the encapsulation layer 40 fills the second opening 133, and the second terminal portion 132 is exposed from the encapsulation layer 40.

[0080] In one embodiment, the depth of the second opening 133 is less than the thickness of the second pin 13.

[0081] Furthermore, the ratio range of the depth of the second opening 133 to the thickness of the second pin 13 is 35% to 60%.

[0082] In one embodiment, in the width direction of the second pin 13, the ratio range of the size of the second opening 133 to the size of the second connection portion 131 is 50% to 100%.

[0083] In one embodiment, in the width direction of the second pin 13, the minimum value of the size of the second opening 133 is the minimum size of the etching process, and the maximum value is less than the width of the second connection portion 131.

[0084] In one embodiment, as Figure 2 and Figure 3 shown, the second terminal portion 132 of the second pin 13 is bent-shaped.

[0085] In one embodiment, as Figure 2 and Figure 3 shown, adjacent second pins 13 are spaced apart.

[0086] In one embodiment, the width of the second connection portion 131 is equal to the width of the second terminal portion 132.

[0087] In one embodiment, the semiconductor structure further includes a conductive bonding layer located between the base island 11 and the chip 20, and the chip 20 is bonded to the base island 11 through the conductive bonding layer. The conductive bonding layer can be, for example, solder paste, silver paste, etc.

[0088] The embodiments of the semiconductor structure provided in this application and the embodiments of the lead frame belong to the same inventive concept. For the description of related details and beneficial effects, reference can be made to each other, and details will not be repeated here.

[0089] It should be noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Further, it can be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Like reference numerals throughout indicate like elements.

[0090] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0091] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A lead frame, characterized in that, the lead frame includes a frame body and at least one connecting unit located within the frame body; the connecting unit includes: a base island; a plurality of first pins located on the side of the base island, the plurality of first pins being spaced apart from the base island; the first pins include a bonding portion, a first connecting portion, and a first terminal portion that are sequentially connected; the bonding portion is used for bonding with a bonding wire; the first connecting portion is located on the side of the bonding portion away from the base island, and the first terminal portion is located on the side of the first connecting portion away from the base island; the first pin is provided with a first opening, and the first opening is only located in the first connecting portion.

2. The lead frame according to claim 1, characterized in that, the depth of the first opening is less than the thickness of the first pin.

3. The lead frame according to claim 2, characterized in that, the ratio range of the depth of the first opening to the thickness of the first pin is 35% - 60%.

4. The lead frame according to claim 1, characterized in that, in the length direction of the first pin, the ratio range of the size of the first opening to the total size of the bonding portion and the first connecting portion is 20% - 40%; and / or, in the width direction of the first pin, the minimum value of the size of the first opening is the minimum size of the etching process, and the maximum value is less than the width of the first connecting portion; and / or, the plurality of first pins are located on the same side of the base island, and the bonding portions of at least two of the first pins are connected; and / or, the width of the first connecting portion is equal to the width of the first terminal portion.

5. The lead frame according to claim 1, characterized in that, the connecting unit further includes a plurality of second pins, the plurality of second pins include a second connecting portion and a second terminal portion located on the side of the second connecting portion away from the base island, the second connecting portion is directly connected to the base island; the second pin is provided with a second opening, and the second opening is only located in the second connecting portion.

6. The lead frame according to claim 5, characterized in that, the depth of the second opening is less than the thickness of the second pin; and / or, in the length direction of the second pin, the ratio range of the size of the second opening to the total size of the second connecting portion is 50% - 100%; and / or, in the width direction of the second pin, the minimum value of the size of the second opening is the minimum size of the etching process, and the maximum value is less than the width of the second connecting portion; and / or, the width of the second connecting portion is the same as the width of the second terminal portion.

7. A semiconductor structure, characterized in that, the semiconductor structure includes: A lead frame, the lead frame includes a base island and a plurality of first pins located on the side of the base island, and the plurality of first pins are spaced apart from the base island; the first pins include a bonding portion, a first connecting portion, and a first terminal portion that are sequentially connected; the first connecting portion is located on the side of the bonding portion away from the base island, and the first terminal portion is located on the side of the first connecting portion away from the base island; the first pin is provided with a first opening, and the first opening is only located in the first connecting portion; A chip mounted on the base island, and a first electrode is provided on the side of the chip away from the base island; A plurality of bonding wires, one end of the bonding wire is bonded to the first electrode, and the other end is bonded to the bonding portion; A plastic encapsulation layer encapsulates the chip, the bonding wire, the base island, the bonding portion, and the first connecting portion, the plastic encapsulation layer fills the first opening, and the first terminal portion exposes the plastic encapsulation layer.

8. The semiconductor structure according to claim 7, wherein, the depth of the first opening is less than the thickness of the first pin; and / or, in the length direction of the first pin, the ratio range of the size of the first opening to the total size of the bonding portion and the first connecting portion is 20% to 40%; and / or, in the width direction of the first pin, the minimum value of the size of the first opening is the minimum size of the etching process, and the maximum value is less than the width of the first connecting portion; and / or, the width of the first connecting portion is equal to the width of the first terminal portion.

9. The semiconductor structure according to claim 7, wherein, the lead frame further includes a plurality of second pins, the second pins include a second connecting portion and a second terminal portion located on the side of the second connecting portion away from the base island, and the second connecting portion is directly connected to the base island; the second pin is provided with a second opening, and the second opening is only located in the second connecting portion; a second electrode is provided on the side of the chip facing the base island, and the second electrode is electrically connected to the base island; the plastic encapsulation layer encapsulates the second connecting portion, the plastic encapsulation layer fills the second opening, and the second terminal portion exposes the plastic encapsulation layer.

10. The semiconductor structure according to claim 9, wherein, the depth of the second opening is less than the thickness of the second pin; and / or, in the length direction of the second pin, the ratio range of the size of the second opening to the total size of the second connecting portion is 50% to 100%; and / or, in the width direction of the second pin, the minimum value of the size of the second opening is the minimum size of the etching process, and the maximum value is less than the width of the second connecting portion; and / or, the width of the second connecting portion is the same as the width of the second terminal portion.

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