High-precision narrow pulse generator

Abstract

The invention discloses a high-precision narrow pulse generator which comprises an FPGA circuit, a laser driving circuit and a laser which are electrically connected in sequence. The FPGA circuit comprises a D trigger, a global clock buffer BUFG, an MUX8 and eight MUX2. The narrow pulse generator can generate pulse signals with high precision, narrow pulse width, steep edges and high stability, can be widely applied to various electronic devices and systems with high pulse quality requirements, improves the applicability, has excellent market prospects, and is suitable for popularization and application. When the method is applied to the automobile radar, the recognition precision can be greatly improved, and the driving safety is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse generators, and particularly to a high-precision narrow pulse generator. Background Art

[0002] Narrow pulse generators are widely used in many fields such as communication, radar, electronic measurement, etc. With the continuous development of automotive autonomous driving, in order to ensure the accurate recognition of the surrounding environment by the vehicle, the requirements for pulse generators by automotive radars are getting higher and higher, so as to meet the higher requirements for safe driving. Traditional pulse generators often have difficulty in simultaneously meeting the requirements of high precision, narrow pulse width, and high stability, and there are deficiencies in the steepness of the pulse rising edge and falling edge and the precise control of the pulse width, which limits their use in application scenarios with demanding pulse quality requirements. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a high-precision narrow pulse generator that can generate pulse signals with high precision, narrow pulse width, steep edges, and high stability, which can be widely used in various electronic devices and systems with high requirements for pulse quality, improving the applicability of the narrow pulse generator, having excellent market prospects, and can greatly improve the recognition accuracy when applied to automotive radars, ensuring driving safety.

[0004] A high-precision narrow pulse generator provided by the present invention includes an FPGA circuit, a laser driving circuit, and a laser, which are electrically connected in sequence; The FPGA circuit includes: A D flip-flop with its D pin set to 1; A global clock buffer BUFG, one end of which is connected to the Q pin of the D flip-flop, and the other end is connected to the laser driving circuit; Eight MUX2s, with the 0 pins of each MUX2 set to 0, the 1 pin and the SEL pin of the first MUX2 both connected to the Q pin of the D flip-flop, the output terminals of the 1st - 7th MUX2s are connected to the 1 pins of the 2nd - 8th MUX2s in one-to-one correspondence, and the SEL pins of the 2nd - 8th MUX2s are all set to 1; A MUX8, its 0 - 7 pins are connected to the output terminals of the eight MUX2s in one-to-one correspondence, and its output terminal is connected to the CLR pin of the D flip-flop.

[0005] Further, the laser driving circuit includes: A pulse driving chip U1, its 1 pin is connected to the FPGA circuit, and its 2 pin and 6 pin are grounded; A capacitor C1, its first end is connected to the 3 pin of the pulse driving chip U1, and its second end is grounded; A capacitor C2, which is connected in parallel with the capacitor C1; The magnetic bead FB1, its first end is connected to the power supply, and its second end is connected to pin 3 of the pulse drive chip U1; The gallium nitride power MOS chip U2, its pin 1 is connected to pins 4 and 5 of the pulse drive chip U1, its pins 2, 5, and 6 are grounded, and its pins 3 and 4 are connected to the laser; The Schottky diode D1, its anode is connected to the power supply, and its cathode is connected to pins 3 and 4 of the gallium nitride power MOS chip U2; The Schottky diode D2 is in parallel with the Schottky diode D1; The MOS transistor M1, its drain is connected to the power supply, and its source and gate are connected to pins 3 and 4 of the gallium nitride power MOS chip U2; The bidirectional voltage regulator diode D3, its first end is connected to pins 3 and 4 of the gallium nitride power MOS chip U2, and its second end is grounded; The bidirectional voltage regulator diode D4 is in parallel with the bidirectional voltage regulator diode D3.

[0006] Compared with the prior art, the beneficial effects of the present invention are: The narrow pulse generator of the present invention realizes step-by-step ps-level narrow pulse output through the combination of MUX2 and MUX8, and can generate pulse signals with high precision, narrow pulse width, steep edges and high stability. It can be widely applied to various electronic devices and systems with high requirements for pulse quality, improving the applicability of the narrow pulse generator and having excellent market prospects. When applied to automotive radar, it can greatly improve its recognition accuracy and ensure driving safety.

[0007] It should be understood that the content described in the summary of the invention part is not intended to limit the key or important features of the embodiments of the present invention, nor to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Brief Description of the Drawings

[0008] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects and advantages of the present invention will become more apparent: Figure 1 It is a connection schematic diagram of a high-precision narrow pulse generator; Figure 2 It is a circuit structure schematic diagram of the FPGA circuit; Figure 3 It is a circuit structure schematic diagram of the laser drive circuit; Figure 4 It is a pulse signal schematic diagram of the FPGA circuit. Detailed Embodiments

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. In addition, it should be noted that for the convenience of description, only the parts related to the invention are shown in the drawings.

[0010] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and embodiments.

[0011] Please refer to Figures 1 to 4 , an embodiment of the present invention provides a high-precision narrow pulse generator, which includes an FPGA circuit, a laser driving circuit, and a laser connected in sequence electrically; The FPGA circuit includes: A D flip-flop, with its D pin set to 1; A global clock buffer BUFG, one end of which is connected to the Q pin of the D flip-flop, and the other end is connected to the laser driving circuit; Eight MUX2s, the 0 pin of each MUX2 is set to 0, the 1 pin and the SEL pin of the first MUX2 are both connected to the Q pin of the D flip-flop, the output ends of the 1st - 7th MUX2s are connected to the 1 pins of the 2nd - 8th MUX2s in one-to-one correspondence, and the SEL pins of the 2nd - 8th MUX2s are all set to 1; A MUX8, its 0 - 7 pins are connected to the output ends of the eight MUX2s in one-to-one correspondence, and its output end is connected to the CLR pin of the D flip-flop.

[0012] In this embodiment, as Figure 2 shown, the Q pin of the D flip-flop is its output, the MUX2 (2-to-1 multiplexer) and the global clock buffer BUFG are both logical resources of the FPGA circuit, the D pin of the D flip-flop is set to 1, and Hit is a single clock cycle signal generated inside the FPGA circuit.

[0013] The eight MUX2s are numbered 0 - 7 in sequence; the 0 pin of each MUX2 is connected to 0, the 1 pin and the SEL pin of MUX2-0 are both connected to the Q pin of the D flip-flop. The output ends of each MUX2 numbered 0 - 6 are connected to the 1 pins of the MUX2s numbered 1 - 7 in one-to-one correspondence (number 0 corresponds to 1, number 1 corresponds to 2, and so on); the SEL pins of the MUX2s numbered 1 - 7 are all set to 1. The output ends of each MUX2 are respectively connected to the corresponding input pins of the MUX8 (8-to-1 multiplexer). The Q pin of the D flip-flop is connected to the BUFG, and then output from the IO pin. Optionally, this IO pin is the global clock pin of the FPGA circuit.

[0014] The input selection of the MUX8 is its SEL pin. As Figure 3As shown, when there is no Hit signal, the default output of the Q pin is 0. When the pulse signal of Hit arrives, after the internal signal transmission delay of the D flip-flop, the Q output is 1. At this time, MUX2-0 switches from the 0-end input to the 1-end input, and the MUX2 numbered 1-7 outputs high level in sequence. MUX8 selects the input of its pins 0-7 as the output according to the input of the SEL pin. When the output of MUX8 is high, then the CLR pin of the D flip-flop is high, and the Q pin output of the D flip-flop becomes 0, resulting in the MUX2 numbered 0-7 becoming low level in sequence.

[0015] Figure 3 Taking the output of MUX2-7 as an example. In some other embodiments, the outputs of MUX2-0, MUX2-1, MUX2-2, MUX2-3, MUX2-4, MUX2-5, MUX2-6, and MUX2-7 can be arbitrarily selected according to the value of the SEL pin of MUX8; thus, the output of MUX8 can be selected in sequence to adjust the output value of the Q pin of the D flip-flop in a step-by-step manner.

[0016] Since the delays of MUX2 and MUX8 inside the FPGA circuit are at the level of several ps, the output of the Q pin is a pulse width at the level of 10 ps. The output of the Q pin is sent to BUFG and then output to the IO pin, thus realizing the output of the IO pin driving the laser through the laser driving circuit.

[0017] The narrow pulse generator of the present application realizes a step-by-step ps-level narrow pulse output through the combination of MUX2 and MUX8, and can generate pulse signals with high precision, narrow pulse width, steep edges, and high stability. It can be widely applied to various electronic devices and systems with high requirements for pulse quality, improving the applicability of the narrow pulse generator and having excellent market prospects. Applied to automotive radar, it can greatly improve its recognition accuracy and ensure driving safety.

[0018] In a preferred embodiment, as Figure 3 shown, the laser driving circuit includes: Pulse driving chip U1, its pin 1 is connected to the FPGA circuit, and its pins 2 and 6 are grounded; Capacitor C1, its first end is connected to pin 3 of the pulse driving chip U1, and its second end is grounded; Capacitor C2, in parallel with capacitor C1; Bead FB1, its first end is connected to the power supply, and its second end is connected to pin 3 of the pulse driving chip U1; Gallium nitride power MOS chip U2, its pin 1 is connected to pins 4 and 5 of the pulse driving chip U1, its pins 2, 5, and 6 are grounded, and its pins 3 and 4 are connected to the laser; Schottky diode D1, whose anode is connected to the power supply, and whose cathode is connected to pins 3 and 4 of the gallium nitride power MOS chip U2; Schottky diode D2, which is connected in parallel with Schottky diode D1; MOS transistor M1, whose drain is connected to the power supply, and whose source and gate are connected to pins 3 and 4 of the gallium nitride power MOS chip U2; Bidirectional voltage-regulating diode D3, whose first end is connected to pins 3 and 4 of the gallium nitride power MOS chip U2, and whose second end is grounded; Bidirectional voltage-regulating diode D4, which is connected in parallel with bidirectional voltage-regulating diode D3.

[0019] In this embodiment, the input signal is driven by the pulse driving chip U1, and then the cooperation between the gallium nitride power MOS chip U2 and the MOS transistor M1 ensures that the output pulse signal can stably and reliably drive various load devices.

[0020] In the description of this specification, the descriptions of terms such as "one embodiment", "some embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or instance. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0021] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A high-precision narrow pulse generator, characterized in that: including an FPGA circuit, a laser driving circuit and a laser which are electrically connected in sequence; The FPGA circuit comprises: The D-pin of a D flip-flop is set to 1; A global clock buffer BUFG, one end of which is connected to the Q pin of the D flip-flop, and the other end of which is connected to the laser driving circuit; There are 8 MUX2s, with the 0-pin of each MUX2 set to 0, the 1-pin and SEL pin of the first MUX2 connected to the Q pin of the D flip-flop, the outputs of the 1st to 7th MUX2s are connected to the 1-pins of the 2nd to 8th MUX2s one by one, and the SEL pins of the 2nd to 8th MUX2s are all set to 1; MUX8, its 0-7 pins are connected to the output ends of 8 MUX2s one by one, and its output end is connected to the CLR pin of the D flip-flop.

2. The high-precision narrow pulse generator according to claim 1, characterized in that: The laser driving circuit comprises: The pulse driving chip U1 has its pin 1 connected to the FPGA circuit, and its pins 2 and 6 are grounded; A capacitor C1, a first end of which is connected to pin 3 of the pulse driving chip U1, and a second end of which is grounded; Capacitor C2, connected in parallel with capacitor C1; A magnetic bead FB1, a first end of which is connected to a power source, and a second end of which is connected to pin 3 of the pulse driving chip U1; Gallium nitride power MOS chip U2, whose pin 1 is connected to pins 4 and 5 of the pulse driver chip U1, whose pins 2, 5 and 6 are grounded, and whose pins 3 and 4 are connected to the laser; Schottky diode D1, with its anode connected to the power supply, and its cathode connected to pins 3 and 4 of the GaN power MOS chip U2; Schottky diode D2, connected in parallel with Schottky diode D1; MOS tube M1, its drain is connected to the power supply, and its source and gate are connected to pins 3 and 4 of the GaN power MOS chip U2; A bidirectional voltage regulator diode D3, a first end of which is connected to pins 3 and 4 of the gallium nitride power MOS chip U2, and a second end of which is grounded; The bidirectional voltage regulator diode D4 is connected in parallel with the bidirectional voltage regulator diode D3.

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