Circuit for level conversion

Abstract

The invention discloses a circuit for level conversion. The circuit comprises a bootstrap circuit used for converting an input voltage into a control voltage; the level conversion circuit is used for providing output voltage according to the control voltage, the level of the output voltage is higher than that of the input voltage, and the voltage amplitude of the control voltage is larger than or equal to two times of the voltage amplitude of the input voltage. According to the circuit, the level conversion circuit is controlled to perform level conversion by using the control voltage with a relatively high voltage amplitude, relatively high current can be generated, and the level conversion speed is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly, to a circuit for level conversion. Background Art

[0002] With the continuous improvement of the design complexity of integrated circuits, integrated circuits have put forward higher requirements for characteristics such as integration, stability, and compatibility. Mixed-signal chips, with their advantages such as high integration, intelligence and automation, high reliability and stability, multi-core and parallel processing, and the development trend of customization and personalization, are widely used in various fields such as communication, medical treatment, and industrial control.

[0003] However, with the development of integrated circuit process technology, the voltage in the digital voltage domain has become lower and lower, while the voltage in the analog voltage domain remains almost unchanged or even becomes higher in special processes. When a low-voltage digital circuit signal is output to a high-voltage analog circuit, a level conversion circuit is required for level conversion. As the digital frequency becomes higher and higher, the speed requirement for the level conversion circuit is also higher and higher. The larger the voltage amplitude of the conversion from digital low level to analog high level, the slower the conversion speed of the level conversion circuit. Therefore, the traditional level conversion circuit cannot meet the demand of integrated circuits for level conversion speed.

[0004] Therefore, it is desirable to provide an improved level conversion circuit to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a circuit for level conversion to improve the level conversion speed.

[0006] According to one aspect of the present invention, there is provided a circuit for level conversion, comprising:

[0007] A bootstrap circuit for converting an input voltage into a control voltage; and

[0008] A level conversion circuit for providing an output voltage according to the control voltage, the level of the output voltage being higher than the level of the input voltage,

[0009] wherein the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

[0010] Optionally, the control voltage includes complementary first voltage and second voltage, and the bootstrap circuit includes a first branch and a second branch having the same circuit structure,

[0011] The first branch uses a first capacitor for charging and discharging to obtain the first voltage, and the charging and discharging path of the first branch is controlled by the inverted voltage of the input voltage;

[0012] The second branch charges and discharges using a second capacitor to obtain the second voltage, and the charge and discharge path of the second branch is controlled by the input voltage.

[0013] Optionally, when the input voltage is at a low level, the first power supply charges the first capacitor, the first voltage is pulled down to the reference ground, the second capacitor starts to discharge to provide the second voltage, and the path from the second voltage to the reference ground is turned off;

[0014] When the input voltage is at a high level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is turned off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

[0015] Optionally, the first branch includes:

[0016] A first inverter for converting the inverted voltage of the input voltage into a first intermediate voltage;

[0017] A first switching transistor connected between the first power supply and the first end of the first capacitor;

[0018] A second switching transistor connected between the first end of the first capacitor and the first output terminal;

[0019] A third switching transistor connected between the first output terminal and the reference ground;

[0020] The first capacitor, whose second end is connected to the output terminal of the first inverter;

[0021] Wherein, the first switching transistor is controlled by the first intermediate voltage, and the second switching transistor and the third switching transistor are controlled by the inverted voltage of the input voltage;

[0022] The second branch includes:

[0023] A second inverter for converting the input voltage into a second intermediate voltage;

[0024] A fourth switching transistor connected between the first power supply and the first end of the second capacitor;

[0025] A fifth switching transistor connected between the first end of the second capacitor and the second output terminal;

[0026] A sixth switching transistor connected between the second output terminal and the reference ground;

[0027] The second capacitor, whose second end is connected to the output terminal of the second inverter;

[0028] Wherein, the fourth switching transistor is controlled by the second intermediate voltage, and the fifth and sixth switching transistors are controlled by the input voltage;

[0029] The first, second, fourth, and fifth switching transistors have the same conduction type, and are opposite to the conduction types of the third and sixth switching transistors.

[0030] Optionally, the bootstrap circuit further includes an initial inverter for obtaining an inverted voltage of the input voltage based on the input voltage.

[0031] Optionally, the control voltage includes complementary first and second voltages, and the level conversion circuit includes:

[0032] A current mirror circuit including a third branch and a fourth branch;

[0033] A seventh switching transistor connected to the third branch, the seventh switching transistor being controlled by the first voltage; and

[0034] An eighth switching transistor connected to the fourth branch, the eighth switching transistor being controlled by the second voltage.

[0035] Optionally, the level conversion circuit further includes:

[0036] A ninth switching transistor connected between the second power supply and the third branch, controlled by the output voltage; and

[0037] A tenth switching transistor connected between the fourth branch and the eighth switching transistor and controlled by the second voltage, the connection node of the tenth and eighth switching transistors providing the output voltage.

[0038] Optionally, the level conversion circuit further includes:

[0039] A ninth switching transistor connected between the third branch and the seventh switching transistor, controlled by the output voltage; and

[0040] A tenth switching transistor connected between the fourth branch and the eighth switching transistor and controlled by the second voltage, the connection node of the tenth and eighth switching transistors providing the output voltage.

[0041] Optionally, the level conversion circuit further includes: a ninth switching transistor connected between the third branch and the seventh switching transistor, controlled by the output voltage.

[0042] Optionally, when the output voltage is at a high level, the ninth switching transistor is turned off.

[0043] The circuit for level conversion provided by the present invention uses a control voltage with a relatively high voltage amplitude to control the level conversion circuit to perform level conversion, which can generate a relatively large current and significantly improve the level conversion speed.

[0044] In some alternative embodiments, the circuit improves the current mirror circuit, eliminates the static current, and has the advantages of low power consumption and anti-leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become more apparent. In the drawings:

[0046] Figure 1 A schematic diagram of a circuit for level conversion according to a first embodiment of the present invention is shown;

[0047] Figure 2 A schematic diagram of a bootstrap circuit according to an embodiment of the present invention is shown;

[0048] Figure 3 A signal waveform diagram of voltages at various parts of a circuit for level conversion according to an embodiment of the present invention is shown;

[0049] Figure 4 A schematic diagram of a circuit for level conversion according to a second embodiment of the present invention is shown;

[0050] Figure 5 A schematic diagram of a circuit for level conversion according to a third embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] The present invention will be described in more detail below with reference to the drawings. In each of the drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0052] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques, and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0053] It should be understood that the connection / coupling between A and B in the embodiments of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0054] Embodiments of a circuit for level conversion provided by the present application will be described below with reference to the drawings.

[0055] Figure 1Shows a schematic diagram of a circuit for level conversion according to a first embodiment of the present invention; Figure 2 Shows a schematic diagram of a bootstrap circuit according to an embodiment of the present invention; Figure 3 Shows a signal waveform diagram of voltages at various parts of a circuit for level conversion according to an embodiment of the present invention.

[0056] As Figure 1 Shown, the circuit 100 for level conversion provided by the embodiment of the present invention includes a bootstrap circuit 110 and a level conversion circuit 120, and this circuit 100 can convert an input voltage VIN into an output voltage VOUT.

[0057] In some embodiments, this circuit 100 is applied to a display driver chip, a power chip, etc., or is applied to a system on chip (SoC) or a digital - analog hybrid circuit. The input voltage VIN is applied to the digital circuit part in these chips or circuits, and its voltage amplitude is relatively low. The output voltage VOUT is applied to the analog circuit part in these chips or circuits, and its voltage amplitude is relatively high.

[0058] The bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage. Specifically, the control voltage at least includes a first voltage VP and a second voltage VN, and the first voltage VP and the second voltage VN are complementary. For example, when the first voltage VP is at a high level, the second voltage VN is at a low level; when the first voltage VP is at a low level, the second voltage VN is at a high level. The voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage VIN. For example, if the high level of the input voltage VIN is VDDL, then the high levels of both the first voltage VP and the second voltage VN are 2*VDDL, and if the low level of the input voltage VIN is 0, then the low levels of both the first voltage VP and the second voltage VN are also 0.

[0059] The level conversion circuit 120 is used to provide the output voltage VOUT according to the control voltage, and the level of the output voltage VOUT is higher than the level of the input voltage VIN. In some embodiments, this level conversion circuit 120 realizes level conversion based on a current mirror.

[0060] In the embodiment of the present invention, the bootstrap circuit 110 is used to convert the input voltage VIN into a control voltage with a higher voltage amplitude, so that a larger current can be generated in the level conversion circuit 120, thereby improving the speed of level conversion.

[0061] Please refer to Figure 2, the bootstrap circuit 110 includes a first branch 111 and a second branch 112 with the same circuit structure. The first branch 111 charges and discharges using a first capacitor C1 to obtain a first voltage VP, and the charge and discharge path of the first branch 111 is controlled by the inverted voltage of the input voltage VIN; the second branch 112 charges and discharges using a second capacitor C2 to obtain a second voltage VN, and the charge and discharge path of the second branch 112 is controlled by the input voltage VIN. Since the first branch 111 and the second branch 112 are controlled by opposite voltages, the bootstrap circuit 110 can generate complementary first voltage VP and second voltage VN according to the input voltage VIN.

[0062] In this embodiment, when the input voltage VIN is at a low level, the first power supply VDDL charges the first capacitor C1, the first voltage VP is pulled down to the reference ground GND, the second capacitor C2 starts to discharge to provide the second voltage VN, and the path from the second voltage VN to the reference ground GND is turned off; when the input voltage VIN is at a high level, the first capacitor C1 starts to discharge to provide the first voltage VP, the path from the first voltage VP to the reference ground GND is turned off, the first power supply VDDL charges the second capacitor C2, and the second voltage VN is pulled down to the reference ground GND.

[0063] Specifically, the bootstrap circuit 110 includes an initial inverter INV0, a first branch 111, and a second branch 112. The input terminal of the initial inverter INV0 receives the input voltage VIN, and the output terminal provides the inverted voltage of the output voltage VOUT.

[0064] The first branch 111 includes a first inverter INV1, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, and a first capacitor C1. The input terminal of the first inverter INV1 is connected to the output terminal of the initial inverter INV0, and is used to convert the inverted voltage of the input voltage VIN into a first intermediate voltage VG1; the first switching transistor M1 is connected between the first power supply VDDL and the first end of the first capacitor C1; the second switching transistor M2 is connected between the first end of the first capacitor C1 and the first output terminal; the third switching transistor M3 is connected between the first output terminal and the reference ground GND; the second end of the first capacitor C1 is connected to the output terminal of the first inverter INV1; wherein, the first switching transistor M1 is controlled by the first intermediate voltage VG1, and the second switching transistor M2 and the third switching transistor M3 are controlled by the inverted voltage of the input voltage VIN. The first intermediate voltage VG1 is also equivalent to the voltage obtained by delaying the input voltage VIN.

[0065] The second branch 112 includes a second inverter INV2, a fourth switching transistor M4, a fifth switching transistor M5, a sixth switching transistor M6, and a second capacitor C2. The input terminal of the second inverter INV2 is connected to the input voltage VIN, and is configured to convert the input voltage VIN into a second intermediate voltage VG2; the fourth switching transistor M4 is connected between the first power supply VDDL and the first terminal of the second capacitor C2; the fifth switching transistor M5 is connected between the first terminal of the second capacitor C2 and the second output terminal; the sixth switching transistor M6 is connected between the second output terminal and the reference ground GND; the second terminal of the second capacitor C2 is connected to the output terminal of the second inverter INV2; wherein, the fourth switching transistor M4 is controlled by the second intermediate voltage VG2, and the fifth switching transistor M5 and the sixth switching transistor M6 are controlled by the input voltage VIN. The second intermediate voltage VG2 is also equivalent to the inverted voltage of the input voltage VIN.

[0066] In this embodiment, the first switching transistor M1, the second switching transistor M2, the fourth switching transistor M4, and the fifth switching transistor M5 have the same conduction type, and are opposite to the conduction types of the third switching transistor M3 and the sixth switching transistor M6. For example, the first switching transistor M1, the second switching transistor M2, the fourth switching transistor M4, and the fifth switching transistor M5 are all P-type metal oxide semiconductor field effect transistors (Positive Channel Metal Oxide Semiconductor, PMOS), and the third switching transistor M3 and the sixth switching transistor M6 are both N-type metal oxide semiconductor field effect transistors (Negative Channel Metal Oxide Semiconductor, NMOS).

[0067] Taking the first branch 111 as an example, the low level of the input voltage VIN is, for example, 0, and the high level is, for example, VDDL. When the input voltage VIN is at the low level, the inverted voltage of the input voltage VIN is at the high level, and the first intermediate voltage VG1 provided by the first inverter INV1 is at the low level. At this time, the first switching transistor M1 is turned on, the second switching transistor M2 is turned off, and the third switching transistor M3 is turned on. The charging path from the first power supply VDDL to the first capacitor C1 is turned on, and the first capacitor C1 is charged to the VDDL voltage. The discharging path from the first capacitor C1 to the first output terminal is turned off, and the current path between the first output terminal and the reference ground GND is turned on. Therefore, the first voltage VP provided by the first output terminal is at the low level. When the input voltage VIN is at the high level, the inverted voltage of the input voltage VIN is at the low level, and the first intermediate voltage VG1 provided by the first inverter INV1 is at the high level. At this time, the first switching transistor M1 is turned off, the second switching transistor M2 is turned on, and the third switching transistor M3 is turned off. The charging path from the first power supply VDDL to the first capacitor C1 is turned off, the discharging path from the first capacitor C1 to the first output terminal is turned on, and the current path between the first output terminal and the reference ground GND is turned off. Based on the principle that the voltage of a capacitor cannot change suddenly, at this time, the voltage at the first end of the first capacitor C1 becomes VDDL + VDDL = 2 * VDDL, that is, the first voltage VP provided by the first output terminal becomes 2 * VDDL. Therefore, when the input voltage VIN changes from the low level to the high level, the first voltage VP also changes from the low level to the high level, and the high level of the first voltage VP is twice the high level of the input voltage VIN.

[0068] The circuit structure of the second branch 112 is the same as that of the first branch 111, and its voltage conversion relationship can also be derived by describing the working principle of the first branch 111. Specifically, the low level of the input voltage VIN is, for example, 0, and the high level is, for example, VDDL. When the input voltage VIN is at the high level, the second intermediate voltage VG2 provided by the second inverter INV2 is at the low level. At this time, the fourth switching transistor M4 is turned on, the fifth switching transistor M5 is turned off, and the sixth switching transistor M6 is turned on. The charging path from the first power supply VDDL to the second capacitor C2 is turned on, and the second capacitor C2 is charged to the VDDL voltage. The discharging path from the second capacitor C2 to the second output terminal is turned off, and the current path between the second output terminal and the reference ground GND is turned on. Therefore, the second voltage VN provided by the second output terminal is at the low level. When the input voltage VIN is at the low level, the second intermediate voltage VG2 provided by the second inverter INV2 is at the high level. At this time, the fourth switching transistor M4 is turned off, the fifth switching transistor M5 is turned on, and the sixth switching transistor M6 is turned off. The charging path from the first power supply VDDL to the second capacitor C2 is turned off, the discharging path from the second capacitor C2 to the second output terminal is turned on, and the current path between the second output terminal and the reference ground GND is turned off. Based on the principle that the voltage of a capacitor cannot change suddenly, at this time, the voltage at the first end of the second capacitor C2 becomes VDDL + VDDL = 2 * VDDL, that is, the second voltage VN provided by the first output terminal becomes 2 * VDDL. Therefore, when the input voltage VIN changes from the high level to the low level, the second voltage VN changes from the low level to the high level, and the high level of the second voltage VN is twice the high level of the input voltage VIN.

[0069] It should be understood that the circuit structures of the foregoing first branch 111 and second branch 112 are only a schematic example, and those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the voltage value of the first power supply VDDL can be the same as the input voltage VIN, so that the voltage amplitude of the first voltage VP is approximately twice the voltage amplitude of the input voltage VIN; the voltage value of the first power supply VDDL can be greater than the input voltage VIN, so that the voltage amplitude of the first voltage VP is greater than twice the voltage amplitude of the input voltage VIN. By adjusting the voltage value of the first power supply VDDL, the voltage amplitude of the first voltage VP can be controlled.

[0070] In this embodiment, the level conversion circuit 120 includes a current mirror circuit, a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9, and a tenth switching transistor M10. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switching transistor M7 is connected to the third branch 121 and is controlled by a first voltage VP. The eighth switching transistor M8 is connected to the fourth branch 122 and is controlled by a second voltage VN. The ninth switching transistor M9 is connected between the second power supply VDDH and the third branch 121 and is controlled by the output voltage VOUT. The tenth switching transistor M10 is connected between the fourth branch 122 and the eighth switching transistor M8 and is controlled by the second voltage VN. The connection node of the tenth switching transistor M10 and the eighth switching transistor M8 serves as the output end of the level conversion circuit 120 and provides the output voltage VOUT.

[0071] As an example, the third branch 121 includes an eleventh switching transistor M11, and the fourth branch 122 includes a twelfth switching transistor M12. The first current terminal of the eleventh switching transistor M11 is connected to the second power supply VDDH through the ninth switching transistor M9. The second current terminal of the eleventh switching transistor M11 is connected to the reference ground GND through the seventh switching transistor M7. The control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and is connected to the second current terminal of the eleventh switching transistor M11. The first current terminal of the twelfth switching transistor M12 is directly connected to the second power supply VDDH. The second current terminal of the twelfth switching transistor M12 is connected to the reference ground GND through the tenth switching transistor M10 and the eighth switching transistor M8 in sequence.

[0072] In this example, the seventh switching transistor M7 and the eighth switching transistor M8 are NMOS transistors, and the ninth switching transistor M9, the tenth switching transistor M10, the eleventh switching transistor M11, and the twelfth switching transistor M12 are all PMOS transistors.

[0073] In this example, for instance, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VP and the second voltage VN are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VP, and the second voltage VN are all 0.

[0074] When the input voltage VIN is at a high level, the first voltage VP provided by the bootstrap circuit 110 is at a high level and the second voltage VN is at a low level. The seventh switching transistor M7 and the tenth switching transistor M10 are turned on, and the eighth switching transistor M8 is turned off. The gate voltage of the eleventh switching transistor M11 is pulled down to the reference ground GND (usually at 0 level). Therefore, the eleventh switching transistor M11 and the twelfth switching transistor M12 are turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled up to VDDH. At this time, the ninth switching transistor M9 is turned off and the leakage path is closed. Therefore, the generation of leakage current is avoided, the static current is eliminated, and the circuit power consumption is reduced.

[0075] When the input voltage VIN is at a low level, the first voltage VP provided by the bootstrap circuit 110 is at a low level and the second voltage VN is at a high level. The seventh switching transistor M7 and the tenth switching transistor M10 are turned off, the eighth switching transistor M8 is turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled down to the reference ground GND voltage.

[0076] In this embodiment, the ninth switching transistor M9 and the tenth switching transistor M10 for eliminating the static current are provided. Therefore, it has the advantages of low power consumption and anti-leakage.

[0077] It should be understood that the circuit structure of the above-mentioned level conversion circuit 120 is only a schematic example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0078] After the circuit 100 for level conversion in the embodiment of the present invention undergoes the above signal processing process, the input voltage VIN with a lower level is converted into the output voltage VOUT with a higher level. Please refer to Figure 3 , the bootstrap circuit 110 converts the input voltage VIN with a voltage amplitude of VDDL into the first voltage VP and the second voltage VN with a voltage amplitude of 2*VDDL. The level conversion circuit 120 generates the output voltage VOUT with a voltage amplitude of VDDH based on the first voltage VP and the second voltage VN. The phases of the input voltage VIN and the output voltage VOUT are basically synchronized.

[0079] Some examples of the circuit for level conversion in the embodiment of the present invention are described above. However, the embodiment of the present invention is not limited thereto, and there may be other ways of expansion and deformation.

[0080] For example, it should be understood that the reference ground potential in the foregoing embodiment can be replaced with other non-zero reference potentials (with a positive voltage amplitude or a negative voltage amplitude) or a controlled variable reference signal in an alternative embodiment.

[0081] For another example, the capacitor provided in the embodiment of the present application may be a lumped-parameter capacitor element, or may be other equivalent elements with functions similar to those of a capacitor. The equivalent structures described herein include, for example but are not limited to, microstrip lines, varactor diodes, conductor structures with certain patterns, etc., which can provide capacitive impedance.

[0082] Meanwhile, those of ordinary skill in the art can realize that, for the structures and methods of each example described in combination with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or reasonable deformation of the structure, but such implementation should not be considered to exceed the scope of the present application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of the present application are illustrative examples and do not impose any limitations on the embodiments of the present application.

[0083] Figure 4 FIG. shows a schematic diagram of a circuit for level conversion according to the second embodiment of the present invention. The circuit structure of the bootstrap circuit 110 in the second embodiment of the present invention is exactly the same as that of the bootstrap circuit 110 in the first embodiment, and will not be described in detail herein.

[0084] In this embodiment, the level conversion circuit 120 includes a current mirror circuit, a seventh switching transistor M7, an eighth switching transistor M8, a ninth switching transistor M9, and a tenth switching transistor M10. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switching transistor M7 is connected to the third branch 121 and is controlled by a first voltage VP; the eighth switching transistor M8 is connected to the fourth branch 122 and is controlled by a second voltage VN. The ninth switching transistor M9 is connected between the third branch 121 and the seventh switching transistor M7 and is controlled by an output voltage VOUT; the tenth switching transistor M10 is connected between the fourth branch 122 and the eighth switching transistor M8 and is controlled by the second voltage VN. The connection node of the tenth switching transistor M10 and the eighth switching transistor M8 serves as the output end of the level conversion circuit 120 and provides the output voltage VOUT.

[0085] As an example, the third branch 121 includes an eleventh switching transistor M11, and the fourth branch 122 includes a twelfth switching transistor M12. The first current terminal of the eleventh switching transistor M11 is directly connected to the second power supply VDDH. The second current terminal of the eleventh switching transistor M11 is sequentially connected to the reference ground GND through the ninth switching transistor M9 and the seventh switching transistor M7. The control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and is connected to the second current terminal of the eleventh switching transistor M11. The first current terminal of the twelfth switching transistor M12 is directly connected to the second power supply VDDH. The second current terminal of the twelfth switching transistor M12 is sequentially connected to the reference ground GND through the tenth switching transistor M10 and the eighth switching transistor M8.

[0086] In this example, the seventh switching transistor M7 and the eighth switching transistor M8 are NMOS transistors, and the ninth switching transistor M9, the tenth switching transistor M10, the eleventh switching transistor M11, and the twelfth switching transistor M12 are all PMOS transistors.

[0087] In this example, for instance, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VP and the second voltage VN are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VP, and the second voltage VN are all 0.

[0088] When the input voltage VIN is at a high level, the first voltage VP provided by the bootstrap circuit 110 is at a high level and the second voltage VN is at a low level. The seventh switching transistor M7 and the tenth switching transistor M10 are turned on, and the eighth switching transistor M8 is turned off. The gate voltage of the eleventh switching transistor M11 is pulled down to the reference ground GND (usually at 0 level), so the eleventh switching transistor M11 and the twelfth switching transistor M12 are turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled up to VDDH. At this time, the ninth switching transistor M9 is turned off, and the leakage path is closed, thus avoiding the generation of leakage current and eliminating the static current, due to reducing the circuit power consumption.

[0089] When the input voltage VIN is at a low level, the first voltage VP provided by the bootstrap circuit 110 is at a low level and the second voltage VN is at a high level. The seventh switching transistor M7 and the tenth switching transistor M10 are turned off, the eighth switching transistor M8 is turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled down to the reference ground GND voltage.

[0090] In this embodiment, the ninth switching transistor M9 and the tenth switching transistor M10 for eliminating the static current are provided, so it has the advantages of low power consumption and anti-leakage.

[0091] It should be understood that the circuit structure of the above level conversion circuit 120 is only a schematic example, and those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0092] Figure 5 A schematic diagram of a circuit for level conversion according to the third embodiment of the present invention is shown.

[0093] In this embodiment, the level conversion circuit 120 includes a current mirror circuit, a seventh switching transistor M7, an eighth switching transistor M8, and a ninth switching transistor M9. The current mirror circuit includes a third branch 121 and a fourth branch 122. The third branch 121 is a current input branch, and the fourth branch 122 is a current output branch. The seventh switching transistor M7 is connected to the third branch 121 and is controlled by a first voltage VP. The eighth switching transistor M8 is connected to the fourth branch 122 and is controlled by a second voltage VN. The ninth switching transistor M9 is connected between the third branch 121 and the seventh switching transistor M7 and is controlled by the output voltage VOUT. The connection node of the fourth branch 122 and the eighth switching transistor M8 serves as the output terminal of the level conversion circuit 120 and provides the output voltage VOUT.

[0094] As an example, the third branch 121 includes an eleventh switching transistor M11, and the fourth branch 122 includes a twelfth switching transistor M12. The first current terminal of the eleventh switching transistor M11 is directly connected to the second power supply VDDH. The second current terminal of the eleventh switching transistor M11 is sequentially connected to the reference ground GND through the ninth switching transistor M9 and the seventh switching transistor M7. The control terminal of the eleventh switching transistor M11 is connected to the control terminal of the twelfth switching transistor M12 and is connected to the second current terminal of the eleventh switching transistor M11. The first current terminal of the twelfth switching transistor M12 is directly connected to the second power supply VDDH, and the second current terminal of the twelfth switching transistor M12 is connected to the reference ground GND through the eighth switching transistor M8.

[0095] In this example, the seventh switching transistor M7 and the eighth switching transistor M8 are NMOS transistors, and the ninth switching transistor M9, the eleventh switching transistor M11, and the twelfth switching transistor M12 are all PMOS transistors.

[0096] In this example, for instance, the high level of the input voltage VIN is set to VDDL, the high levels of the first voltage VP and the second voltage VN are both 2*VDDL, and the low levels of the input voltage VIN, the first voltage VP, and the second voltage VN are all 0.

[0097] When the input voltage VIN is at a high level, the first voltage VP provided by the bootstrap circuit 110 is at a high level and the second voltage VN is at a low level. The seventh switching transistor M7 is turned on, and the eighth switching transistor M8 is turned off. The gate voltage of the eleventh switching transistor M11 is pulled down to the reference ground GND (usually 0 level). Therefore, the eleventh switching transistor M11 and the twelfth switching transistor M12 are turned on, and the output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled up to VDDH. At this time, the ninth switching transistor M9 is turned off, and the leakage path is closed. Therefore, the generation of leakage current is avoided, and the static current is eliminated, reducing the circuit power consumption.

[0098] When the input voltage VIN is at a low level, the first voltage VP provided by the bootstrap circuit 110 is at a low level, and the second voltage VN is at a high level. The seventh switching transistor M7 is turned off, and the eighth switching transistor M8 is turned on. The output voltage VOUT provided by the output terminal of the level conversion circuit 120 is pulled down to the reference ground GND voltage.

[0099] In this embodiment, a ninth switching transistor M9 for eliminating static current is provided, so it has the advantages of low power consumption and anti-leakage.

[0100] It should be understood that the circuit structure of the above level conversion circuit 120 is only a schematic example. Those skilled in the art can achieve the same or similar technical effects by changing parameters such as the type of switching transistors and the corresponding circuit connection relationships. In addition, the magnitude of the output voltage VOUT can be adjusted by adjusting the voltage value of the second power supply VDDH.

[0101] In summary, the embodiment of the present invention provides a circuit for level conversion. By using a control voltage with a relatively high voltage amplitude to control the level conversion circuit 120 for level conversion, a relatively large current can be generated, significantly improving the level conversion speed.

[0102] In some optional embodiments, the circuit improves the current mirror circuit, eliminates static current, and has the advantages of low power consumption and anti-leakage.

[0103] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0104] As described above in accordance with the embodiments of the present invention, these embodiments do not describe all details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A circuit for level conversion, comprising: A bootstrap circuit for converting an input voltage into a control voltage; as well as a level conversion circuit, configured to provide an output voltage according to the control voltage, wherein the level of the output voltage is higher than the level of the input voltage, Wherein, the voltage amplitude of the control voltage is greater than or equal to twice the voltage amplitude of the input voltage.

2. The circuit according to claim 1, wherein The control voltage includes a complementary first voltage and a second voltage, the bootstrap circuit includes a first branch and a second branch having the same circuit structure, The first branch uses a first capacitor to charge and discharge to obtain the first voltage, and the charging and discharging path of the first branch is controlled by the inverse voltage of the input voltage; The second branch uses a second capacitor to charge and discharge to obtain the second voltage, and the charging and discharging path of the second branch is controlled by the input voltage.

3. The circuit according to claim 2, wherein: When the input voltage is at a low level, the first power supply charges the first capacitor, the first voltage is pulled down to the reference ground, the second capacitor starts to discharge to provide the second voltage, and the path from the second voltage to the reference ground is cut off; When the input voltage is at a high level, the first capacitor starts to discharge to provide the first voltage, the path from the first voltage to the reference ground is cut off, the first power supply charges the second capacitor, and the second voltage is pulled down to the reference ground.

4. The circuit according to claim 3, wherein: The first branch comprises: A first inverter, used for converting an inverted voltage of the input voltage into a first intermediate voltage; A first switch tube, connected between the first power supply and a first end of the first capacitor; A second switch tube is connected between the first end of the first capacitor and the first output end; A third switch tube is connected between the first output terminal and the reference ground; The first capacitor has a second end connected to the output end of the first inverter; Wherein, the first switch tube is controlled by the first intermediate voltage, and the second switch tube and the third switch tube are controlled by the inverse voltage of the input voltage; The second branch comprises: A second inverter, used for converting the input voltage into a second intermediate voltage; a fourth switch tube, connected between the first power supply and the first end of the second capacitor; a fifth switch tube, connected between the first end and the second output end of the second capacitor; a sixth switch tube, connected between the second output terminal and the reference ground; The second capacitor, a second end of which is connected to the output end of the second inverter; Wherein, the fourth switch tube is controlled by the second intermediate voltage, and the fifth switch tube and the sixth switch tube are controlled by the input voltage; The conduction types of the first switch tube, the second switch tube, the fourth switch tube and the fifth switch tube are the same, and opposite to the conduction types of the third switch tube and the sixth switch tube.

5. The circuit according to claim 2, wherein: The bootstrap circuit further includes an initial inverter for obtaining an inverted voltage of the input voltage according to the input voltage.

6. The circuit according to claim 1, wherein: The control voltage includes a complementary first voltage and a second voltage, and the level conversion circuit includes: A current mirror circuit includes a third branch and a fourth branch; a seventh switch tube, connected to the third branch, the seventh switch tube being controlled by the first voltage; and An eighth switch tube is connected to the fourth branch, and the eighth switch tube is controlled by the second voltage.

7. The circuit according to claim 6, wherein: The level conversion circuit further includes: a ninth switch tube, connected between the second power supply and the third branch, and controlled by the output voltage; and A tenth switch tube is connected between the fourth branch and the eighth switch tube and is controlled by the second voltage. A connection node between the tenth switch tube and the eighth switch tube provides the output voltage.

8. The circuit according to claim 6, wherein: The level conversion circuit also includes: a ninth switch tube, connected between the third branch and the seventh switch tube, and controlled by the output voltage; and A tenth switch tube is connected between the fourth branch and the eighth switch tube and is controlled by the second voltage. A connection node between the tenth switch tube and the eighth switch tube provides the output voltage.

9. The circuit according to claim 6, wherein: The level conversion circuit further includes: a ninth switch tube connected between the third branch and the seventh switch tube and controlled by the output voltage.

10. The circuit according to any one of claims 7 to 9, wherein: When the output voltage is at a high level, the ninth switch tube is turned off.

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