Dynamic element matching circuit for high-speed multi-bit Sigma-Delta modulator

Abstract

The invention discloses a dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator, and relates to an analog integrated circuit, the dynamic element matching circuit comprises a loop filter, a Flash ADC (Analog to Digital Converter) and a DAC (Digital to Analog Converter), the loop filter is connected with a comparator array of the Flash ADC, and the DAC is used as a feedback loop to be connected to the output end of the Flash ADC and is connected with the input end of the loop filter by subtracting an input signal of the modulator; a DEM module is embedded in the reference generation circuit of the Flash ADC, the DEM module is located at the front end of the reference generation circuit of the Flash ADC, and the access sequence of resistors is rotated by controlling a switch resistor ring circuit arranged between the DEM module and a comparator array so as to disrupt at the reference voltage generation position, so that thermometer codes are scrambled. According to the invention, the regeneration time of the comparator in the Flash ADC is not compressed, the loop delay is not increased, the improvement of the system stability is facilitated, and the method is more suitable for the design of a high-speed Sigma-Delta modulator.

Description

Technical Field

[0001] The present invention relates to analog integrated circuits, and more particularly, to a dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator. Background Art

[0002] Sigma-Delta modulators generally use multi-bit quantization to achieve higher precision, and multi-bit quantization requires a multi-bit DAC. In a multi-bit continuous-time Sigma-Delta modulator structure, due to process variations during manufacturing, there will be mismatches between DAC units. When there are mismatches in the DAC, the output signal of the modulator will have significant harmonic distortion, and the harmonics will not be suppressed by the noise transfer function of the modulator system, thus directly affecting the dynamic performance of the modulator. Therefore, in order to suppress the large harmonics introduced by DAC mismatches, dynamic element matching is required to correct the mismatches.

[0003] A common method for correcting DAC mismatches is to add dynamic element matching (DEM) between a Flash ADC (Flash analog-to-digital converter) and the DAC, as Figure 1 shown. The reference voltage of the Flash ADC is generated by resistor chain voltage division, and the dynamic element matching method is to scramble the thermometer code to randomly select the multi-bit DAC connected to the Flash ADC. Representative literature in this regard includes [1][2][3][4].

[0004] However, this correction method has certain limitations. Since the correction module exists in the feedback path before the DAC, it will increase the loop delay, thereby increasing the risk of oscillation in the modulator system. Theoretically speaking, the sampling clock rate of a continuous-time Sigma-Delta modulator is jointly determined by the operating speed of its quantizer and the signal settling time of the DAC. The addition of the correction module will compress the regeneration time of the comparator, which is not conducive to the design of high-speed Sigma-Delta modulators.

[0005] References:

[0006] [1] Li Linyang. Design of a Low-Power Continuous-Time Quadrature Bandpass Delta-Sigma ADC for Bluetooth [D]. Xidian University, 2021. DOI: 10.27389 / d.cnki.gxadu.2021.000369.

[0007] [2]T. Wang, Y. Lin and C. Liu. A 0.022mm2 98.5dB SNDR Hybrid Audio Modulator With Digital ELD Compensation in 28nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2015, 50(11):2655-2664.

[0008] [3] Wang Menghao. Research and Design of Continuous-Time Sigma-Delta Modulators[D]. China Academy of Launch Vehicle Technology, 2020. DOI:10.27096 / d.cnki.ghtdy.2020.000023.

[0009] [4] L. Sharifi and O. Hashemipour. Multi-bit Quantizer Delta-Sigma Modulator with the Feedback DAC Mismatch Error Shaping[C]. 2019 27th Iranian Conference on Electrical Engineering(ICEE), 2019:209-213. SUMMARY OF THE INVENTION

[0010] The technical problem to be solved by the present invention is to provide a dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator, which does not increase the loop delay and is beneficial to improving the system stability in view of the deficiencies of the prior art.

[0011] A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to the present invention includes a loop filter, a Flash ADC, and a DAC. The loop filter is connected to the comparator array of the Flash ADC. The DAC is connected as a feedback loop to the output end of the Flash ADC and is subtracted from the modulator input signal and then connected to the input end of the loop filter. The reference generation circuit of the Flash ADC is embedded with a DEM module, and the DEM module is located at the front end of the reference generation circuit of the Flash ADC. By controlling and setting the switching resistor loop circuit between it and the comparator array, the access order of the resistors is rotated to scramble at the reference voltage generation, so as to scramble the thermometer code.

[0012] Preferably, the reference generation circuit of the Flash ADC includes a resistor chain having a voltage V1 output terminal and a voltage V2 output terminal, a first operational amplifier U1, a second operational amplifier U2, a random number generator, a first switching transistor M1, a second switching transistor M2, and a switched resistor ring circuit; the voltage V1 output terminal is connected to the inverting input terminal of the first operational amplifier U1, the non-inverting input terminal of the first operational amplifier U1 is connected to the Vin<(K-1):0> terminal of the switched resistor ring circuit through a first K-bit switch group, the voltage V2 output terminal is connected to the inverting input terminal of the second operational amplifier U2, the non-inverting input terminal of the second operational amplifier U2 is connected to the Vin<(K-1):0> terminal of the switched resistor ring circuit through a second K-bit switch group, and the input terminal of the random number generator is connected to four K-bit switch groups at the same time; the output terminal of the first operational amplifier U1 is connected to the gate of the first switching transistor M1, the source of the first switching transistor M1 is connected to the power supply terminal, and the drain of the first switching transistor M1 is connected to the VREFP terminal of the switched resistor ring circuit; the output terminal of the second operational amplifier U2 is connected to the gate of the second switching transistor M2, the source of the second switching transistor M2 is connected to the reference ground terminal, and the drain of the second switching transistor M2 is connected to the VREFN terminal of the switched resistor ring circuit; the switched resistor ring circuit is provided with a VO<(N-1):0> terminal, which is connected to the comparator array; where N is a natural number.

[0013] Preferably, the switched resistor ring circuit is composed of a third K-bit switch group, a fourth K-bit switch group, and a resistor ring.

[0014] Preferably, the resistor ring includes N resistor groups, and a connection resistor is provided between every two adjacent resistor groups. All the resistor groups are connected in series through the connection resistor to form a resistor ring; both ends of each resistor group are respectively connected to one end of two switches in the third K-bit switch group and the fourth K-bit switch group, the other ends of the switches in the third K-bit switch group are connected to the VREFP terminal, and the other ends of the switches in the fourth K-bit switch group are connected to the VREFN terminal.

[0015] Preferably, the arrangement orders of the third K-bit switch group and the fourth K-bit switch group are opposite.

[0016] Preferably, the resistor group is composed of two resistors R connected in series, and the resistance value of the connection resistor is the sum of the two resistors in the resistor group.

[0017] Preferably, the resistor chain includes a first resistor R1, a second resistor R2, and a third resistor R3; the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series in sequence. One end of the first resistor R1 is connected to the power supply terminal, one end of the third resistor R3 is connected to the reference ground terminal, a voltage V1 is output at the connection between the first resistor R1 and the second resistor R2, and a voltage V2 is output at the connection between the second resistor R2 and the third resistor R3.

[0018] Preferably, N = 2 n , where n is the number of bit quantization in the Sigma-Delta modulator.

[0019] Preferably, the random number generator is a small-step random number pointer generator.

[0020] Preferably, the execution steps of the small-step random number pointer generator are as follows:

[0021] Step 1: Obtain the value represented by the current pointer position;

[0022] Step 2: Generate a random number from -1 to 3;

[0023] Step 3: Add the value and the random number, then perform a modulo operation on the sum with 32, and use the remainder as the pointer position for the new cycle;

[0024] Step 4: If the end instruction has not been reached, use the pointer position of the new cycle as the current pointer position and re-execute Step 1.

[0025] Beneficial effects

[0026] The advantages of the present invention are as follows:

[0027] 1. Move the dynamic element matching of the multi-bit Sigma-Delta modulator forward to the resistors of the Flash ADC. Rotate the resistors through the switched resistor loop circuit to scramble the resistors at the source, thereby scrambling the reference voltage, and finally realizing the scrambling of the thermometer code. This method not only does not introduce loop delay, which is beneficial to the stability of the system, but also does not compress the regeneration time of the comparators in the Flash ADC.

[0028] 2. The present invention proposes a small-step random number pointer generator, which makes the switched resistor loop conduct similar switches in adjacent clock cycles. In this way, the step size of the resistor rotation is small, so that the reference voltage at each output node changes by a small number of steps, and a smaller settling time is required, which is more suitable for application in high-speed Sigma-Delta modulators. Description of the drawings

[0029] Figure 1Schematic diagram of the result of the dynamic element matching circuit for a traditional Sigma-Delta modulator;

[0030] Figure 2 Reference voltage generation circuit for a traditional Flash ADC;

[0031] Figure 3 Schematic diagram of the structure of the dynamic element matching circuit for the high-speed multi-bit Sigma-Delta modulator of the present invention;

[0032] Figure 4 Schematic diagram of the structure of the Flash ADC embedded with DEM of the present invention;

[0033] Figure 5 Schematic diagram of the structure of the switched resistor ring circuit of the present invention;

[0034] Figure 6 Simplified diagram of the switched resistor ring circuit when switch S<0> and switch SN<0> of the present invention are closed;

[0035] Figure 7 Schematic diagram of the comparison of the establishment time of the reference voltage rotation generated by the Flash ADC of the present invention;

[0036] Figure 8 Schematic diagram of the execution flow of the small-step random number pointer generator of the present invention;

[0037] Figure 9 Based on Figure 4 Circuit reference voltage simulation waveform diagram. Detailed implementation manners

[0038] The present invention will be further described below in conjunction with embodiments, but it does not constitute any limitation to the present invention. Any person's limited modifications within the scope of the claims of the present invention are still within the scope of the claims of the present invention.

[0039] Refer to Figure 2, a dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to the present invention includes a loop filter, a Flash ADC, and a DAC. After the input signal Vin and the feedback signal are subtracted, they pass through the loop filter and are then quantized by the Flash ADC to output the digital code Dout. The DAC is connected as a feedback loop to the output end of the Flash ADC and is subtracted from the modulator input signal and connected to the input end of the loop filter; the reference generation circuit of the Flash ADC is embedded with a DEM module, and the DEM module is located at the front end of the reference generation circuit of the Flash ADC. By controlling and setting the switched resistor loop circuit between it and the comparator array, the access order of the resistors is rotated to scramble at the reference voltage generation, so as to scramble the thermometer code. That is, the present invention moves the DEM from the feedback path to the front end of the reference generation circuit of the Flash ADC, and at the same time proposes to rotate the resistors of the switched resistor loop circuit to achieve scrambling at the source, which will not compress the regeneration time of the comparators in the Flash ADC and will not increase the loop delay, which is beneficial to the improvement of system stability.

[0040] In this embodiment, the reference generation circuit of the Flash ADC includes a resistor chain with a voltage V1 output terminal and a voltage V2 output terminal, a first operational amplifier U1, a second operational amplifier U2, a random number generator, a first switching transistor M1, a second switching transistor M2, and a switched resistor loop circuit. Among them, the resistor chain includes a first resistor R1, a second resistor R2, and a third resistor R3; the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series in sequence. One end of the first resistor R1 is connected to the power supply terminal, one end of the third resistor R3 is connected to the reference ground terminal, and the voltage V1 is output at the connection between the first resistor R1 and the second resistor R2, and the voltage V2 is output at the connection between the second resistor R2 and the third resistor R3. The reference voltage of the traditional Flash ADC is generated by voltage division of the resistor chain. Taking four-bit quantization as an example, that is, n = 4, as Figure 3 shown, the connection positions of the voltage VREFP and the voltage VREFN are fixed, and the resistor chain divides 2 4 = 16 reference voltages in the middle of the voltage VREFP and the voltage VREFN. In the resistor loop, in order to rotate the access nodes of VREFP and VREFN, switches need to be provided at both ends of each resistor group, that is, the number of switches in each switch group is 2N, which is K = 32.

[0041] The reference generation circuit of the Flash ADC with the embedded DEM technology proposed by the present invention is as Figure 4As shown, the output terminal of voltage V1 is connected to the inverting input terminal of the first operational amplifier U1. The non-inverting input terminal of the first operational amplifier U1 is connected to the Vin<31:0> terminal of the switched resistor ring circuit through the first 32-bit switch group. The output terminal of voltage V2 is connected to the inverting input terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the Vin<31:0> terminal of the switched resistor ring circuit through the second 32-bit switch group. The input terminal of the random number generator is connected to the four 32-bit switch groups simultaneously. The output terminal of the first operational amplifier U1 is connected to the gate of the first switching transistor M1. The source of the first switching transistor M1 is connected to the power supply terminal. The drain of the first switching transistor M1 is connected to the VREFP terminal of the switched resistor ring circuit. The output terminal of the second operational amplifier U2 is connected to the gate of the second switching transistor M2. The source of the second switching transistor M2 is connected to the reference ground terminal. The drain of the second switching transistor M2 is connected to the VREFN terminal of the switched resistor ring circuit. The switched resistor ring circuit is provided with a VO<15:0> terminal, which is connected to the comparator array.

[0042] In this Flash ADC structure, first, two voltages V1 and V2 are generated through a resistor chain. The two operational amplifiers play a clamping role, clamping the voltage at the VREFP terminal to V1 and the voltage at the VREFN terminal to V2. The random number generator controls the pointers of 32 switches, only conducting a pair of switches each time, and the position of the pointers changes in each clock cycle, thus rotating the resistor access sequence of the resistor ring. In this way, a scrambled reference voltage is generated, and then the randomized thermometer code is output by the subsequent comparator, thereby achieving the effect of dynamic element matching.

[0043] As Figure 5 shown is the circuit structure of the switched resistor ring circuit, which corresponds to Figure 4 the part in the dashed box in. The switched resistor ring circuit is composed of a third 32-bit switch group, a fourth 32-bit switch group, and a resistor ring. Specifically, the resistor ring includes 16 resistor groups, and a connection resistor is provided between every two adjacent resistor groups. All the resistor groups are connected in series through the connection resistors to form a resistor ring. The two ends of each resistor group are respectively connected to one end of two switches in the third 32-bit switch group and the fourth 32-bit switch group. The other ends of the switches in the third 32-bit switch group are connected to the VREFP terminal, and the other ends of the switches in the fourth 32-bit switch group are connected to the VREFN terminal. The arrangement orders of the third 32-bit switch group and the fourth 32-bit switch group are opposite. The resistor group is composed of two resistors R connected in series, and the resistance value of the connection resistor is the sum of the two resistors in the resistor group.

[0044] The voltages VREFP and VREFN are the maximum and minimum input reference voltages respectively. They are connected to the node Vin<31:0> of the resistor loop through switches. The input nodes are separated by 2R. The output reference voltage is generated by resistor voltage division for the comparator, and the outputs VO<15:0> are separated by 4R. The switches are controlled by a random number generator, and only one pair of switches conducts each time.

[0045] Take Figure 5 the closing of switch SN<0> in the third 32-bit switch group and switch S<0> in the fourth 32-bit switch group as an example. There will be two resistor paths from the VREFP terminal to the VREFN terminal, as shown in Figure 6 . One will first pass through R and generate an output reference voltage VO<15>; the other will first pass through 2R + R = 3R and then generate an output reference voltage VO<0>. There are a total of 16 reference voltage outputs in the two resistor paths. Different conducting switches will cause the access order of the resistors to rotate accordingly, and the reference voltages corresponding to each output node will be different, thus achieving the effect of DEM.

[0046] Considering that a certain setup time is required for the rotation of the reference voltages after the resistor rotation, taking the node VO<15> as an example, as Figure 7 shown, if the number of steps the reference voltage spans is large, the setup time during the rotation process will be longer, such as t2; if the number of steps is small, the setup time will be short, such as t1. The shorter the setup time, the more suitable it is for application in high-speed sigma-delta modulators. For Figure 5 the switched resistor loop, the conduction of adjacent switches will cause the output node voltage to span fewer steps. Therefore, the present invention proposes a small-step random number pointer generator to update the position of the pointer in each clock cycle to control the switches in the switched resistor loop, which is more suitable for the design of high-speed Sigma-Delta modulators, and its execution flow is as Figure 8 .

[0047] The execution steps of the small-step random number pointer generator are as follows:

[0048] Step 1: Obtain the value represented by the current pointer position;

[0049] Step 2: Generate a random number from -1 to 3;

[0050] Step 3: Add the value and the random number, then take the remainder of the sum with respect to 32, and use the remainder as the pointer position for the new cycle;

[0051] Step 4: If the end instruction has not been reached, use the pointer position of the new cycle as the current pointer position and re-execute Step 1.

[0052] Figure 9It is the reference voltage simulation of the Flash ADC with the embedded DEM technology. It can be seen that the output reference voltage rotates in each clock cycle, and the step span of the 16 reference voltages never exceeds 3.

[0053] The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which will not affect the implementation effect of the present invention and the practicability of the patent.

Claims

1. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator, comprising a loop filter, a Flash ADC and a DAC, characterized in that: The loop filter is connected to the comparator array of the Flash ADC, and the DAC is connected to the output end of the Flash ADC as a feedback loop and is subtracted from the modulator input signal and connected to the input end of the loop filter; the reference generation circuit of the Flash ADC is embedded with a DEM module, and the DEM module is located at the front end of the reference generation circuit of the Flash ADC, and the connection order of the resistors is rotated by controlling a switch resistor loop circuit arranged between the DEM module and the comparator array to disrupt the reference voltage generation location, thereby scrambling the thermometer code.

2. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 1, characterized in that: The reference generation circuit of the Flash ADC includes a resistor chain having a voltage V1 output terminal and a voltage V2 output terminal, a first operational amplifier U1, a second operational amplifier U2, a random number generator, a first switch tube M1, a second switch tube M2 and a switch resistor loop circuit; the voltage V1 output terminal is connected to the inverting input terminal of the first operational amplifier U1, the positive input terminal of the first operational amplifier U1 is connected to the Vin<(K-1):0> terminal of the switch resistor loop circuit through a first K-bit switch group, the voltage V2 output terminal is connected to the inverting input terminal of the second operational amplifier U2, the positive input terminal of the second operational amplifier U2 is connected to the Vin<(K-1):0> terminal of the switch resistor loop circuit through a second K-bit switch group, -1):0> terminal is connected, and the input terminal of the random number generator is simultaneously connected to four K-bit switch groups; the output terminal of the first operational amplifier U1 is connected to the gate of the first switch tube M1, the source of the first switch tube M1 is connected to the power supply terminal, and the drain of the first switch tube M1 is connected to the VREFP terminal of the switch resistance ring circuit; the output terminal of the second operational amplifier U2 is connected to the gate of the second switch tube M2, the source of the second switch tube M2 is connected to the reference ground terminal, and the drain of the second switch tube M2 is connected to the VREFN terminal of the switch resistance ring circuit; the switch resistance ring circuit is provided with a VO<(N-1):0> terminal connected to the comparator array; wherein N and K are both natural numbers.

3. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 2, characterized in that: The switch resistance ring circuit is composed of a third K-position switch group, a fourth K-position switch group and a resistance ring.

4. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 3, characterized in that: The resistance ring includes N resistance groups, a connecting resistor is provided between each two adjacent resistance groups, and all the resistance groups are connected in series through the connecting resistor to form a resistance ring; the two ends of each resistance group are respectively connected to one end of two switches in the third K-bit switch group and the fourth K-bit switch group, the other end of the switch in the third K-bit switch group is connected to the VREFP end, and the other end of the switch in the fourth K-bit switch group is connected to the VREFN end.

5. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 4, characterized in that: The arrangement order of the third K-position switch group and the fourth K-position switch group is opposite.

6. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 4, characterized in that: The resistor group is composed of two resistors R connected in series, and the resistance value of the connection resistor is the sum of the two resistors in the resistor group.

7. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 2, characterized in that: The resistor chain includes a first resistor R1, a second resistor R2 and a third resistor R3; the first resistor R1, the second resistor R2 and the third resistor R3 are connected in series once, one end of the first resistor R1 is connected to the power supply end, one end of the third resistor R3 is connected to the reference ground end, the connection between the first resistor R1 and the second resistor R2 outputs a voltage V1, and the connection between the second resistor R2 and the third resistor R3 outputs a voltage V2.

8. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 2, characterized in that: N=2 n , where n is the number of bit quantization in the Sigma-Delta modulator.

9. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 2, characterized in that: The random number generator is a small-step random number pointer generator.

10. A dynamic element matching circuit for a high-speed multi-bit Sigma-Delta modulator according to claim 9, characterized in that: The execution steps of the small-step random number pointer generator are as follows: Step 1: Get the value represented by the current pointer position; Step 2: Generate a random number between 1 and 3; Step 3, after adding the numerical value and the random number, perform a modulo operation on the addition result with respect to 32, and use the remainder as the pointer position of the new cycle; Step 4: If the end instruction has not arrived, re-execute step 1 using the pointer position of the new cycle as the current pointer position.

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