On-chip pseudo resistor calibration circuit based on delta-sigma modulator

Abstract

The invention relates to an on-chip pseudo resistor calibration circuit based on a delta-sigma modulator, which realizes on-chip continuous adjustable large resistance from G ohm to T ohm magnitude based on the characteristics of simple realization mode, relatively accurate resistance value of a switch capacitor resistor and relatively large resistance value of a pseudo resistor of the delta-sigma modulator technology. Based on the characteristics of large loop gain, high precision and small hardware overhead of the delta-sigma modulator, the resistance value of the pseudo resistor is accurately calibrated to the resistance value of the switched capacitor resistor, and the resistance value is amplified. Compared with a traditional pseudo resistor, the circuit achieves the precise and controllable resistance value, and improves the robustness, the temperature characteristic and the linearity of the resistor. Compared with a switched capacitor resistor, the circuit realizes a resistance value above T ohm magnitude; compared with the existing pseudo resistance calibration circuit technology, the circuit can realize a wider resistance adjustment range and less hardware and power consumption overhead.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and particularly to an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator. Background Art

[0002] Large resistors in the G ohm range have important applications in many fields. In weak current detection, a transimpedance amplifier requires a resistor in the range of G ohms to T ohms to amplify the input pA-level current to an appropriate voltage range for subsequent analog-to-digital converter design; in the design of a current digital-to-analog converter, a low-pass filter composed of resistors in the G ohm range is used in the bias circuit to effectively filter out the thermal noise generated by the bias circuit; in a capacitive coupling amplifier, a resistor in the T ohm range is required to bias the amplifier, and the resistance value of this resistor also determines the high-pass corner frequency of the amplifier; in some low-frequency integrator applications that require a few Hz or even a few hundred mHz, resistors in the G ohm to T ohm range can greatly reduce the use of on-chip capacitors. If an off-chip large resistor in the G ohm range is used for design, the leakage of ESD in the IO will cause the equivalent resistance value to decrease, and using a specific IO design will also increase the design difficulty of the overall circuit. Integrating a large resistor in the G ohm range directly on the chip can effectively avoid this problem.

[0003] Currently, the commonly used on-chip methods for implementing resistors in the G ohm to T ohm range are divided into three types, namely: 1) pseudo-resistors, 2) switched-capacitor resistors, and 3) duty-cycle resistors. The advantage of pseudo-resistors is that they have a small area, a compact layout, a simple implementation method, and can achieve a large resistance value. The disadvantages are that the resistance value fluctuates greatly with process and temperature changes, the resistance linearity is poor, and the resistance value is difficult to adjust. A switched-capacitor resistor consists of a sampling capacitor and a sampling switch. Its advantage is that the resistance value can be accurately adjusted by the clock frequency, and the temperature and voltage coefficients of the capacitor are small, so that the resistance value fluctuates little with process and temperature changes. The disadvantage is that it is easily affected by parasitic capacitance, and the maximum resistance value that can be achieved is often less than 100 G ohms. A duty-cycle resistor can achieve precise control of the resistance value by adjusting the conduction time of the resistor. The advantage is that the resistance linearity is good, and the disadvantage is that the maximum resistance value that can be achieved is limited (<100 G ohms), and the change of process temperature will affect the duty cycle.

[0004] Existing on-chip large resistors are difficult to achieve a controllable T ohm range resistor, and have problems of poor temperature characteristics and poor consistency. Summary of the Invention

[0005] Based on this, it is necessary to provide an on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator for the above technical problems. This circuit improves the technology for implementing a T ohm range resistor on the chip, realizes an adjustable large resistor in the G ohm to T ohm range, and greatly reduces the resistance value fluctuation caused by process and temperature changes.

[0006] An on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator, the on-chip pseudo-resistor calibration circuit comprising: A direction comparator for determining a conversion control signal according to the magnitude relationship between an input voltage and a common-mode voltage.

[0007] A conversion switch for outputting a first voltage and a second voltage according to the input voltage, the common-mode voltage, and the conversion control signal, and respectively transmitting them to the reference input terminal and the calibration input terminal of a pseudo-resistor calibration module based on a ΔΣ modulator.

[0008] A pseudo-resistor calibration module based on a ΔΣ modulator for converting the first voltage into a reference current using a switched-capacitor reference resistor, converting the second voltage into a calibration current using a calibration pseudo-resistor, integrating, quantifying, performing digital-to-analog conversion, and low-pass filtering the difference between the reference current and the calibration current to obtain a filtered voltage, feeding back the filtered voltage to the calibration pseudo-resistor, and transmitting the filtered voltage to a control voltage copying circuit.

[0009] A control voltage copying circuit for copying the difference between the filtered voltage and the common-mode voltage to a copying pseudo-resistor.

[0010] A copying pseudo-resistor for adjusting its resistance value according to the copied voltage, the common-mode voltage, and the input voltage, and calibrating its resistance value to several times the resistance value of the switched-capacitor reference resistor.

[0011] In one embodiment, the pseudo-resistor calibration module based on a ΔΣ modulator comprises: a switched-capacitor reference resistor, a calibration pseudo-resistor, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter.

[0012] A switched-capacitor reference resistor for converting the first voltage into a reference current using a series-connected switched-capacitor unit, and transmitting the reference current to the integrator.

[0013] A calibration pseudo-resistor for converting the second voltage into a calibration current using a parallel-connected calibration pseudo-resistor unit, and transmitting the calibration current to the integrator.

[0014] An integrator for integrating the difference between the reference current and the calibration current to obtain an analog voltage.

[0015] A quantizer for comparing the magnitude of the analog voltage and the common-mode voltage, converting the comparison result into a digital code, and obtaining a digital output voltage.

[0016] A digital-to-analog conversion module for converting the digital output voltage into an analog output voltage.

[0017] A low-pass filter for performing low-pass filtering on the analog output voltage to obtain a filtered voltage.

[0018] In one embodiment, the switched-capacitor reference resistor includes M series-connected switched-capacitor resistors, and the resistance value of the switched-capacitor resistor is adjusted by the clock frequency. The resistance value of the switched-capacitor reference resistor is:

[0019] Wherein, is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of series-connected switched-capacitor units.

[0020] In one embodiment, the calibration pseudo-resistor is composed of N calibration pseudo-resistor units connected in parallel.

[0021] The calibration pseudo-resistor unit includes two series-connected P-type transistors; the drains of the two P-type transistors are connected, the sources of the two P-type transistors are respectively configured as the input and output of the calibration pseudo-resistor unit, and the gates of the two transistors are connected and connected to the output terminal of the low-pass filter; the body terminals of the two P-type transistors are connected to the drains or respectively connected to their respective sources; the aspect ratios and layout connection methods of the P-type transistors in the N calibration pseudo-resistor units are exactly the same.

[0022] The resistance value of the calibration pseudo-resistor unit is:

[0023] Wherein, is the resistance value of the calibration pseudo-resistor unit; is the resistance value of the switched-capacitor reference resistor is the clock frequency, is the sampling capacitor, M is the number of series-connected switched-capacitor units, and N is the number of parallel-connected calibration pseudo-resistor units.

[0024] In one embodiment, the integrator is a passive or active integrator.

[0025] In one embodiment, the quantizer uses a dynamic comparator or a static comparator to compare the analog voltage and the common-mode voltage.

[0026] In one embodiment, the conversion switch is further configured to, if the input voltage is greater than the common-mode voltage, the first voltage is the input voltage, and the second voltage is the difference between twice the common-mode voltage and the input voltage.

[0027] If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage.

[0028] If the input voltage is equal to the common-mode voltage, both the first voltage and the second voltage are the common-mode voltage.

[0029] Transmit the first voltage to the reference input terminal of the pseudo-resistor calibration module based on the ΔΣ modulator, and transmit the second voltage to the calibration input terminal of the pseudo-resistor calibration module based on the ΔΣ modulator.

[0030] In one embodiment, the replicated pseudo-resistor includes: a floating voltage source and a replicated pseudo-resistor unit composed of two P-type transistors; the resistance value of the replicated pseudo-resistor is controlled by the floating voltage source.

[0031] The floating voltage source includes a unity-gain amplifier and a bootstrap capacitor; The output of the unity-gain amplifier drives the lower plate of the bootstrap capacitor. The input terminal of the unity-gain amplifier is the input terminal of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output terminal of the floating voltage source.

[0032] The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistors in the replicated pseudo-resistor unit.

[0033] In one embodiment, the aspect ratio and connection method of the P-type transistors in the replicated pseudo-resistor unit are the same as those of the calibration pseudo-resistor unit in the calibration pseudo-resistor.

[0034] In one embodiment, the control voltage replication circuit includes: a sampling capacitor and a sampling switch.

[0035] At the sampling moment, sample the voltage difference between the filtered voltage and the common-mode voltage (VCM), and store the voltage difference on the sampling resistor.

[0036] At the transmission moment, transmit the voltage difference on the sampling resistor to the replicated pseudo-resistor through the sampling switch.

[0037] The above-mentioned on-chip pseudo-resistor calibration circuit based on the ΔΣ modulator realizes a continuously adjustable large resistor in the range of G ohms to T ohms on the chip based on the simple implementation method of the ΔΣ modulator technology, the relatively accurate resistance value of the switched-capacitor resistor, and the large resistance value of the pseudo-resistor. Based on the characteristics of the large loop gain, high accuracy, and small hardware overhead of the ΔΣ modulator, the resistance value of the pseudo-resistor is accurately calibrated to the resistance value of the switched-capacitor resistor and amplified. Compared with traditional pseudo-resistors, this circuit realizes accurate controllability of the resistance value, improves the robustness, temperature characteristics, and linearity of the resistor; compared with switched-capacitor resistors, this circuit realizes resistance values above the T ohm level; compared with the existing pseudo-resistor calibration circuit technologies, this circuit can achieve a wider resistance adjustment range, less hardware and power consumption overhead. Description of the Drawings

[0038] Figure 1 It is a block diagram of the on-chip pseudo-resistor calibration circuit based on the ΔΣ modulator in one embodiment; Figure 2 Schematic diagram of a reference pseudo-resistance calibration loop implemented based on ΔΣ modulator technology in another embodiment; Figure 3 Schematic diagram of a replicated pseudo-resistance in another embodiment; Figure 4 Schematic diagram of a direction comparator and a switch in another embodiment; Figure 5 Graph of the measured resistance value versus the clock frequency in another embodiment; Figure 6 Graph of the measured resistance value versus the temperature in another embodiment, where (a) is the graph of the measured resistance value versus the temperature under the first resistance value configuration, (b) is the graph of the measured resistance value versus the temperature under the second resistance value configuration, (c) is the graph of the measured resistance value versus the temperature under the third resistance value configuration, and (d) is the graph of the measured resistance value versus the temperature under the fourth resistance value configuration; Figure 7 Graph of the multi-chip test results in another embodiment, where (a) is the first multi-chip test result graph, (b) is the second multi-chip test result graph, (c) is the third multi-chip test result graph, and (d) is the fourth multi-chip test result graph; Figure 8 Graph of the measured amplitude versus the total harmonic distortion in another embodiment. Detailed implementation manners

[0039] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] In one embodiment, as Figure 1 shown, a on-chip pseudo-resistance calibration circuit based on a ΔΣ modulator is provided. The on-chip pseudo-resistance calibration circuit includes: a direction comparator 10, a switch 20, a pseudo-resistance calibration module 30 based on a ΔΣ modulator, a control voltage replication circuit 40, and a replicated pseudo-resistance 50.

[0041] The direction comparator 10 is configured to determine a conversion control signal according to the magnitude relationship between an input voltage and a common-mode voltage.

[0042] Specifically, the input signal of the direction comparator 10 is an input voltage (VIN). By comparing the magnitude relationship between the input voltage and the common-mode voltage, a corresponding control signal (DIR) is input.

[0043] The direction comparator 10 controls the switching switch according to the magnitude relationship between the input voltage and the common-mode voltage, and outputs a corresponding control signal (DIR) to the switched-capacitor reference resistor and the calibration pseudo-resistor of the pseudo-resistor calibration module based on the ΔΣ modulator.

[0044] The switching switch 20 is configured to output a first voltage and a second voltage according to the input voltage, the common-mode voltage, and the conversion control signal, and transmit them to the reference input terminal and the calibration input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator, respectively.

[0045] Specifically, the input signals of the switching switch 20 are the input voltage VIN and the output of the direction comparator (DIR), and the output first voltage VA and second voltage VB are determined by the DIR signal.

[0046] The pseudo-resistor calibration module 30 based on the ΔΣ modulator is configured to convert the first voltage into a reference current by using the switched-capacitor reference resistor, convert the second voltage into a calibration current by using the calibration pseudo-resistor, integrate, quantize, perform digital-to-analog conversion, and low-pass filter the difference between the reference current and the calibration current to obtain a filtered voltage, feedback the filtered voltage to the calibration pseudo-resistor, and transmit the filtered voltage to the control voltage copying circuit 40.

[0047] The switched-capacitor reference resistor will be driven by a clock, and its resistance value can be controlled by the clock frequency. Charge is injected into the integrator through the switched-capacitor reference resistor; the quantizer quantizes the output result of the integrator and drives the digital-to-analog converter; the low-pass filter filters the output of the digital-to-analog converter, and inputs the filtered voltage to the gate of the calibration pseudo-resistor composed of P-type transistors to control the on-resistance of the P-type transistors. The charge on the integrator can flow out through the calibration pseudo-resistor; the difference between the output voltage of the integrator and the common-mode voltage is copied to the copy pseudo-resistor composed of P-type transistors through the control voltage copying circuit to regulate the resistance value of the copy pseudo-resistor.

[0048] The control voltage copying circuit 40 is configured to copy the difference between the filtered voltage and the common-mode voltage to the copy pseudo-resistor 50.

[0049] The copy pseudo-resistor 50 is configured to regulate its resistance value according to the copied voltage, the common-mode voltage, and the input voltage, and calibrate its resistance value to several times the resistance value of the switched-capacitor reference resistor.

[0050] In the above-mentioned on-chip pseudo-resistor calibration circuit based on a ΔΣ modulator, the circuit is based on the ΔΣ modulator technology, which has the advantages of simple implementation, relatively accurate resistance values of switched-capacitor resistors, and large pseudo-resistance values. It realizes a continuously adjustable large resistor with an on-chip resistance ranging from G ohms to T ohms. Based on the characteristics of large loop gain, high precision, and small hardware overhead of the ΔΣ modulator, the pseudo-resistance value is accurately calibrated to the switched-capacitor resistor value, and its value is amplified. Compared with traditional pseudo-resistors, this circuit realizes accurate controllability of the resistance value, improving the robustness, temperature characteristics, and linearity of the resistor. Compared with switched-capacitor resistors, this circuit realizes resistance values above the T ohm level. Compared with the existing pseudo-resistor calibration circuit technologies, this circuit can achieve a wider resistance adjustment range, less hardware, and lower power consumption.

[0051] In one embodiment, the pseudo-resistor calibration module 30 based on a ΔΣ modulator includes: a switched-capacitor reference resistor, a calibration pseudo-resistor, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter.

[0052] The switched-capacitor reference resistor is used to convert the first voltage into a reference current by using a series-connected switched-capacitor unit and transmit the reference current to the integrator.

[0053] The calibration pseudo-resistor is used to convert the second voltage into a calibration current by using a parallel-connected calibration pseudo-resistor unit and transmit the calibration circuit to the integrator.

[0054] The integrator is used to integrate the difference between the reference current and the calibration current to obtain an analog voltage.

[0055] Specifically, the input of the integrator is connected to the voltage VX, and the output of the integrator is connected to the quantizer. The input currents of the integrator are I IN and I OUT , the integration capacitor in the integrator is C INT , and the output result V(t) of the integrator is the sum of the integration result of the difference between I IN and I OUT on the capacitor at a given time and the previous integration result V(t - T CLK ). It can be expressed by the following formula:

[0056] where is the derivative of the adopted frequency.

[0057] The quantizer is used to compare the magnitudes of the analog voltage and the common-mode voltage, convert the comparison result into a digital code, and obtain a digital output voltage.

[0058] Specifically, the input signal of the quantizer is the output analog voltage of the integrator. By comparing its magnitude with the common-mode voltage, the comparison result is converted into a digital code for output. The comparator circuit inside the quantizer can use a dynamic comparator or a static comparator.

[0059] A digital-to-analog conversion module for converting the digital output voltage into an analog output voltage.

[0060] Specifically, the input signal of the digital-to-analog conversion module is the output digital code of the quantizer, and the output signal is the corresponding analog voltage.

[0061] A low-pass filter for performing low-pass filtering on the analog output voltage to obtain a filtered voltage.

[0062] Specifically, the input signal of the low-pass filter is the output analog voltage of the digital-to-analog converter, and the output signal is the filtered voltage.

[0063] In one embodiment, the switched-capacitor reference resistor includes: M series-connected switched-capacitor resistors. The resistance value of the switched-capacitor resistor is adjusted by the clock frequency. The resistance value of the switched-capacitor reference resistor is:

[0064] Wherein, is the resistance value of the switched-capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of series-connected switched-capacitor units.

[0065] Specifically, the switched-capacitor reference resistor (R REF ) composed of M switched-capacitor resistors. The resistance value of R REF can be adjusted by the clock frequency, and the resistance value is jointly determined by the clock frequency, the sampling capacitor ( ) and the number of series-connected switched-capacitors (M).

[0066] The sampling capacitor ( ) can be composed of a fixed-capacitance capacitor or a tunable-capacitance capacitor. The number of series-connected switched-capacitors (M) can be configured by a digital code, and the values of and M can be configured according to the usage scenario.

[0067] As Figure 1 shown, one end of the switched-capacitor reference resistor is connected to voltage VA, and the other end is connected to voltage VX. The current flowing through the resistor is the input current (I IN ), and the current direction is from VA to VX.

[0068] In one embodiment, the calibration pseudo-resistor is composed of N calibration pseudo-resistor units ( are connected in parallel; the calibration pseudo-resistance unit includes two P-type transistors connected in series; the drains of the two P-type transistors are connected, the sources of the two P-type transistors are respectively configured as the input and output of the calibration pseudo-resistance unit, and the gates of the two transistors are connected and connected to the output of the low-pass filter; the body terminals (the body terminal is the substrate of the P-type transistor) of the two P-type transistors are connected to the drains or respectively connected to their respective sources; the aspect ratios and layout connection methods of the P-type transistors in the N calibration pseudo-resistance units are exactly the same; the resistance value of the calibration pseudo-resistance unit is:

[0069] Wherein, is the resistance value of the calibration pseudo-resistance unit; is the resistance value of the switched-capacitor reference resistor is the clock frequency, is the sampling capacitor, M is the number of series-connected switched-capacitor units, and N is the number of parallel-connected calibration pseudo-resistance units.

[0070] Specifically, the calibration pseudo-resistance composed of N calibration pseudo-resistance units ( ) connected in parallel finally realizes that the equivalent resistance (R CAL / N) of the N parallel-connected calibration pseudo-resistance units is equal to the reference resistance value (R REF ). Then the resistance value of a single calibration pseudo-resistance unit is NR REF , realizing the amplification of the resistance value.

[0071] The inputs, outputs, and gates of the N parallel-connected calibration pseudo-resistance units are respectively connected to form a calibration pseudo-resistance. The input terminal is connected to the voltage VX, the output terminal is connected to the voltage V B , and the current flowing through the calibration pseudo-resistance is the output current (I OUT ), and the current direction is from VX to VB. The average value of the voltage VB and the voltage VA is the common-mode voltage (VCM) at which the circuit operates.

[0072] The two P-type transistors inside the calibration pseudo-resistance unit are connected in series, and the calibration pseudo-resistance units are connected in parallel. All the calibration pseudo-resistance units are connected to the output point of the low-pass filter.

[0073] In one embodiment, the integrator is a passive or active integrator.

[0074] In one embodiment, the quantizer uses a dynamic comparator or a static comparator to compare the analog voltage and the common-mode voltage.

[0075] In one embodiment, the switch 20 is further configured to, if the input voltage is greater than the common-mode voltage, set the first voltage as the input voltage and the second voltage as the difference between twice the common-mode voltage and the input voltage.

[0076] If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage.

[0077] If the input voltage is equal to the common-mode voltage, both the first voltage and the second voltage are the common-mode voltage.

[0078] Transmit the first voltage to the reference input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator, and transmit the second voltage to the calibration input terminal of the pseudo-resistor calibration module 30 based on the ΔΣ modulator.

[0079] In one embodiment, the replica pseudo-resistor 50 includes: a floating voltage source and a replica pseudo-resistor 50 unit composed of two P-type transistors; the resistance value of the replica pseudo-resistor 50 is controlled by the floating voltage source.

[0080] The floating voltage source includes a unity-gain amplifier and a bootstrap capacitor; The output of the unity-gain amplifier drives the lower plate of the bootstrap capacitor, the input terminal of the unity-gain amplifier is the input terminal of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output terminal of the floating voltage source.

[0081] The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistors in the replica pseudo-resistor 50 unit.

[0082] Specifically, inside the replica pseudo-resistor, there is a replica pseudo-resistor unit composed of two P-type transistors and a floating voltage source. The aspect ratio of the P-type transistors in the replica pseudo-resistor unit is the same as that of the transistors in the calibration pseudo-resistor unit. The connection method is that the drains are connected and connected to the input of the floating voltage source. The sources of the two transistors respectively form the input and output of the replica pseudo-resistor. The gates are connected and connected to the output of the floating voltage source. The connection of the body terminals needs to be consistent with the calibration pseudo-resistor unit. One end of the replica pseudo-resistor is connected to the common-mode voltage (VCM), and the other end is the input voltage (VIN).

[0083] The resistance value of the replica pseudo-resistor is controlled by the floating voltage source. The floating voltage source is composed of a unity-gain amplifier with a high input impedance cascaded with a bootstrap capacitor (C H ), and the output of the unity-gain amplifier is connected to the lower plate of the bootstrap capacitor (C H ). The input of the unity-gain amplifier is the input of the floating voltage source, and the upper plate of the bootstrap capacitor is the output of the floating voltage source.

[0084] In one embodiment, the aspect ratio and connection method of the P-type transistors in the replica pseudo-resistor 50 unit are the same as those of the calibration pseudo-resistor unit in the calibration pseudo-resistor.

[0085] In one embodiment, the control voltage replication circuit 40 includes: a sampling capacitor and a sampling switch.

[0086] At the sampling moment, the voltage difference between the sampled and filtered voltage and the common-mode voltage (VCM) is stored as the voltage difference across the sampling resistor.

[0087] At the transmission moment, the voltage difference across the sampling resistor is transmitted through the sampling switch to the replica dummy resistor 50.

[0088] Specifically, the input signal of the control voltage replication circuit is the difference between the output analog voltage of the low-pass filter and the common-mode voltage. During the sampling period, this difference voltage is stored in the sampling capacitor, and during the transmission period, this difference voltage is transmitted to the capacitor (C H ) in the floating voltage source of the replica dummy resistor formed by P-type transistors.

[0089] In one embodiment, a schematic diagram of a reference dummy resistor calibration loop implemented based on delta-sigma (ΔΣ) modulator technology is as shown in Figure 2 . The principle is that the switched-capacitor reference resistor 1 is formed by connecting M switched-capacitor units 11 in series. The equivalent resistance value of the switched-capacitor unit 11 can be precisely controlled by the clock frequency. One end of the switched-capacitor reference resistor 1 is connected to one end of the calibration dummy resistor 2 formed by P-type transistors and is commonly connected to the input VX of the integrator. The integration voltage result on the integrator 3 is the difference between the injected charge of the switched-capacitor reference resistor 1 and the outflow charge of the calibration dummy resistor 2 formed by P-type transistors. The quantizer 4 quantizes the output result of the integrator 3 and drives the digital-to-analog converter 5, and the low-pass filter 6 filters the output of the digital-to-analog converter 5 to output the filtered voltage 61 after removing high-frequency noise and uses this voltage signal to control the on-resistance of the calibration dummy resistor 2 formed by P-type transistors. The above-mentioned switched-capacitor reference resistor 1, the calibration dummy resistor 2 formed by P-type transistors, the integrator 3, the quantizer 4, the digital-to-analog converter 5, and the low-pass filter 6 together constitute the ΔΣ modulator. The above-mentioned ΔΣ modulator has a large loop gain and a negative feedback response, making the charge flowing into the integrator 3 through the switched-capacitor reference resistor 1 equal to the charge flowing out of the integrator 3 through the calibration dummy resistor 2 formed by P-type transistors, and also making the VX voltage equal to the common-mode voltage VCM.

[0090] The input voltages of the above-mentioned reference dummy resistor calibration loop are VA and VB respectively. VA is the input voltage at one end of the switched-capacitor reference resistor 1, and VB is the input voltage at one end of the calibration dummy resistor 2 formed by P-type transistors. The average value of VA and VB is equal to the common-mode voltage VCM, making the switched-capacitor reference resistor 1 and the calibration dummy resistor 2 formed by P-type transistors have the same voltage drop, and the amount of charge flowing through them is equal, making the resistance value of the switched-capacitor reference resistor 1 equal to the resistance value of the calibration dummy resistor 2 formed by P-type transistors, achieving the calibration and control of the dummy resistor resistance value calibration.

[0091] The resistance value of the switched-capacitor reference resistor 1 composed of M switched-capacitor units 11 connected in series can be adjusted by the clock frequency, and the resistance value is jointly determined by the clock frequency ( ), the sampling capacitor ( ) and the number of series-connected switched-capacitor units (M).

[0092] The calibration dummy resistor 2 composed of P-type transistors, and the calibration dummy resistor is composed of N calibration dummy resistor units ( ) 21 connected in parallel. Each calibration dummy resistor unit 21 contains two series-connected P-type transistors. The connection method is that the drains of the transistors are connected, and the sources of the two transistors respectively form the input and output of the dummy resistor unit, and the gates are connected and connected to the output of the low-pass filter. The body terminals can be selected to be connected to the drains or respectively connected to their own sources. The aspect ratios of the P-type transistors and the layout connection methods in the above N calibration dummy resistor units 21 are exactly the same. The resistance value of the calibration dummy resistor 2 composed of the above P-type transistors is , then the resistance value of a single calibration dummy resistor unit 21 can be calculated as follows:

[0093] The calibration dummy resistor 2 composed of P-type transistors, the resistance value can be adjusted by the clock frequency ( ). The number of series-connected M of the switched-capacitor units 11 and the number of parallel-connected N of the calibration dummy resistor units 21 form a resistance amplification factor, realizing the amplification of the dummy resistor value to NM times the value of the switched-capacitor unit.

[0094] The current flowing into the switched-capacitor reference resistor 1 can be calculated as:

[0095] The current flowing out of the calibration dummy resistor 2 composed of P-type transistors can be calculated as:

[0096] The input signal of the integrator 3 is the difference between the currents I IN and I OUT . The integrator 3 can be composed of a passive or active integrator. The integration capacitor in the integrator is denoted as C INT . The output result of the integrator is and the sum of the integration result of the difference between on the capacitor over a given time and the integration result at the previous moment , and can be calculated as:

[0097] A quantizer 4, whose input signal is the output analog voltage of an integrator 3, converts the comparison result into a digital code output by comparing its magnitude with a common-mode voltage. The comparator circuit inside the quantizer can actually use a dynamic comparator or a static comparator. For the above-mentioned digital-to-analog converter 5, its input signal is the output digital code of the quantizer 4, and the output signal is the corresponding analog voltage. For the above-mentioned low-pass filter 6, its input signal is the output analog voltage of the digital-to-analog converter 5, and the output signal is a filtered voltage 61, which is used to control the resistance value of a calibration pseudo-resistor 2 composed of P-type transistors.

[0098] As Figure 3 shown, a replica pseudo-resistor 50 composed of P-type transistors has its resistance value controlled by a floating voltage source, which is composed of a high-input-impedance unity-gain amplifier 72 cascaded with a bootstrap capacitor 73. The output of the above-mentioned unity-gain amplifier 72 drives the lower plate of the bootstrap capacitor 73. The input of the unity-gain amplifier 72 is the input of the floating voltage source, and the upper plate of the bootstrap capacitor 73 is the output of the floating voltage source. The voltage stored in the bootstrap capacitor controls the on-resistance of the P-type transistors in the replica pseudo-resistor unit 71. The aspect ratio and connection method of the P-type transistors in the replica pseudo-resistor unit 71 are the same as those of the calibration pseudo-resistor unit, minimizing the systematic mismatch between transistors. One end of the resistance of a replica pseudo-resistor 7 composed of P-type transistors needs to be connected to the common-mode voltage (VCM), and the other end is the input voltage (VIN).

[0099] As Figure 4 shown, a control voltage replication circuit 40 is composed of a sampling capacitor and a sampling switch. At the sampling moment, the voltage difference between the sampled filtered voltage 61 and the common-mode voltage (VCM) is stored in the sampling capacitor ; at the transmission moment, the voltage on the sampling capacitor is transmitted to the bootstrap capacitor 73.

[0100] A direction comparator 10, whose input signal is the input voltage VIN, outputs a corresponding control signal (DIR) by comparing the magnitude relationship between the input voltage VIN and the common-mode voltage VCM, controlling the output voltages VA and VB of a switching converter 20. When VIN is greater than VCM, VA is equal to VIN and VB is equal to 2*VCM - VIN. When VIN is less than VCM, VA is equal to 2*VCM - VIN and VB is equal to VIN. When VIN is equal to VCM, both VA and VB are VCM.

[0101] Figure 5 shows the relationship between the clock frequency and the resistance value of the replica pseudo-resistor obtained by testing, achieving a wide-range on-chip adjustment of large resistances from 2.5 T ohms to 1.6 G ohms. Figure 6(a) to (d) therein show the resistance value versus temperature curves obtained from tests under four resistance value configurations. Between -40 °C and 60 °C, the maximum fluctuation of the resistance value is 20%, which is more than two orders of magnitude higher than that of traditional pseudo-resistors. In high-temperature cases, the configuration with a large resistance value will increase the leakage current and reduce the resistance value. Figure 7 (a) to (d) therein show the four test results of 24 chip samples, and the maximum resistance value change rate (triple variance ratio mean) is 25%. Figure 8 It shows the relationship between the total harmonic distortion (THD) and the input voltage amplitude under different input voltage amplitudes, and this calibration scheme achieves a large input range of 3.93 Vpp.

[0102] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0103] The above-described embodiments merely represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An on-chip pseudo-resistance calibration circuit based on a ΔΣ modulator, characterized in that: The upper pseudo-resistance calibration circuit comprises: A direction comparator, used to determine a conversion control signal according to a magnitude relationship between an input voltage and a common mode voltage; A conversion switch, configured to output a first voltage and a second voltage according to the input voltage, the common mode voltage and the conversion control signal, and transmit the first voltage and the second voltage to a reference input terminal and a calibration input terminal of a pseudo-resistance calibration module based on a ΔΣ modulator, respectively; A pseudo-resistance calibration module based on a ΔΣ modulator, which is used to convert a first voltage into a reference current using a switched capacitor reference resistor, convert a second voltage into a calibration current using a calibration pseudo-resistor, integrate, quantize, perform digital-to-analog conversion, and perform low-pass filtering on a difference between the reference current and the calibration current to obtain a filtered voltage, feed the filtered voltage back to the calibration pseudo-resistor, and transmit the filtered voltage to a control voltage replication circuit; A control voltage replication circuit is used to replicate the difference between the filter voltage and the common mode voltage to a replication pseudo resistor; The replica pseudo resistor is used to adjust its resistance value according to the replicated voltage, the common mode voltage and the input voltage, and calibrate its resistance value to several times the resistance value of the switch capacitor reference resistor.

2. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 1, characterized in that: The pseudo-resistance calibration module based on the ΔΣ modulator includes: a switched capacitor reference resistor, a calibration pseudo-resistance, an integrator, a quantizer, a digital-to-analog conversion module, and a low-pass filter; The switched capacitor reference resistor is used to convert the first voltage into a reference current by using a series-connected switched capacitor unit, and transmit the reference current to the integrator; The calibration pseudo resistor is used to convert the second voltage into a calibration current by using a calibration pseudo resistor unit connected in parallel, and transmit the calibration current to the integrator; The integrator is used to integrate the difference between the reference current and the calibration current to obtain an analog voltage; The quantizer is used to compare the analog voltage and the common mode voltage, convert the comparison result into a digital code, and obtain a digital output voltage; The digital-to-analog conversion module is used to convert the digital output voltage into an analog output voltage; The low-pass filter is used to perform low-pass filtering on the analog output voltage to obtain a filtered voltage.

3. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 2, characterized in that: The switch capacitor reference resistor comprises: M switch capacitor resistors connected in series, the resistance of the switch capacitor resistor is adjusted by the clock frequency, and the resistance of the switch capacitor reference resistor is: in, is the resistance of the switched capacitor reference resistor, is the clock frequency, is the sampling capacitor, and M is the number of switch capacitor units connected in series.

4. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 2, characterized in that: The calibration pseudo-resistance is composed of N calibration pseudo-resistance units connected in parallel; The calibration pseudo-resistance unit comprises two P-type transistors connected in series; the drains of the two P-type transistors are connected, the sources of the two P-type transistors respectively constitute the input and output of the calibration pseudo-resistance unit, and the gates of the two transistors are connected and connected to the output end of the low-pass filter; The body terminals of the two P-type transistors are connected to the drains or to their respective sources; The width-to-length ratio and layout connection method of the P-type transistors in the N calibration pseudo-resistance units are exactly the same; The resistance of the calibration pseudo-resistance unit is: in, To calibrate the resistance value of the pseudo resistance unit; is the resistance of the switched capacitor reference resistor, is the clock frequency, is the sampling capacitor, M is the number of switch capacitor units connected in series, and N is the number of calibration pseudo resistance units connected in parallel.

5. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 2, characterized in that: The integrator is a passive or active integrator.

6. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 2, characterized in that: The quantizer uses a dynamic comparator or a static comparator to compare the analog voltage with the common mode voltage.

7. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 1, characterized in that: The conversion switch is further used for, if the input voltage is greater than the common mode voltage, the first voltage is the input voltage, and the second voltage is the difference between twice the common mode voltage and the input voltage; If the input voltage is less than the common-mode voltage, the first voltage is the difference between twice the common-mode voltage and the input voltage, and the second voltage is the input voltage; If the input voltage is equal to the common mode voltage, the first voltage and the second voltage are both common mode voltages; The first voltage is transmitted to a reference input terminal of a pseudo-resistance calibration module based on a ΔΣ modulator, and the second voltage is transmitted to a calibration input terminal of the pseudo-resistance calibration module based on a ΔΣ modulator.

8. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 1, characterized in that: The replica pseudo resistor comprises: a floating voltage source and a replica pseudo resistor unit composed of two P-type transistors; the resistance of the replica pseudo resistor is controlled by the floating voltage source; The floating voltage source includes a unity gain amplifier and a bootstrap capacitor; The output of the unity gain amplifier drives the lower plate of the bootstrap capacitor, the input end of the unity gain amplifier is the input end of the floating voltage source, and the upper plate of the bootstrap capacitor is connected to the output end of the floating voltage source; The voltage stored in the bootstrap capacitor is used to control the on-resistance of the P-type transistor in the replica pseudo-resistance unit.

9. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 8, characterized in that: The width-to-length ratio and connection mode of the P-type transistor in the replica pseudo-resistance unit are the same as the width-to-length ratio and connection mode of the calibration pseudo-resistance unit in the calibration pseudo-resistance.

10. The on-chip pseudo-resistance calibration circuit based on ΔΣ modulator according to claim 1, characterized in that: The control voltage replica circuit comprises: a sampling capacitor and sampling switch; At a sampling moment, sampling a voltage difference between the filter voltage and a common mode voltage (VCM), and storing the voltage difference in a sampling resistor; At the transmission time, the voltage difference on the sampling resistor is transmitted to the replica pseudo resistor through the sampling switch.

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