High-throughput qc-ldpc code encoding method and device adaptive to multiple code types
By constructing H1 XOR tree and H2 inverse XOR tree, parallel information sequence and verification sequence are generated step by step, solving the throughput and code pattern adaptation problems of QC-LDPC encoder in high-speed communication scenarios, and achieving improvements in high throughput and hardware reuse rate.
Patent Information
- Application Number
- CN202510102504.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2045-01-22
AI Technical Summary
Existing QC-LDPC encoders have low throughput in high-speed communication scenarios, are difficult to adapt to multiple code types, have poor hardware reuse, and cannot meet the dual requirements of performance and cost.
By constructing the H1 XOR tree and the H2 inverse XOR tree, parallel information sequences and verification sequences are generated step by step. The XOR tree is used to replace the shift register, which reduces the encoding clock cycle and improves parallelism. It supports encoding with multiple code lengths and multiple code rates, reduces the number of XOR gates, and improves hardware reuse.
It improves the encoder's throughput and flexibility, reduces the clock cycle required for encoding, saves hardware resources, supports adaptation to multiple code lengths and bit rates, and improves hardware reuse rate.
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Figure CN120074545B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of electronic communication, and particularly relates to a quasi-cyclic low-density parity-check (QC-LDPC) encoding method and device, which can be used for channel coding in various high-speed communication scenarios. BACKGROUND
[0002] With the development of wireless communication technology, modern wireless communication has higher requirements for high-speed transmission and reliability of data. Low-density parity-check (LDPC) code is a kind of forward error correction code, and due to its excellent error correction performance close to the Shannon limit, it has been widely applied in IEEE 802.11 communication standards, 5G NR and Bluetooth series standards. Among them, quasi-cyclic low-density parity-check (QC-LDPC) is a special kind of LDPC code, and its generator matrix and check matrix both have quasi-cyclic structure, which makes it have irreplaceable advantages in storage and encoder design. However, the existing QC-LDPC encoder still faces many problems: first, although taking the number of column blocks of the base matrix as the parallel degree of the encoder can improve the throughput of the encoder to a certain extent, a large number of shift registers are needed to serially encode the data in the calculation process of each part of the check sequence, which is difficult to further improve the throughput of the encoder; second, there are many different code lengths and code rates in the existing standards, and the adaptation to multiple types of codes has always been a research difficulty: the existing encoder is often designed for a single code length and a single code rate, and such an encoder has low hardware reuse rate.
[0003] WANG Guodong et al. published "Design and implementation of LDPC encoder based on FPGA" in Journal of Measurement Science and Instrumentation, which uses a generating sub-shift algorithm to encode a single code length and code rate of 8176 and 7 / 8. Although the structure of the encoder is of low complexity, it can only achieve a throughput of 800 Mbps at a working clock of 159 MHz, and it takes 1420 clock cycles for single encoding and the encoder structure only supports a single code length and code rate.
[0004] Sunitha Kopparthi et al. published "Implementation of a Flexible Encoder for Structured Low-Density Parity-Check Codes" in IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, which uses fast iterative algorithm to encode five code lengths and four code rates in IEEE wireless metropolitan area network standard, and the theoretical throughput can be improved to 3.22Gbps~6.28Gbps, but due to the encoder still uses the idea of separate encoding for different code lengths and different code rates, the hardware utilization is low.
[0005] The problems existing in the above prior art all affect the throughput of the QC-LDPC encoder and the flexible adaptation to different code lengths and different code rates, resulting in that the performance requirements cannot be met in high-speed communication scenarios, the hardware multiplexing rate is poor, and it is difficult to meet the dual demands of performance and cost in actual communication systems. SUMMARY
[0006] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a QC-LDPC encoding method and device with high throughput and adaptation to multiple code types, so as to fully utilize the parallel characteristics between bit positions in the QC-LDPC encoding process, improve the throughput of the encoder, and on this basis, reduce the number of operations by using common operations of different code lengths and different code rates, and improve the multiplexing rate of the encoder hardware and the adaptability to multiple code lengths and code rates.
[0007] The technical scheme for achieving the purpose of the present application includes:
[0008] Technical scheme one:
[0009] 1. A QC-LDPC encoding method with high throughput and adaptation to multiple code types, characterized in that it comprises:
[0010] storing the information sequence S into the input register and outputting it in parallel to obtain a parallel information sequence S';
[0011] constructing an H1 XOR tree and using it to XOR the parallel information sequence S' by rows to generate intermediate sequences qn of multiple code lengths and multiple code rates;
[0012] constructing an H2 inverse XOR tree and using it to XOR the intermediate sequences qn by rows to generate encoding sequences pn of multiple code lengths and multiple code rates;
[0013] using a code type selector to select one from the multiple code lengths and multiple code rates of the encoding sequences pn to generate a single code length and code rate check sequence p;
[0014] The parallel information sequence S′ is concatenated with the check sequence p, and then the parallel-to-serial conversion is performed to output the encoded data.
[0015] Preferably, the construction of the H1 XOR tree includes:
[0016] For each known code pattern, a parity-check matrix is provided. Perform column partitioning sequentially to obtain all parity-based pre-submatrices. in Let i be the parity-check basis matrix, and let i be the number of rows. The number of columns is It is the i-th parity-check basis matrix The former List, It is the i-th parity-check basis matrix after m b List;
[0017] All parity basis pre-submatrices Sort the submatrices by increasing row code length and increasing column code rate to obtain the sorted parity-prefix submatrix sequence.
[0018] The sorted parity pre-base submatrix sequence Each row of elements is concatenated with a zero matrix to obtain g XOR tree base matrices of the same code length. in Let I be the j-th XOR tree base matrix with the same code length. ZERO For z j ×z j The zero matrix, z j It is the j-th XOR tree base matrix with the same code length. The corresponding expansion factor is 1≤j≤g;
[0019] XOR all tree base matrices of the same code length Concatenate the zero matrix to obtain the H1 XOR tree base matrix.
[0020] XOR tree base matrix H1 The extension is performed to obtain the H1 XOR tree extension matrix H. 1EX Then, perform a merge operation on the shared elements to obtain the H1 XOR tree merge matrix H. 1COM ;
[0021] Merge the H1 XOR tree into matrix H. 1COM The column index of the element with value 1 in row k is denoted as . Input register number Bits are connected using XOR gates, and the H1 XOR tree is merged into matrix H. 1COMAll row generated XOR gate package, get H1 XOR tree;
[0022] As preferred, the configuration H2 inverse XOR tree, comprising:
[0023] For each code type known corresponding one check base matrix In turn, column segmentation, get all check base after sub-matrix Wherein The number of rows of the i-th check base matrix is The number of columns is The i-th check base matrix The first Column, The i-th check base matrix The last m b Column;
[0024] All check base after sub-matrix In turn, get all check base after inverse matrix
[0025] All check base after inverse matrix According to the row code length increase and column code rate decrease, get the sorted check base after inverse matrix sequence
[0026] The sorted check base after inverse matrix sequence Each row element is spliced with a zero matrix, and g same code length XOR tree inverse base matrix is obtained Wherein The j-th same code length XOR tree base matrix is I ZERO The zero matrix of z j ×z j , z j The expansion factor corresponding to the j-th same code length XOR tree inverse base matrix 1≤j≤g;
[0027] All same code length XOR tree inverse base matrix Spliced with a zero matrix to get H2 inverse XOR tree base matrix H
[0028] The H2 inverse XOR tree base matrix H Expansion to get H2 inverse XOR tree expansion matrix H 2EX , and then perform the merging common operation to get the H2 inverse XOR tree merging matrix H 2COM
[0029] The H2 inverse XOR tree merging matrix H 2COM The column index value at the position where the k-th row element value is 1 is denoted as The input register is connected with the first The H2 inverse XOR tree merging matrix H 2COM All rows of the XOR gate package are generated, and the H2 inverse XOR tree is obtained.
[0030] Technical solution two:
[0031] 2. A QC-LDPC encoding device with high throughput and adaptive multi-type code, comprising:
[0032] A serial-parallel conversion module is configured to convert an input serial information sequence S into a parallel information sequence S' and input the parallel information sequence S' to a parallel-serial conversion module;
[0033] An H1 XOR tree module is configured to perform row-wise XOR operation on the parallel information sequence S' to generate an intermediate sequence qn of multiple code lengths and multiple code rates, and store the intermediate sequence qn in an intermediate sequence register;
[0034] An H2 inverse XOR tree module is configured to perform row-wise XOR operation on the intermediate sequence qn to generate an encoding sequence pn of multiple code lengths and multiple code rates, and input the encoding sequence pn to a code type selector module;
[0035] The code type selector module is configured to perform one-to-many selection on the encoding sequence pn of multiple code lengths and multiple code rates to generate a check sequence p of a single code length and a single code rate, and input the check sequence p to a parallel-serial conversion module;
[0036] The parallel-serial conversion module is configured to perform serial-parallel conversion on the parallel information sequence and the check sequence p after splicing, and output an encoding sequence.
[0037] Compared with the prior art, the present application has the following advantages:
[0038] First, the present application uses check matrix encoding, and divides the main encoding process into two steps by constructing an H1 XOR tree and an H2 inverse XOR tree: calculating an intermediate sequence qn and calculating a check sequence p, thereby reducing the required clock period of theoretical encoding, improving the calculation parallelism, and increasing the theoretical throughput rate of the encoder.
[0039] Second, the present application adopts a full code type encoder, which simultaneously calculates the encoding results of all code lengths and code rates when calculating the intermediate sequence qn and the check sequence pn, and performs encoding output according to the externally input code length and code rate, thereby increasing the flexibility and adaptability of the encoder.
[0040] Third, the present application can reduce the number of XOR gates required for encoding by performing merging common operation on the H1 XOR tree matrix and the H2 inverse XOR tree matrix, thereby improving the reuse rate of the logic hardware while ensuring the correctness of the encoding result.
[0041] Fourthly, the present application uses XOR tree to replace the shift register used in the traditional coding scheme, which can save hardware storage resources, and support the generation of the simplest H1 XOR tree and H2 inverse XOR tree when only a single code length code rate is needed, further improving the hardware utilization rate. BRIEF DESCRIPTION OF DRAWINGS
[0042] Figure 1 is the flow chart of the present application;
[0043] Figure 2 is the sub-flow chart of constructing H1 XOR tree in the present application;
[0044] Figure 3 is the sub-flow chart of constructing H2 inverse XOR tree in the present application;
[0045] Figure 4 is the structure schematic diagram of the device of the present application;
[0046] Figure 5 is the comparison chart of the present application and the existing algorithm theoretical throughput rate;
[0047] Figure 6 is the comparison chart of the present application and the existing algorithm hardware resource consumption. DETAILED DESCRIPTION
[0048] The implementation and effects of the present application are further described in detail below in combination with the drawings.
[0049] Embodiment 1: QC-LDPC coding method with high throughput and adaptive to multiple code types.
[0050] Referring to Figure 1 , the implementation steps of the present example include the following:
[0051] Step 1, obtaining parallel information sequence S' and storing it in the output register.
[0052] 1.1) storing the information sequence S into the input register with bit width of r max ×g max serially;
[0053] 1.2) outputting the first L bits of the input register in parallel to obtain the parallel information sequence S';
[0054] 1.3) storing the parallel information sequence S' into the first L bits of the output register with bit width of g max .
[0055] In the present example, the information sequence S=(s1,s2,…s L ), that is, the information bits have L bits; the encoder supports t code types of r code rates and g code lengths, wherein the maximum code rate in the r code rates is denoted as r maxThe maximum code length among the g code lengths is denoted as g. max .
[0056] Step 2: Construct the H1 XOR tree.
[0057] Reference Figure 2 The implementation of this step includes the following:
[0058] 2.1) For each known code pattern, a parity-check matrix is generated. Perform column partitioning sequentially to obtain all parity-based pre-submatrices. in:
[0059] Let i be the parity-check basis matrix, and let i be the number of rows. The number of columns is
[0060] It is the i-th parity-check basis matrix The former List, It is the i-th parity-check basis matrix after m b List,
[0061] The element values in the array are all not greater than z. i The number composition, z i It is the base matrix extension factor.
[0062] 2.2) All parity basis submatrices Sort the submatrices by increasing row code length and increasing column code rate to obtain the sorted parity-prefix submatrix sequence.
[0063]
[0064] in It is the sorted sequence of submatrices before the parity basis. The submatrix in row j and column k.
[0065] In this example, the sorted The code lengths corresponding to the elements in each row of the matrix sequence are equal, and the code rates corresponding to the elements in each column are equal, that is, they satisfy:
[0066]
[0067] Where Length(·) calculates the code length of the code corresponding to the element, and Rate(·) calculates the code rate of the code corresponding to the element.
[0068] 2.3) The sorted parity base submatrix sequence Each row of the element is spliced with a zero matrix to obtain g same code length XOR tree base matrices Wherein:
[0069] is the jth same code length XOR tree base matrix, I ZERO is a zero matrix of z j ×z j , z j is the expansion factor corresponding to the jth same code length XOR tree base matrix .
[0070] 2.4) Splice all same code length XOR tree base matrices to obtain the H1 XOR tree base matrix
[0071]
[0072] Wherein I ZERO represents a zero matrix of z j ×z j , z j is the expansion factor corresponding to the jth same code length XOR tree base matrix ,each element value in represents a z j order unit matrix cyclically right shifted by the value obtained square matrix;
[0073] In this example, is a matrix with rows and columns, and the upper right part of the matrix is a zero matrix.
[0074] 2.5) Expanding the H1 XOR tree base matrix to obtain the H1 XOR tree expansion matrix H 1EX , and then performing a merging common operation to obtain the H1 XOR tree merging matrix H 1COM :
[0075] 2.5.1) Calculate the H1 XOR tree base matrix each row of which is expanded by the expansion factor z i :
[0076]
[0077] Wherein refers to the common code length of each base matrix in the same code length XOR tree base matrix , is the number of columns of the check base matrix of the ith code length;
[0078] 2.5.2) Splice Each element value in the array is expanded into a z. i The square matrix obtained by cyclically right-shifting the identity matrix of order 1 by this value yields the H1 XOR tree extension matrix H. 1EX :
[0079]
[0080] Where h (u1,v1) It is H 1EX The element in row u1 and column v1, h (u1,v2) It is H 1EX The element in row u1 and column v2, h (u2,v1) It is H 1EX The element in row u2 and column v1, h (u2,v2) It is H 1EX The element in row u2 and column v2, and h (u1,v1) =h (u1,v2) =h (u2,v1) =h (u2,v2) =1.
[0081] 2.5.3) Expand the H1 XOR tree matrix H 1EX Perform the merge operation, that is, traverse the H1 XOR tree extension matrix H. 1EX All elements, merge h (u2,v1) and h (u2,v2) After passing through the XOR gate, we obtain the H1 XOR tree merge matrix H. 1COM :
[0082]
[0083] 2.6) Merge the H1 XOR tree into matrix H 1COM The column index of the element with value 1 in row k is denoted as . Input register number Bits are connected using XOR gates, and the H1 XOR tree is merged into matrix H. 1COM The XOR gates generated from all rows are encapsulated to obtain the H1 XOR tree.
[0084] Step 3: Use the H1 XOR tree to perform row-wise XOR on the parallel information sequence S′ to generate an intermediate sequence qn with multiple code lengths and multiple code rates.
[0085] 3.1) Store the column indices of elements with a value of 1 in each row of the H1 XOR tree, where the index of the element with a value of 1 in the k-th row is _____.
[0086] 3.2) For the parallel information sequence S′, the first... Perform an XOR operation on each bit to obtain the k-th bit of the i-th intermediate sequence qi;
[0087] 3.3) Traverse all rows of the H1 XOR tree, and perform XOR operation on the parallel information sequence S' according to the stored column index values in sequence to generate intermediate sequences qn of multiple code lengths and multiple code rates.
[0088] Step 4, construct the H2 inverse XOR tree.
[0089] Referring to Figure 3 , the implementation of this step includes the following:
[0090] 4.1) Perform column segmentation on each check basis matrix corresponding to each known code type to obtain all check basis sub-matrices wherein:
[0091] is the ith check basis matrix, the number of rows of which is and the number of columns of which is
[0092] is the first columns of the ith check basis matrix is the last m b columns of the ith check basis matrix
[0093] The element values in i are all not greater than z i , and z i is the basis matrix expansion factor.
[0094] 4.2) Invert all check basis sub-matrices in sequence to obtain all check basis inverse matrices
[0095] 4.3) Sort all check basis inverse matrices according to increasing row code length and decreasing column code rate to obtain a sorted check basis inverse matrix sequence
[0096]
[0097] wherein is the sorted check basis inverse matrix sequence , and the jth row and kth column sub-matrix of
[0098] In this example, the sorted check basis inverse matrix sequence has equal code lengths corresponding to the elements in each row and equal code rates corresponding to the elements in each column, i.e., it satisfies:
[0099]
[0100] where Length(·) denotes the code length corresponding to the element, and Rate(·) denotes the code rate corresponding to the element.
[0101] 4.4) The sorted check basis inverse matrix sequence Each row element is spliced with a zero matrix to obtain g same code length XOR tree inverse basis matrices wherein:
[0102] is the jth same code length XOR tree basis matrix, I ZERO represents a zero matrix of z j ×z j , z j is the expansion factor corresponding to the jth same code length XOR tree inverse basis matrix .
[0103] 4.5) All same code length XOR tree inverse basis matrices are spliced with zero matrices to obtain H2 inverse XOR tree basis matrices
[0104]
[0105] wherein I ZERO represents a zero matrix of z j ×z j , z j is the expansion factor corresponding to the jth same code length XOR tree inverse basis matrix , each element value in j represents a z 2EX order unit matrix cyclically right shifted by the value obtained square matrix;
[0106] In this example, is a matrix with a row number of and a column number of , and the upper right part of the matrix is a zero matrix.
[0107] 4.6) The H2 inverse XOR tree basis matrix is expanded to obtain the H2 inverse XOR tree expansion matrix H 2COM , and then a merge common operation is performed to obtain the H2 inverse XOR tree merge matrix H i :
[0108] 4.6.1) The H2 inverse XOR tree basis matrix is expanded by each row expansion factor z i :
[0109]
[0110] wherein is the same code length XOR tree basis matrix the common code length of each base matrix, is the check base matrix of the ith code length the number of columns of
[0111] 4.6.2) expand each element value in to a z i square matrix by cyclically right shifting the value obtained by the z 2EX :
[0112]
[0113] where e (u1,v1) is the element in the u1th row and the v1th column of H 2EX , e (u1,v2) is the element in the u1th row and the v2th column of H 2EX , e (u2,v1) is the element in the u2th row and the v1th column of H 2EX , e (u2,v2) is the element in the u2th row and the v2th column of H 2EX , and e (u1,v1) = e (u1,v2) = e (u2,v1) = e (u2,v2) = 1.
[0114] 4.6.3) perform a merge common operation on the H2 inverse XOR tree merge matrix H 2EX , i.e., traverse all the elements of the H2 inverse XOR tree expansion matrix H 2EX , merge the XOR gates at e (u2,v1) and e (u2,v2) , to obtain the H2 inverse XOR tree merge matrix H 2COM :
[0115]
[0116] 4.7) the column index value at which the element value in the kth row of the H2 inverse XOR tree merge matrix H 2COM is 1 is denoted as , and the XOR gate is connected between the bit of the input register, and the H2 inverse XOR tree merge matrix H 2COM is encapsulated by the XOR gate generated by all the rows to obtain the H2 inverse XOR tree.
[0117] Step 5, the H2 inverse XOR tree is used to perform row XOR on the intermediate sequence qn to generate a multi-code length and multi-code rate coded sequence pn.
[0118] 5.1) store the column index at which the element value in each row of the H2 inverse XOR tree is 1, where the index at which the element value in the kth row is 1 is denoted as
[0119] 5.2) XOR operation is performed on the kth bit of the intermediate sequence qi in the ith group, to obtain the kth bit of the check sequence pi of the ith group.
[0120] 5.3) All rows of the H2 inverse XOR tree are traversed, and XOR operation is performed on the intermediate sequence qn according to the stored column index value, to generate the coded sequence pn of multiple code lengths and multiple code rates.
[0121] Step 6, the coded sequence pn of multiple code lengths and multiple code rates is subjected to one-to-many selection by using the code type selector, to generate the check sequence p of single code length and code rate.
[0122] 6.1) All code rates, all code lengths and the check sequence values q1, q2, …, q i ,…,q t are stored in the code type selection table.
[0123] 6.2) The multiplexer is generated according to the code type selection table.
[0124] 6.3) The required coded code rate r n , the required coded code length g n are input into the multiplexer, to generate the check sequence of the required code type.
[0125] In this example, the code type selector inputs are the required coded code rate r n , the required coded code length g n and the t groups of check sequence values q1, q2, …, q i ,…,q t , and the code type selector output is the check sequence of the required code length and code rate, which is stored in the output register, starting from the (L+1)th bit of the output register and stored from low to high.
[0126] Step 7, the parallel information sequence S' and the check sequence p are spliced and subjected to parallel-to-serial conversion, to output the coded data.
[0127] 7.1) The 1st to Lth bits of the parallel information sequence S' are stored in the corresponding 1st to Lth bits of the output register; 7.2) the 1st to r n ×g n bits of the stored check sequence p are stored in the (L+1)th to (L+r n ×g n bits of the output register.
[0128] 7.3) The 1st to (L+r n ×g n bits of the output register are subjected to parallel-to-serial conversion to obtain the required coded data, which is output from the output register from low to high.
[0129] Embodiment 2: QC-LDPC encoding device with high throughput and adaptive multi-type code
[0130] Reference Figure 4 The device of the present example comprises a serial-parallel conversion module 1, an H1 XOR tree module 2, an H2 inverse XOR tree module 3, a code type selector module 4, and a parallel-serial conversion module 5. The encoding principle is as follows:
[0131] The serial-parallel conversion module 1 converts the input serial information sequence S into a parallel information sequence S' and inputs it to the parallel-serial conversion module; the H1 XOR tree module 2 XORs the parallel information sequence S' by rows to generate intermediate sequences qn of multiple code lengths and multiple code rates, and stores them in an intermediate sequence register; the H2 inverse XOR tree module 3 takes out the intermediate sequences qn stored in the intermediate sequence register, XORs the intermediate sequences qn by rows to generate encoding sequences pn of multiple code lengths and multiple code rates, and inputs them to the code type selector module; the code type selector module 4 establishes a code type selection table for all code rates and all code lengths and the encoding sequences pn, generates a multiplexer according to the code type selection table, inputs the required encoding code rate r n , the required encoding code length g n to the multiplexer, generates a check sequence p, and inputs it to the parallel-serial conversion module; and the parallel-serial conversion module 5 concatenates the parallel information sequence S' and the check sequence p, and then performs parallel-serial conversion to output the encoding sequence.
[0132] The effect of the present application is further illustrated by simulation experiments.
[0133] I. Simulation conditions:
[0134] The simulation uses a CPU of Intel Core i9-10900F with a frequency of 2.80 GHz, a memory of 32.0 GB, a 64-bit operating system, and Microsoft Windows 10 Professional, and the simulation software is MATLAB 2022a.
[0135] The simulation standard is IEEE 802.11 series standard, which has 648, 1296, and 1944 code lengths, each with 1 / 2, 2 / 3, 3 / 4, and 5 / 6 code rates, i.e., there are 12 code types, each corresponding to a check basis matrix.
[0136] II. Simulation content and result analysis:
[0137] Simulation 1: Under the above simulation conditions, the information sequences of the 12 code types are set as pseudo-random sources, and the MATLAB random number seed is set as a fixed value. The information sequences of each code type are encoded using the method of the present application, the traditional generation of sub-shift algorithm, and the fast iterative encoding algorithm, respectively. The results are shown in Table 1.
[0138] Table 1 Comparison of coding results between the present invention and traditional algorithms.
[0139]
[0140] As can be seen from Table 1, under all 12 code types, the encoding results obtained by the present invention are consistent with those obtained by the traditional generator sub-shift algorithm and the fast iterative coding algorithm, indicating that the encoding results of the present invention are correct.
[0141] Simulation 2: Under the above simulation conditions, the required code length is set to 1944, the required code rate to be 5 / 6, and the clock frequency to be 200MHz. The theoretical maximum throughput supported by the present invention, the traditional generator sub-shift algorithm, and the fast iterative coding algorithm are calculated respectively. Where N L It is the code length, N R It's the bitrate, f CLK It is the operating clock frequency, N CC It is the number of clock cycles required for one encoding operation.
[0142] The theoretical maximum throughput of the three methods is compared, and the results are as follows: Figure 5 .
[0143] from Figure 5 As can be seen, under the given 12 code types, the theoretical throughput of this invention reaches a maximum of 162Gbps when the code length is 1944 and the code rate is 5 / 6. Its theoretical throughput is 40.5 times that of the traditional generator sub-shift algorithm and 12 times that of the fast iterative coding algorithm. At the same time, under other code types, the theoretical throughput of this invention is better than other algorithms, indicating that this invention has a high theoretical coding throughput.
[0144] Simulation 3: Under the above simulation conditions, the computational and storage resources required for the present invention, the traditional generator shift algorithm, and the fast iterative coding algorithm to complete the encoding are calculated respectively. The results are as follows: Figure 6 .
[0145] Since the encoding process involves performing an XOR operation on the bit stream, computational resources refer to the number of XOR operations, and storage resources refer to the total number of bits in the registers required to store the variables.
[0146] from Figure 6 As can be seen, the present invention requires 41,588 XOR calculations and occupies 3,564 bits of memory, which consumes less hardware resources than traditional generator shift algorithms and fast iterative coding algorithms.
[0147] The above description is only the preferred embodiment of the present application, and does not constitute any limitation on the present application. Those skilled in the art can make modifications and replacements in form and details without departing from the principles and structures of the present application after understanding the principles and implementation methods of the present application, but the above modifications shall be included in the protection scope of the present application.
[0148] It should be noted that the step numbers in the present application specification and claims are only for clearly describing the embodiments of the present application, facilitating understanding, and the sequence of the numbers is not limited.
Claims
1. A QC-LDPC encoding method of high throughput, adaptive multi-class code type, characterized in that, The method comprises the following steps: storing the information sequence S into an input register and outputting in parallel to obtain a parallel information sequence S'; constructing an H1 exclusive-OR tree and using the H1 exclusive-OR tree to perform exclusive-OR operation on the parallel information sequence S' by row to generate an intermediate sequence qn of multiple code lengths and multiple code rates; the H1 exclusive-OR tree is obtained according to the following manner: performing column segmentation on the check basis matrix in sequence to obtain all check basis pre-submatrices, sorting the check basis pre-submatrices according to the increase of row code length and the increase of column code rate to obtain a sorted check basis pre-submatrix sequence, and splicing a zero matrix to each row element of the sorted check basis pre-submatrix sequence to obtain g same code length exclusive-OR tree basis matrices; splicing a zero matrix to the same code length exclusive-OR tree basis matrices to obtain an H1 exclusive-OR tree basis matrix; performing merging common operation on the H1 exclusive-OR tree basis matrix after expansion to obtain an H1 exclusive-OR tree merging matrix, and encapsulating exclusive-OR gates generated by all rows of the H1 exclusive-OR tree merging matrix to obtain an H1 exclusive-OR tree; constructing an H2 inverse exclusive-OR tree and using the H2 inverse exclusive-OR tree to perform exclusive-OR operation on the intermediate sequence qn by row to generate an encoding sequence pn of multiple code lengths and multiple code rates; the H2 inverse exclusive-OR tree is obtained according to the following manner: performing column segmentation on the check basis matrix in sequence to obtain all check basis post-submatrices, inverting all check basis post-submatrices in sequence to obtain all check basis post-inverse matrices, sorting the check basis post-inverse matrices according to the increase of row code length and the increase of column code rate to obtain a sorted check basis post-inverse matrix sequence; splicing a zero matrix to each row element of the sorted check basis post-inverse matrix sequence to obtain g same code length exclusive-OR tree basis matrices; splicing a zero matrix to the same code length exclusive-OR tree basis matrices to obtain an H2 inverse exclusive-OR tree basis matrix, performing merging common operation on the H2 inverse exclusive-OR tree basis matrix after expansion to obtain an H2 inverse exclusive-OR tree merging matrix; and encapsulating exclusive-OR gates generated by all rows of the H2 inverse exclusive-OR tree merging matrix to obtain an H2 inverse exclusive-OR tree; using a code type selector to perform multiple selection on the encoding sequence pn of multiple code lengths and multiple code rates to generate a check sequence p of single code length and code rate; splicing the parallel information sequence S' and the check sequence p and performing parallel-serial conversion to output an encoding sequence.
2. The method according to claim 1, wherein: The input register has a bit width equal to the maximum code length L of all code types in the information sequence S to be encoded max ; the information sequence S and the parallel information sequence S' respectively represent the following: S = (s1, s2,... s L ); where s1'=s1, s2'=s2,..., s L '=s L .
3. The method of claim 1, wherein, the H1 exclusive-OR tree is constructed by: (3a) a check matrix corresponding to each code type known Column partitioning is sequentially performed to obtain all check base pre-submatrices wherein is the i-th check matrix, the number of rows of is the i-th check matrix, the number of rows of is the i-th parity check matrix of the first column, is the i-th parity check matrix of the last m b columns; (3b) all the check basis pre-submatrices According to the row code length increase and the column code rate increase, the check basis pre-submatrices are sorted to obtain a sorted check basis pre-submatrix sequence wherein is the sorted check basis submatrix sequence the jth row, kth column submatrix; (3c) concatenating the sorted check basis pre-submatrix sequence Each row element concatenates a zero matrix, and g same code length XOR tree basis matrices are obtained wherein is the jth identical code length XOR tree basis matrix, I ZERO is the zero matrix of size z j × z j , z j is the jth identical code length XOR tree basis matrix corresponding to the expansion factor, 1≤j≤g; (3d) Concatenate all the same length XOR tree base matrices with zero matrices to get H1 XOR tree base matrix where I ZERO represents a zero matrix of size z j × z j , z j is the jth identical code length XOR tree basis matrix corresponding to the expansion factor, 1≤j≤g, each element value in the matrix represents a z j order unit matrix which is cyclically right shifted by the value obtained square matrix; (3e) H1 XOR tree base matrix H1 XOR tree extended matrix H is obtained by expanding H1 XOR tree base matrix H 1EX H1 XOR tree merge matrix H is obtained by performing merge common operation on H1 XOR tree extended matrix H 1COM ; (3f) The H1 XOR tree merge matrix H 1COM The column index value at which the kth row element value is 1 is denoted as The input register is denoted as The XOR gates between the bits are connected, and the H1 XOR tree merge matrix H 1COM The XOR gates generated by all rows are encapsulated, and the H1 XOR tree is obtained.
4. The method of claim 1, wherein, the H1 exclusive-OR tree is used to perform exclusive-OR operation on the parallel information sequence S' by row to generate the intermediate sequence qn of multiple code lengths and multiple code rates, which comprises the following steps: The column index of each row element value 1 of the H1 exclusive OR tree is stored, wherein the index of the element value 1 in the kth row is denoted as The kth bit of the ith intermediate sequence qi is obtained by performing exclusive OR operation on the kth bit of the parallel information sequence S' and the kth bit of the (i-1)th intermediate sequence q(i-1). The kth bit of the ith intermediate sequence qi is obtained by performing exclusive OR operation on the kth bit of the parallel information sequence S' and the kth bit of the (i-1)th intermediate sequence q(i-1). all rows of the H1 exclusive-OR tree are traversed, and the parallel information sequence S' is subjected to exclusive-OR operation according to the stored column index values in sequence to generate the intermediate sequence qn of multiple code lengths and multiple code rates.
5. The method of claim 1, wherein, the H2 inverse exclusive-OR tree is constructed by: (5a) a check matrix corresponding to each code type known Column partitioning is sequentially performed to obtain all check matrix submatrices wherein is the ith check matrix, having a row number of having a column number of is the i-th parity check matrix of the first column, is the i-th parity check matrix of the last m b columns; (5b) Compute all the parity-check matrix H (5c) all the check matrix post-inverses sorted by increasing row code length and decreasing column code rate, resulting in a sorted sequence of check matrix post-inverses wherein is the sorted check basis post-inverse matrix sequence the jth row, kth column submatrix (5d) the sorted check basis post-inverse matrix sequence Each row of elements concatenates a zero matrix, respectively, to obtain g same code length XOR tree inverse basis matrix wherein is the jth identical code length XOR tree base matrix, I ZERO represents a zero matrix, z j ×z j represents a zero matrix, z j is the jth identical code length XOR tree inverse base matrix is the corresponding extension factor, 1≤j≤g; (5e) Invert the all-zeros matrix to get the H2 XOR tree basis matrix Concatenate the all-zeros matrix to get the H2 inverse XOR tree basis matrix where I ZERO represents z j ×z j zero matrix, z j is the jth identical code length XOR tree inverse basis matrix corresponding to the expansion factor, 1≤j≤g. each element value in the matrix represents a z j order unit matrix cyclically right shifted by the value obtained square matrix; (5f) H2 inverse XOR tree base matrix The H2 inverse XOR tree base matrix H is obtained by performing expansion on H2 inverse XOR tree base matrix H 2EX The H2 inverse XOR tree base matrix H is obtained by performing expansion on H2 inverse XOR tree base matrix H 2COM ; (5g) The H2 inverse XOR tree merge matrix H 2COM The column index value at which the kth row element value is 1 is denoted as The input register is denoted as The XOR gates between the bits are connected, and the H2 inverse XOR tree merge matrix H 2COM The XOR gates generated by all rows are encapsulated to obtain the H2 inverse XOR tree.
6. The method of claim 1, wherein: the H2 inverse exclusive-OR tree is used to perform exclusive-OR operation on the intermediate sequence qn by row to generate the encoding sequence pn of multiple code lengths and multiple code rates, which comprises the following steps: Store the column indices of each row of the H2 inverse XOR tree where the element value is 1, where the indices of the k-th row where the element value is 1 are... For the i-th intermediate sequence qi Perform an XOR operation on the bits to obtain the k-th bit of the i-th check sequence pi; all rows of the H2 inverse exclusive-OR tree are traversed, and the intermediate sequence qn is subjected to exclusive-OR operation according to the stored column index values in sequence to generate the encoding sequence pn of multiple code lengths and multiple code rates.
7. The method of claim 1, wherein, the code type selector is used to perform multiple selection on the encoding sequence pn of multiple code lengths and multiple code rates to generate the check sequence p of single code length and code rate, which comprises the following steps: All code rates, all code lengths, and check sequence values q1, q2,..., q i ,…,q t Establish a code type selection table; a multiple selection selector is generated according to a code type selection table; The desired encoding code rate r n The desired encoding code length g n The input multiplexer generates the desired code type check sequence.
8. The method of claim 1, wherein, the parallel information sequence S' and the check sequence p are spliced and subjected to parallel-serial conversion to output the encoding data, which comprises the following steps: The first bit to the Lth bit of the parallel information sequence S' are stored in the corresponding first bit to the Lth bit of the output register; The first to r-th bits of the stored check sequence p are stored into the output register from the L+1-th to L+r-th bits n x g n bits; the first to r-th bits of the stored check sequence p are stored into the output register from the L+1-th to L+r-th bits n x g n bits; The first bit to the L+r bit of the output register n xg n The parallel-to-serial conversion is performed on the bits to obtain the required encoded data, which is output from the low bit to the high bit of the output register.
9. The method of claim 3, wherein: The H1 XOR tree spreading matrix H constructed in step (3e) 1EX which is expressed as follows: where h (u1,v1) is H 1EX is the element in row u1 and column v1, h (u1,v2) is H 1EX is the element in row u1 and column v2, h (u2,v1) is H 1EX is the element in row u2 and column v1, h (u2,v2) is H 1EX is the element in row u2 and column v2, and h (u1,v1) = h (u1,v2) = h (u2,v1) = h (u2,v2) = 1.
10. The method of claim 3, wherein: In step (3e), matrix H 1EX To perform the merge operation, traverse the H1 XOR tree extension matrix H. 1EX All elements, merge h (u2,v1) and h (u2,v2) After passing through the XOR gate, we obtain the H1 XOR tree merge matrix H. 1COM It is represented as follows: wherein h (u1,v2) is H 1EX is the element in row u1 and column v2, h (u2,v1) is H 1EX is the element in row u2 and column v1.
11. The method of claim 5, wherein, The H2 inverse XOR tree merge matrix H constructed in step (5f) 2EX which is represented as follows: where e (u1,v1) is H 2EX is the element in the u1th row and v1th column, e (u1,v2) is H 2EX is the element in the u1th row and v2th column, e (u2,v1) is H 2EX is the element in the u2th row and v1th column, e (u2,v2) is H 2EX is the element in the u2th row and v2th column, and e (u1,v1) = e (u1,v2) = e (u2,v1) = e (u2,v2) = 1.
12. The method of claim 5, wherein: In step (5f) the matrix H 2EX is combined with the common operation, which is traversing H2 inverse XOR tree expansion matrix H 2EX all elements, combining e (u2,v1) and e (u2,v2) at XOR gate, resulting in H2 inverse XOR tree combined matrix H 2COM which is represented as follows: where e (u1,v2) is H 2EX the element in row u1, column v2, e (u2,v1) is H 2EX the element in row u2, column v1.
13. A QC-LDPC encoding device of high throughput and adaptive multi-class code type, characterized in that, The application relates to a parallel-serial conversion module for converting an input serial information sequence S into a parallel information sequence S' and inputting the parallel information sequence S' into the parallel-serial conversion module; The H1 XOR tree module is used for performing row-wise XOR operation on the parallel information sequence S' to generate an intermediate sequence qn of multiple code lengths and multiple code rates and storing the intermediate sequence qn in an intermediate sequence register; the H1 XOR tree is obtained according to the following manner: The check matrix is sequentially subjected to column segmentation to obtain all check matrix pre-submatrices, the check matrix pre-submatrices are sorted according to increasing row code length and increasing column code rate to obtain a sorted check matrix pre-submatrix sequence, and the elements of each row of the sorted check matrix pre-submatrix sequence are spliced with zero matrices respectively to obtain g same-code-length XOR tree base matrices; the same-code-length XOR tree base matrices are spliced with zero matrices to obtain an H1 XOR tree base matrix; The H1 XOR tree base matrix is expanded and then subjected to a merge-common operation to obtain an H1 XOR tree merge matrix; the XOR gates generated by all rows of the H1 XOR tree merge matrix are encapsulated to obtain an H1 XOR tree; The H2 inverse XOR tree module is used for performing row-wise XOR operation on the intermediate sequence qn to generate an encoding sequence pn of multiple code lengths and multiple code rates and inputting the encoding sequence pn into a code type selector module; the H2 inverse XOR tree is obtained according to the following manner: The check matrix is sequentially subjected to column segmentation to obtain all check matrix post-submatrices, all the check matrix post-submatrices are sequentially inverted to obtain all check matrix post-inverse matrices, the check matrix post-inverse matrices are sorted according to increasing row code length and increasing column code rate to obtain a sorted check matrix post-inverse matrix sequence; the elements of each row of the sorted check matrix post-inverse matrix sequence are spliced with zero matrices respectively to obtain g same-code-length XOR tree base matrices; the same-code-length XOR tree base matrices are spliced with zero matrices to obtain an H2 inverse XOR tree base matrix, the H2 inverse XOR tree base matrix is expanded and then subjected to a merge-common operation to obtain an H2 inverse XOR tree merge matrix; the XOR gates generated by all rows of the H2 inverse XOR tree merge matrix are encapsulated to obtain an H2 inverse XOR tree; The code type selector module is used for performing multiple selection on the encoding sequence pn of multiple code lengths and multiple code rates to generate a check sequence p of a single code length and a single code rate and inputting the check sequence p into the parallel-serial conversion module; The parallel-serial conversion module is used for splicing the parallel information sequence and the check sequence p and then performing parallel-serial conversion to output an encoding sequence.