Printed circuit board, electronic equipment and vehicle

Abstract

The invention relates to a printed circuit board, electronic equipment and a vehicle. The printed circuit board comprises a multi-layer circuit substrate, a first impedance line, a second impedance line and a reference layer. The first impedance line and the second impedance line are respectively positioned on the circuit substrates of different layers and are electrically connected through via holes; the reference layer is located in a via hole avoiding area and is arranged between a layer where the first impedance line is located and a layer where the second impedance line is located, the reference layer is overlapped with the first impedance line and / or the second impedance line in the stacking direction of the circuit substrate, the reference layer is connected with a reference potential, and the reference layer is connected with the second impedance line. And the via hole avoiding area is arranged around the via hole. According to the technical scheme, the problem that the impedance line is inductively suddenly changed at the via hole position can be solved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of printed circuit boards, and particularly to a printed circuit board, an electronic device, and a vehicle. Background Art

[0002] A printed circuit board (PCB) is fabricated using electronic printing technology. The printed circuit board is not only a carrier for providing circuits but also a carrier for providing electrical signals. Printed circuit boards in certain communication, medical, and industrial control industries have certain requirements for impedance and need to design impedance lines.

[0003] The design expectation of impedance lines is to ensure that the impedance remains as consistent as possible at all positions of the impedance lines, that is, it is necessary to be as close as possible to the design target (such as 50 ohms) to avoid sudden changes in impedance up and down. When designing impedance lines on a multi-layer printed circuit board, there is a situation where the impedance line changes layers. At this time, it is necessary to drill holes in the printed circuit board, and the impedance line changes layers through vias. However, the impedance at the via position usually has a capacitive mutation or an inductive mutation. To address this problem, currently, the capacitance and inductance of the via can be fine-tuned by adjusting the avoidance distance between the via and the surrounding copper foil. For example, the smaller the avoidance distance, the impedance of the via can be adjusted towards the capacitive direction, and the larger the avoidance distance, the impedance of the via can be adjusted towards the inductive direction. However, due to process limitations, both the via size and the avoidance distance have a minimum limit. If the impedance line has an inductive mutation at the via position and the via still shows inductance when the avoidance distance reaches the process limit, the problem of the inductive mutation of the impedance line at the via position cannot be solved by adjusting the avoidance distance. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a printed circuit board, an electronic device, and a vehicle to solve the problem of the inductive mutation of the impedance line at the via position.

[0005] The present disclosure provides a printed circuit board, including a multi-layer circuit substrate, a first impedance line, a second impedance line, and a reference layer;

[0006] The first impedance line and the second impedance line are respectively located on different layers of the circuit substrate and are electrically connected through vias;

[0007] The reference layer is located in the via avoidance area, is disposed between the layer where the first impedance line is located and the layer where the second impedance line is located, and in the stacking direction of the circuit substrate, the reference layer overlaps with the first impedance line and / or the second impedance line, wherein the reference layer is connected to a reference potential, and the via avoidance area is arranged around the via.

[0008] In the present disclosure, the circuit substrate includes a ground layer, and the reference layer is electrically connected to the ground layer.

[0009] In the present disclosure, the reference layer includes a first sub-reference layer and / or a second sub-reference layer;

[0010] In the stacking direction of the circuit board, the first sub-reference layer overlaps with the first impedance line, and / or the second sub-reference layer overlaps with the second impedance line.

[0011] In the present disclosure, the first sub-reference layer and the ground layer of the circuit board where the first impedance line is located are on the same layer, and / or the second sub-reference layer and the ground layer of the circuit board where the second impedance line is located are on the same layer.

[0012] In the present disclosure, the first sub-reference layer extends along the length direction of the first impedance line, and the width of the first sub-reference layer is greater than or equal to the line width of the first impedance line;

[0013] And / or, the second sub-reference layer extends along the length direction of the second impedance line, and the width of the second sub-reference layer is greater than or equal to the line width of the second impedance line.

[0014] In the present disclosure, the reference layer and the ground layer are made of the same material.

[0015] In the present disclosure, the reference layer is an extension of the ground layer to the via avoidance area.

[0016] In the present disclosure, the multi-layer circuit board includes a top-layer circuit board and a bottom-layer circuit board. The first impedance line is located on the surface of the top-layer circuit board away from the bottom-layer circuit board, and the second impedance line is located on the surface of the bottom-layer circuit board away from the top-layer circuit board.

[0017] The present disclosure also provides an electronic device, including the printed circuit board provided by the present disclosure.

[0018] The present disclosure also provides a vehicle, including the electronic device provided by the present disclosure.

[0019] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0020] The technical solution provided by the embodiments of the present disclosure adds a reference layer between the layer where the first impedance line is located and the layer where the second impedance line is located. The reference layer is located in the via avoidance area around the via, and the reference layer intersects with the first impedance line and / or the second impedance line, so that the reference layer becomes the reference plane of the first impedance line and / or the second impedance line. The reference layer and the first impedance line and / or the second impedance line provide capacitive reactance at the via, realizing capacitive compensation at the via. In this way, the capacitive reactance at the via can be adjusted by setting the overlapping area (i.e., the facing area) and / or the spacing between the reference layer and the first impedance line and / or the second impedance line, so as to cancel the inductive mutation at the via. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0022] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of the layer change of the surface impedance line and the bottom impedance line of a printed circuit board in the related art;

[0024] Figure 2 It is a schematic structural diagram of the position of a via in a printed circuit board in the related art;

[0025] Figure 3 It is a simulation diagram of the capacitive mutation of the impedance line at the via provided by the embodiments of the present disclosure;

[0026] Figure 4 It is a simulation diagram of the inductive mutation of the impedance line at the via provided by the embodiments of the present disclosure;

[0027] Figure 5 It is a simulation diagram of controlling the capacitance and inductance of the via by adjusting the avoidance distance in the related art;

[0028] Figure 6 It is a schematic structural diagram of a printed circuit board provided by the embodiments of the present disclosure;

[0029] Figure 7 It is a schematic structural diagram of the position of a via in a printed circuit board provided by the embodiments of the present disclosure;

[0030] Figure 8 It is a simulation diagram of the impedance of the impedance line at the via provided by the embodiments of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to more clearly understand the above-mentioned objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0032] In the following description, many specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.

[0033] Currently, referring to Figure 1 and Figure 2 (taking the surface impedance line and the bottom impedance line as examples), the surface impedance line 1 (50 ohms) changes layers through a via and is electrically connected to the bottom impedance line 2 (50 ohms) on the bottom layer. After testing, the impedance at the via position of the impedance line will have a mutation. For example, it can exhibit a Figure 3 capacitive mutation as shown, or it can exhibit an Figure 4 inductive mutation as shown (specifically, it will vary according to the actual structure of the printed circuit board). In this regard, the capacitance and inductance of the via can be fine-tuned by adjusting the avoidance distance between the via and the surrounding copper foil to improve the above-mentioned impedance mutation problem. Referring to Figure 5 , curve a1 is for the case without a via, and the impedance line always approaches 50 ohms; curves b1, c1 and d1 are for the cases with avoidance distances of 0.35 mm, 0.4 mm and 0.6 mm respectively. It can be seen therefrom that as the avoidance distance increases, the impedance mutation at the via changes from a capacitive mutation to an inductive mutation. Therefore, the problem of impedance mutation at the via can be improved by adjusting the avoidance distance. However, due to process limitations, both the via size and the avoidance distance have minimum limitations. If the impedance line exhibits an inductive mutation at the via position and the via still exhibits an inductive characteristic when the avoidance distance reaches the process limit, the problem of the inductive mutation of the impedance line at the via position cannot be solved by adjusting the avoidance distance.

[0034] In view of the above technical problems, an embodiment of the present disclosure provides a printed circuit board. Figure 6 is a schematic structural diagram of a printed circuit board provided by an embodiment of the present disclosure; Figure 7 is a schematic structural diagram of the position of a via of a printed circuit board provided by an embodiment of the present disclosure. As shown in Figure 6 and Figure 7As shown, the printed circuit board includes a multi-layer circuit substrate (not shown in the figure), a first impedance line 10, a second impedance line 20 and a reference layer 30; the first impedance line 10 and the second impedance line 20 are respectively located on different layers of the circuit substrate, and are electrically connected through vias 40; the reference layer 30 is located in a via avoidance area 50, and is arranged between the layer where the first impedance line 10 is located and the layer where the second impedance line 20 is located, and in the stacking direction of the circuit substrate, the reference layer 30 overlaps with the first impedance line 10 and / or the second impedance line 20, wherein the reference layer 30 is connected to a reference potential, and the via avoidance area 50 is arranged around the via 40.

[0035] The technical solution disclosed in the present invention is applicable to the case where the impedance line cannot be changed in a perceptual mutation at the via position by reducing the avoidance distance of the via avoidance zone 50. In this case, the avoidance distance of the via avoidance zone 50 can be set as small as possible to improve the problem of the via presenting a perceptual mutation, and then the problem of the via presenting a perceptual mutation can be eliminated by setting the reference layer 30. Of course, in order to reduce the process difficulty of setting the avoidance distance, the via avoidance zone 50 can also be formed under an easy-to-implement process, and the problem of the via presenting a perceptual mutation can be eliminated only by adjusting the reference layer 30.

[0036] In the above technical solution, the circuit substrate can be a single-sided circuit board or a double-sided circuit board, and can include an insulating layer and a circuit layer. The length, line width and thickness of the first impedance line 10 and the second impedance line 20 can be set according to the actual impedance requirements. The reference layer 30 is connected to the reference potential and is a conductive layer, such as a metal layer. The reference potential is different from the potential of the first impedance line 10 and the second impedance line 20 when transmitting electrical signals. Usually, the reference potential is a reference ground. In the stacking direction of the circuit substrate, the reference layer 30 can overlap only with the first impedance line 10, the reference layer 30 can overlap only with the second impedance line 20, and the reference layer 30 can also overlap with both the first impedance line 10 and the second impedance line 20, depending on the actual situation, and the present disclosure does not limit this.

[0037] In the disclosed embodiment, since the reference layer 30 overlaps with the first impedance line 10 and / or the second impedance line 20 in the stacking direction of the circuit substrate, a capacitor is formed between the reference layer 30 and the first impedance line 10 at the via position, and / or a capacitor is formed between the reference layer 30 and the second impedance line 20, thereby increasing the capacitive reactance at the via and achieving capacitive compensation at the via. As is well known, the size of the capacitor is related to the facing area of ​​the capacitor plates and the distance between the plates. Therefore, the actual inductive mutation of the impedance line at the via position can be offset by capacitive compensation by setting the overlapping area of ​​the reference layer 30 and the first impedance line 10 and / or the second impedance line 20, and / or setting the distance between the reference layer 30 and the first impedance line 10 and / or the second impedance line 20.

[0038] In some embodiments, the multi-layer circuit board includes a top circuit board and a bottom circuit board. The first impedance line is located on the surface of the top circuit board away from the bottom circuit board, and the second impedance line is located on the surface of the bottom circuit board away from the top circuit board.

[0039] It should be noted that the first impedance line 10 and the second impedance line 20 in the embodiments of the present disclosure are not limited to being disposed on the top surface and the bottom surface of the printed circuit board. The first impedance line 10 and the second impedance line 20 can also be disposed on the inner layer circuit board.

[0040] Based on the above technical solutions, the impedance at the via is simulated and compared in the embodiments of the present disclosure. Refer to Figure 8 , curve a2 is for the case without vias, and the impedance line always approaches 50 ohms; curve b2 is for the case where the avoidance distance is 0.6 mm, and there is an inductive mutation at the via; curve c2 is for the case where a reference layer is provided in the via avoidance area. It can be clearly seen that the inductive mutation at the via is reduced, and the impedance is closer to 50 ohms.

[0041] For the printed circuit board provided by the embodiments of the present disclosure, by adding a reference layer between the layer where the first impedance line is located and the layer where the second impedance line is located, the reference layer is located in the via avoidance area around the via, and the reference layer intersects with the first impedance line and / or the second impedance line, so that the reference layer becomes the reference plane of the first impedance line and / or the second impedance line. The reference layer and the first impedance line and / or the second impedance line provide capacitive reactance at the via, realizing capacitive compensation at the via. In this way, the capacitive reactance at the via can be adjusted by setting the overlapping area (i.e., the facing area) and / or the spacing between the reference layer and the first impedance line and / or the second impedance line, so as to offset the inductive mutation at the via.

[0042] In some embodiments, the circuit board includes a ground layer, and the reference layer is electrically connected to the ground layer.

[0043] Specifically, the ground layer is located on the side of the circuit board opposite to the trace. The ground layer serves as the reference plane for the trace and is usually disposed over the entire surface. Exemplarily, the ground layer is a copper layer. In this embodiment, by electrically connecting the reference layer 30 to the ground layer of the circuit board, the reference layer 30 and the ground layer are at the same potential, that is, both are connected to the reference ground, so as to avoid providing power for the reference layer 30 additionally, reducing the cost and the wiring difficulty.

[0044] In some embodiments, the reference layer includes a first sub-reference layer and / or a second sub-reference layer; in the stacking direction of the circuit board, the first sub-reference layer intersects with the first impedance line, and / or the second sub-reference layer intersects with the second impedance line.

[0045] Such as Figure 6As shown, in this embodiment, corresponding sub-reference layers can be respectively set for the first impedance line 10 and the second impedance line 20. The first sub-reference layer 31 and the second sub-reference layer 32 can be located on the same layer or on different layers. Thus, the capacitance between the first sub-reference layer 31 and the first impedance line 10, and / or the capacitance between the second sub-reference layer 32 and the second impedance line 20 can be flexibly set to offset the inductive mutation at the via.

[0046] In some embodiments, the first sub-reference layer is on the same layer as the ground layer of the circuit board where the first impedance line is located, and / or the second sub-reference layer is on the same layer as the ground layer of the circuit board where the second impedance line is located.

[0047] Considering the influence of the thickness of the circuit board and the board spacing on the capacitance value, in this embodiment, by setting the first sub-reference layer on the same layer as the ground layer of the circuit board where the first impedance line is located, and / or the second sub-reference layer on the same layer as the ground layer of the circuit board where the second impedance line is located, the distance between the sub-reference layer and the corresponding impedance line is minimized, so that the capacitive compensation effect is the best.

[0048] In some embodiments, the first sub-reference layer extends along the length direction of the first impedance line, and the width of the first sub-reference layer is greater than or equal to the line width of the first impedance line; and / or, the second sub-reference layer extends along the length direction of the second impedance line, and the width of the second sub-reference layer is greater than or equal to the line width of the second impedance line.

[0049] In this embodiment, the first sub-reference layer can cover the part of the first impedance line located in the via avoidance area, and / or the second sub-reference layer can cover the part of the second impedance line located in the via avoidance area, so that the facing area between the sub-reference layer and the corresponding impedance line is the largest, in order to make the capacitive compensation effect the best by setting the distance between the sub-reference layer and the corresponding impedance line.

[0050] In some embodiments, the reference layer and the ground layer are made of the same material. This can facilitate the selection of materials. Optionally, the reference layer and the ground layer are both made of copper to save costs.

[0051] In some embodiments, the reference layer is an extension of the ground layer into the via avoidance area. In this way, the reference layer can be formed simultaneously when the ground layer is prepared, thus saving the process flow and reducing the process cost. Exemplarily, the ground layer is a copper layer. When preparing the ground layer, the reference layer can be left by etching the copper layer.

[0052] The embodiments of the present disclosure also provide an electronic device, including the printed circuit board provided by the embodiments of the present disclosure. This electronic device can be any electronic product having the above printed circuit board, and the present disclosure does not limit this.

[0053] The electronic device provided in this embodiment includes the printed circuit board provided in the embodiments of the present disclosure, which has the same and corresponding functions and beneficial effects, and will not be elaborated here.

[0054] The embodiments of the present disclosure also provide a vehicle, including the electronic device provided in the embodiments of the present disclosure.

[0055] The above are only specific implementation manners of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A printed circuit board, characterized in that, it includes a multi-layer circuit substrate, a first impedance line, a second impedance line and a reference layer; the first impedance line and the second impedance line are respectively located on the circuit substrates of different layers and are electrically connected through vias; the reference layer is located in a via avoidance area, is arranged between the layer where the first impedance line is located and the layer where the second impedance line is located, and in the stacking direction of the circuit substrate, the reference layer overlaps with the first impedance line and / or the second impedance line, wherein the reference layer is connected to a reference potential, and the via avoidance area is arranged around the via.

2. The printed circuit board according to claim 1, characterized in that, the circuit substrate includes a ground layer, and the reference layer is electrically connected to the ground layer.

3. The printed circuit board according to claim 2, characterized in that, the reference layer includes a first sub-reference layer and / or a second sub-reference layer; in the stacking direction of the circuit substrate, the first sub-reference layer overlaps with the first impedance line, and / or the second sub-reference layer overlaps with the second impedance line.

4. The printed circuit board according to claim 3, characterized in that, the first sub-reference layer and the ground layer of the circuit substrate where the first impedance line is located are on the same layer, and / or the second sub-reference layer and the ground layer of the circuit substrate where the second impedance line is located are on the same layer.

5. The printed circuit board according to claim 3, characterized in that, the first sub-reference layer extends along the length direction of the first impedance line, and the width of the first sub-reference layer is greater than or equal to the line width of the first impedance line; and / or, the second sub-reference layer extends along the length direction of the second impedance line, and the width of the second sub-reference layer is greater than or equal to the line width of the second impedance line.

6. The printed circuit board according to claim 2, characterized in that, the reference layer and the ground layer are made of the same material.

7. The printed circuit board according to claim 2, characterized in that, the reference layer is an extension part of the ground layer to the via avoidance area.

8. The printed circuit board according to claim 1, characterized in that, the multi-layer circuit substrate includes a top-layer circuit substrate and a bottom-layer circuit substrate, the first impedance line is located on the surface of the top-layer circuit substrate away from the bottom-layer circuit substrate, and the second impedance line is located on the surface of the bottom-layer circuit substrate away from the top-layer circuit substrate.

9. An electronic device, characterized in that, it includes the printed circuit board according to any one of claims 1 to 8.

10. A vehicle, characterized in that, it includes the electronic device according to claim 9.

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