Printed circuit board, electronic equipment and vehicle

Abstract

The invention relates to a printed circuit board, electronic equipment and a vehicle. The printed circuit board comprises a multilayer circuit substrate, a first impedance line, a second impedance line and a plurality of via holes. The first impedance line and the second impedance line are respectively located on different layers of circuit substrates and are electrically connected through the plurality of via holes, the via holes are used for communicating two adjacent layers of circuit substrates, and the two layers of circuit substrates communicated with different via holes are different; in the stacking direction of the multilayer circuit substrate, the plurality of via holes comprise a first via hole and a second via hole which are adjacent to each other, the first via hole and the second via hole are arranged in a staggered manner, and the first via hole and the second via hole are electrically connected through an extended wire. According to the technical scheme, the problem that the impedance line is in capacitive abrupt change at the via hole position can be solved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of printed circuit boards, and particularly to a printed circuit board, an electronic device, and a vehicle. Background Art

[0002] A printed circuit board (PCB) is manufactured using electronic printing technology. A printed circuit board is not only a carrier for providing a circuit but also a carrier for providing electrical signals. Printed circuit boards in certain communication, medical, and industrial control industries have certain requirements for impedance and need to design impedance lines.

[0003] The design expectation of impedance lines is to ensure that the impedance remains as consistent as possible at all positions of the impedance lines, that is, it is necessary to be as close as possible to the design target (such as 50 ohms) to avoid sudden changes in impedance up and down. When designing impedance lines on a multi-layer printed circuit board, there is a situation where the impedance line changes layers. At this time, it is necessary to punch holes in the printed circuit board, and the impedance line changes layers through vias. However, the impedance at the via position usually has a capacitive mutation. To address this problem, currently, the capacitive property of the via can be fine-tuned by adjusting the avoidance distance between the via and the surrounding copper cladding. For example, by increasing the avoidance distance, the impedance of the via can be adjusted towards the inductive direction, thereby improving the capacitive mutation of the via. However, adjusting the avoidance distance has limitations because when actually designing a circuit board (especially a high-density circuit board), the traces and ground vias around the via may be particularly dense, and there is no extra space to increase the avoidance distance. At this time, it is impossible to improve the capacitive mutation of the via by adjusting the avoidance distance. Therefore, there is an urgent need for a method to improve the problem of capacitive mutation of impedance lines at the via position. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a printed circuit board, an electronic device, and a vehicle to improve the problem of capacitive mutation of impedance lines at the via position.

[0005] The present disclosure provides a printed circuit board, including a multi-layer circuit substrate, a first impedance line, a second impedance line, and a plurality of vias;

[0006] The first impedance line and the second impedance line are respectively located on circuit substrates of different layers and are electrically connected through the plurality of vias. The vias are used to connect adjacent layers of the circuit substrates, and different vias connect different adjacent layers of the circuit substrates;

[0007] Along the stacking direction of the multi-layer circuit substrate, the plurality of vias include adjacent first vias and second vias, the first vias and the second vias are arranged in a staggered manner, and the first vias and the second vias are electrically connected through extended traces.

[0008] In the present disclosure, the extended trace is disposed on the common circuit board connected by the first via and the second via.

[0009] In the present disclosure, a hollowed-out area is formed on a target circuit board adjacent to the circuit board where the extended trace is located. In the stacking direction of the multi-layer circuit board, the hollowed-out area overlaps with the orthographic projection of the extended trace on any plane of the circuit board. Wherein, the target circuit board is different from the circuit board where the first impedance line is located, and the target circuit board is also different from the circuit board where the second impedance line is located.

[0010] In the present disclosure, the hollowed-out area coincides with the orthographic projection of the extended trace on any plane of the circuit board.

[0011] In the present disclosure, the printed circuit board further includes a first pad and a second pad. The first pad and the first impedance line are on the same layer, and the first impedance line is electrically connected to the via through the first pad. The second pad and the second impedance line are on the same layer, and the second impedance line is electrically connected to the via through the second pad;

[0012] The target via is disposed opposite to the target pad. In the stacking direction of the multi-layer circuit board, the outer edge of the via avoidance area corresponding to the target via overlaps with the outer edge of the target pad. Wherein, the target via is at least one of the plurality of vias, and the target pad includes the first pad and / or the second pad.

[0013] In the present disclosure, the first via is at least one, and the second via is at least one.

[0014] In the present disclosure, the plurality of vias includes the first via and two second vias adjacent to the first via.

[0015] In the present disclosure, the multi-layer circuit board includes a top-layer circuit board and a bottom-layer circuit board. The first impedance line is on the surface of the top-layer circuit board away from the bottom-layer circuit board, and the second impedance line is on the surface of the bottom-layer circuit board away from the top-layer circuit board.

[0016] The present disclosure also provides an electronic device, including the printed circuit board provided by the present disclosure.

[0017] The present disclosure also provides a vehicle, including the electronic device provided by the present disclosure.

[0018] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0019] In the technical solution provided by the embodiments of the present disclosure, the first impedance line and the second impedance line are electrically connected through a plurality of vias. Along the stacking direction of the multi-layer circuit board, the plurality of vias include adjacent first vias and second vias. The first vias and the second vias are arranged in a staggered manner, and the first vias and the second vias are electrically connected through an extended trace. In this way, by providing staggered vias among the plurality of vias for realizing the layer change of the first impedance line and the second impedance line, that is, at least one of the plurality of vias is arranged in a staggered manner with other vias, the adjacent first vias and second vias in the present disclosure are obtained, and the first vias and the second vias are electrically connected through an extended trace. Thus, by providing an extended trace to add trace inductance, inductance is added to the via with capacitive mutation, realizing inductive compensation of the via path. Furthermore, without adjusting the avoidance distance of the via, the problem that the impedance line shows capacitive mutation at the via position can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic structural diagram of the layer change of the surface impedance line and the bottom impedance line of a printed circuit board in the related art;

[0023] Figure 2 It is a schematic structural diagram of a via for realizing the layer change of an impedance line in a printed circuit board in the related art;

[0024] Figure 3 It is a simulation diagram of the capacitive mutation of the impedance line at the via provided by the embodiments of the present disclosure;

[0025] Figure 4 It is a simulation diagram of controlling the capacitance of a via by adjusting the avoidance distance in the related art;

[0026] Figure 5 It is a schematic structural diagram of a plurality of vias in a printed circuit board provided by the embodiments of the present disclosure;

[0027] Figure 6 It is a three-dimensional structural diagram of the layer change of the impedance line on a printed circuit board provided by the embodiments of the present disclosure;

[0028] Figure 7 For Figure 6 corresponding top view;

[0029] Figure 8 Another structural schematic diagram of multiple vias in a printed circuit board provided by an embodiment of the present disclosure;

[0030] Figure 9 A three-dimensional structural schematic diagram of impedance line layer change on a printed circuit board provided by an embodiment of the present disclosure;

[0031] Figure 10 is Figure 9 corresponding top view;

[0032] Figure 11 A three-dimensional structural schematic diagram of impedance line layer change on a printed circuit board provided by an embodiment of the present disclosure;

[0033] Figure 12 is Figure 11 corresponding top view;

[0034] Figure 13 A simulation diagram of the impedance of an impedance line at a via provided by an embodiment of the present disclosure;

[0035] Figure 14 A top view of a hollowed-out area provided by an embodiment of the present disclosure;

[0036] Figure 15 Another simulation diagram of the impedance of an impedance line at a via provided by an embodiment of the present disclosure. Detailed implementation manners

[0037] In order to more clearly understand the above-mentioned objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0038] Many specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all of the embodiments.

[0039] Currently, referring to Figure 1 and Figure 2(Taking the surface impedance line and the bottom impedance line as examples), in a multi-layer printed circuit board, the surface impedance line 1 (50 ohms) changes layers through vias and is electrically connected to the bottom impedance line 2 (50 ohms) on the bottom layer. Exemplarily, the multi-layer printed circuit board may include 10 circuit substrates L1, L2, L3, …… L9 and L10. There are multiple vias, and each via is used to connect adjacent circuit substrates. Through the vertical stacking of multiple vias, each circuit substrate is interconnected, so that the surface impedance line 1 and the bottom impedance line 2 are electrically connected through multiple vias. After testing, the impedance of the impedance line will have a mutation at the via position. For example, it can show a Figure 3 capacitive mutation as shown. In this regard, the capacitance of the via can be finely adjusted by adjusting the avoidance distance between the via and the surrounding copper foil to improve the above-mentioned capacitive mutation problem. Refer to Figure 4 . Curve m5 is for the case where the avoidance distance is not adjusted, curve m7 is for the case where the avoidance distance is adjusted on the circuit substrate where the surface impedance line is located, and curve m6 is for the case where the avoidance distance is adjusted on each circuit substrate. It can be seen from the figure that as the number of circuit substrates with the adjusted avoidance distance increases, the capacitive mutation of the via becomes smaller and smaller, achieving the effect of improving the capacitive mutation of the via. However, adjusting the avoidance distance has limitations because when actually designing a circuit board (especially a high-density circuit board), the traces and ground vias around the via may be particularly dense, and there is no extra space to increase the avoidance distance. At this time, it is impossible to improve the capacitive mutation of the via by adjusting the avoidance distance.

[0040] In view of the above technical problems, an embodiment of the present disclosure provides a printed circuit board. Figure 5 It is a schematic structural diagram of multiple vias in a printed circuit board provided by an embodiment of the present disclosure; Figure 6 It is a three-dimensional structural diagram of the impedance line layer change on a printed circuit board provided by an embodiment of the present disclosure; Figure 7 is Figure 6 corresponding top view. As Figure 5 , Figure 6 and Figure 7 shown, the printed circuit board includes multiple circuit substrates 10 ( Figure 5 schematically shows 10 circuit substrates), a first impedance line 20, a second impedance line 30, and multiple vias 40; the first impedance line 20 and the second impedance line 30 are respectively located on different circuit substrates 10 and are electrically connected through multiple vias 40. The vias 40 are used to connect adjacent circuit substrates 10, and the two circuit substrates 10 connected by different vias 40 are different; along the stacking direction of the multiple circuit substrates 10, the multiple vias 40 include adjacent first vias 41 and second vias 42, the first vias 41 and the second vias 42 are arranged in a staggered manner, and the first vias 41 and the second vias 42 are electrically connected through an extended trace 50.

[0041] The technical solution of the present disclosure is applicable to the situation where the via hole exhibits a capacitive mutation during impedance line layer change, and can be applied to high-density printed circuit boards. In the above technical solution, the circuit substrate 10 can be a single-sided circuit board or a double-sided circuit board, and the circuit substrates 10 are insulated from each other by an insulating layer. The lengths, line widths, and thicknesses of the first impedance line 10 and the second impedance line 20 can be set according to actual impedance requirements. The via hole 40 can be a high-density hole, which is usually formed by laser ablation of the substrate and then electroplated to form an interlayer connection.

[0042] In the embodiment of the present disclosure, the first via hole 41 and the second via hole 42 are arranged in a staggered manner, and the first via hole 41 and the second via hole 42 are electrically connected through an extended trace 50. Therefore, along the stacking direction of the multi-layer circuit substrate 10, the first via hole 41 and the second via hole 42 are completely staggered, that is, there is no overlap, and the first via hole 41 and the second via hole 42 are not directly electrically connected, but are electrically connected through the extended trace 50. In this way, by setting the extended trace 50 to add trace inductance, inductance is added to the capacitive mutation via hole, realizing inductive compensation of the via hole path, and thus being able to improve the problem that the impedance line exhibits a capacitive mutation at the via hole position without adjusting the avoidance distance of the via hole.

[0043] In some embodiments, the multi-layer circuit substrate 10 includes a top-layer circuit substrate and a bottom-layer circuit substrate. The first impedance line is located on the surface of the top-layer circuit substrate away from the bottom-layer circuit substrate, and the second impedance line is located on the surface of the bottom-layer circuit substrate away from the top-layer circuit substrate.

[0044] It should be noted that the first impedance line 10 and the second impedance line 20 in the embodiment of the present disclosure are not limited to being disposed on the top surface and the bottom surface of the printed circuit board. The first impedance line 10 and the second impedance line 20 can also be disposed on an inner-layer circuit substrate (such as L2-L9).

[0045] In some embodiments, the first via hole is at least one, and the second via hole is at least one. Exemplarily, referring to Figure 5 , the multiple via holes 40 include two first via holes 41 and one second via hole 42. In the figure, the via holes connecting the circuit substrates L3 and L4 and the via holes connecting the circuit substrates L5 and L6 are the first via holes 41, and the via hole connecting the circuit substrates L4 and L5 is the second via hole 42. At this time, two extended traces can be set to add trace inductance, thereby adjusting the capacitance of the via hole. Additionally, referring to Figure 8, a plurality of vias 40 include a first via 41 and a second via 42. The via connecting circuit boards L3 and L4 is the first via 41, and the via connecting circuit boards L4 and L5 is the second via 42. At this time, only one extended trace can be set to add trace inductance, thereby adjusting the capacitance of the via. It can be understood that which via to be misaligned can be determined according to the routing space of the circuit board. For example, the routing space of circuit board L4 is sufficient to set the extended trace, and at this time, the via connecting circuit boards L4 and L5 can be misaligned. In addition, the specific number of the first vias and the second vias can be jointly determined by the routing space of the circuit board and the inductance to be increased. For example, the longer the length of the extended trace that can be set by the routing space, the less inductance needs to be increased, and the number of the first vias and the second vias can be set less, which depends on the actual situation.

[0046] In some embodiments, the plurality of vias include a first via and two second vias adjacent to the first via. In this way, two extended traces can be set by misaligning one via, which is convenient for the design and preparation of the printed circuit board.

[0047] It should be noted that the increased inductance mainly depends on the length of the extended trace. The longer the extended trace, the more inductance is increased. Based on this, the embodiments of the present disclosure also provide Figure 9 (or Figure 10 ) and Figure 11 (or Figure 12 ) the structures of extended traces with different lengths shown, where Figure 9 the length of the extended trace shown is greater than Figure 6 the length of the extended trace shown, Figure 11 the length of the extended trace shown is greater than Figure 9 the length of the extended trace shown. Based on the above technical solutions, the embodiments of the present disclosure perform simulation comparison on the impedance at the via. Referring to Figure 13 , curve m0 is for the case where the via is not misaligned and the avoidance distance is not adjusted, curve m1 is for the case of the structure shown in Figure 6 , curve m2 is for the case of the structure shown in Figure 9 , curve m3 is for the case of the structure shown in Figure 11As shown in the structure, it can be clearly seen that as the extension of the routing increases, the capacitive mutation of the via gradually decreases. In addition, curve m4 is for the case where the via is misaligned but the two misaligned vias are directly electrically connected. It can be seen from the figure that its capacitive mutation is greater than the case where the via is not misaligned. This is because, although the via is misaligned, it is still directly electrically connected, which is equivalent to the via path not being extended. On the contrary, the misalignment of the via increases the area directly facing the upper and lower vias, thereby increasing the capacitance, resulting in further improvement in capacitance. In addition, if too many extended routings are set, and / or the length of the extended routing is too long, it will lead to too much increased inductance, which will cause the via to have a problem of inductive mutation. Therefore, the number and length of the extended routing need to be appropriately adjusted according to the actual capacitive mutation of the via.

[0048] In the printed circuit board provided by the embodiment of the present disclosure, the first impedance line and the second impedance line are electrically connected through a plurality of vias. Along the stacking direction of the multi-layer circuit substrate, the plurality of vias include adjacent first vias and second vias, the first vias and the second vias are staggered, and the first vias and the second vias are electrically connected through an extended trace. In this way, by setting staggered holes in the plurality of vias for realizing the layer exchange of the first impedance line and the second impedance line, that is, at least one via in the plurality of vias is staggered with other vias, the adjacent first vias and the second vias of the present disclosure are obtained, and the first vias and the second vias are electrically connected by extending the trace, thereby, by setting the extended trace to add trace inductance, inductance is added to the vias with capacitive mutation, and inductance compensation of the via path is realized, and then the problem of capacitive mutation of the impedance line at the via position can be improved without adjusting the avoidance distance of the via.

[0049] In some embodiments, the extended trace is arranged on a common circuit substrate connected to the first via and the second via. Usually, a whole copper layer (i.e., a ground layer) is plated on the side of the circuit substrate opposite to the circuit layer (the impedance line is arranged on the circuit layer). On a circuit substrate provided with an impedance line (such as the first impedance line and the second impedance line of the present disclosure), the copper layer serves as a reference plane for the impedance line. If an extended trace is arranged on the reference plane, the complete reference of the impedance line will be broken, thereby affecting the impedance of the impedance line. Therefore, the embodiment of the present disclosure arranges the extended trace on the common circuit substrate connected to the first via and the second via, so that the extended trace is located on the circuit substrate between the first impedance line and the second impedance line, thereby avoiding the extended trace being located on the copper layer of the circuit substrate where the first impedance line and the second impedance line are located, thereby ensuring the integrity of the reference plane of the first impedance line and the second impedance line, and ensuring that the impedance of the entire impedance line approaches the target impedance.

[0050] In some embodiments, a hollowed-out area is formed on a target circuit board adjacent to the circuit board where the extended trace is located. In the stacking direction of the multi-layer circuit board, the hollowed-out area overlaps with the orthographic projection of the extended trace on any circuit board plane. Here, the target circuit board is different from the circuit board where the first impedance line is located and is also different from the circuit board where the second impedance line is located.

[0051] As part of the impedance line layer change, the extended trace should also approach the target impedance. If the impedance of the extended trace is corrected by adjusting its line width, it will inevitably change the trace inductance, resulting in a change in the overall impedance on the via path. At this time, it is necessary to consider both the length and line width of the extended trace to determine the compensated inductance, which increases the design difficulty. Therefore, in the embodiments of the present disclosure, by hollowing out a partial area of the circuit board adjacent to the circuit board where the extended trace is located, the formed hollowed-out area overlaps with the extended trace, increasing the height of the extended trace to the reference plane, thereby adjusting the impedance of the extended trace. In this way, it can not only ensure that the impedance of the extended trace approaches the target impedance but also does not affect the overall impedance on the via path. Optionally, Figure 14 , the orthographic projection of the hollowed-out area 60 on any circuit board plane coincides with the extended trace. In addition, based on the above technical solution, the embodiments of the present disclosure perform a simulation comparison on the impedance at the via. Figure 15 , curve m8 is for the case where the vias are not misaligned and the avoidance distance is not adjusted, curve m9 is for the case where the vias are misaligned and an extended trace is added, and curve m10 is for the case where the vias are misaligned, an extended trace is added, and a hollowed-out area is provided. As can be seen from the figure, the technical solution provided by the embodiments of the present disclosure, which misaligns the vias and adds an extended trace, can effectively improve the problem of capacitive mutation at the vias.

[0052] In some embodiments, the printed circuit board further includes a first pad and a second pad. The first pad and the first impedance line are on the same layer, and the first impedance line is electrically connected to the via through the first pad. The second pad and the second impedance line are on the same layer, and the second impedance line is electrically connected to the via through the second pad; the target via is disposed opposite to the target pad. In the stacking direction of the multi-layer circuit board, the outer edge of the via avoidance area corresponding to the target via overlaps with the outer edge of the target pad, where the target via is at least one of the multiple vias, and the target pad includes the first pad and / or the second pad. In this way, when there is still space for adjusting the avoidance distance in the wiring of at least one circuit board, by misaligning the vias and adding an extended trace, combined with adjusting the avoidance distance, the capacitive mutation at the vias can be reduced.

[0053] Embodiments of the present disclosure also provide an electronic device, including a printed circuit board provided by the embodiments of the present disclosure. The electronic device may be any electronic product having the above printed circuit board, and the present disclosure does not limit this.

[0054] The electronic device provided by this embodiment includes the printed circuit board provided by the embodiments of the present disclosure, and has the same and corresponding functions and beneficial effects, which will not be elaborated here.

[0055] Embodiments of the present disclosure also provide a vehicle, including the electronic device provided by the embodiments of the present disclosure.

[0056] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A printed circuit board, characterized in that, it includes a multi-layer circuit substrate, a first impedance line, a second impedance line and a plurality of vias; the first impedance line and the second impedance line are respectively located on the circuit substrates of different layers, and are electrically connected through the plurality of vias, the vias are used to connect the adjacent two layers of the circuit substrates, and the two layers of the circuit substrates connected by different vias are different; along the stacking direction of the multi-layer circuit substrate, the plurality of vias include adjacent first vias and second vias, the first vias and the second vias are arranged in a staggered manner, and the first vias and the second vias are electrically connected through an extended trace.

2. The printed circuit board according to claim 1, characterized in that, the extended trace is disposed on the common circuit substrate connected by the first via and the second via.

3. The printed circuit board according to claim 2, characterized in that, a hollow area is formed on the target circuit substrate adjacent to the circuit substrate where the extended trace is located. In the stacking direction of the multi-layer circuit substrate, the hollow area overlaps with the orthographic projection of the extended trace on any plane of the circuit substrate. Wherein, the target circuit substrate is different from the circuit substrate where the first impedance line is located, and the target circuit substrate is also different from the circuit substrate where the second impedance line is located.

4. The printed circuit board according to claim 3, characterized in that, the orthographic projection of the hollow area and the extended trace on any plane of the circuit substrate coincides.

5. The printed circuit board according to claim 1, characterized in that, the printed circuit board further includes a first pad and a second pad. The first pad and the first impedance line are on the same layer, and the first impedance line is electrically connected to the via through the first pad. The second pad and the second impedance line are on the same layer, and the second impedance line is electrically connected to the via through the second pad; the target via and the target pad are arranged opposite to each other. In the stacking direction of the multi-layer circuit substrate, the outer edge of the via avoidance area corresponding to the target via overlaps with the outer edge of the target pad. Wherein, the target via is at least one of the plurality of vias, and the target pad includes the first pad and / or the second pad.

6. The printed circuit board according to claim 1, characterized in that, the first via is at least one, and the second via is at least one.

7. The printed circuit board according to claim 6, characterized in that, the plurality of vias include the first via and two second vias adjacent to the first via.

8. The printed circuit board according to claim 1, characterized in that, the multi-layer circuit substrate includes a top-layer circuit substrate and a bottom-layer circuit substrate. The first impedance line is located on the surface of the top-layer circuit substrate away from the bottom-layer circuit substrate, and the second impedance line is located on the surface of the bottom-layer circuit substrate away from the top-layer circuit substrate.

9. An electronic device, characterized in that, it includes the printed circuit board according to any one of claims 1 to 8.

10. A vehicle, characterized in that, Comprising the electronic device as claimed in claim 9.

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