Wiring circuit board and method for manufacturing wiring circuit board

Abstract

The invention provides a printed circuit board and a method for manufacturing the printed circuit board. A wired circuit board (1) is provided with: a first insulating layer (12); a conductor pattern (13) that is positioned on the first insulating layer (12) and that has a terminal (131C); and a dummy conductor pattern (14A) disposed on the first insulating layer (12) so as to be separated from the conductor pattern (13). The dummy conductor pattern (14A) is disposed in a circular region (R3) having a diameter of 3.5 mm in which the terminal (131C) is located at the center in a plane direction, which is a direction in which the surface of the first insulating layer (12) extends. The conductor pattern (13) is formed together with the dummy conductor pattern (14A).

Description

Technical Field

[0001] The present invention relates to a wiring circuit board and a method for manufacturing the wiring circuit board. Background Art

[0002] Conventionally, as a wiring circuit board, a wiring circuit board including an insulating layer and a conductor pattern formed on the insulating layer is known.

[0003] In addition, as a method for manufacturing such a wiring circuit board, a method is known in which, in a process of forming a conductor pattern by electroplating, a conductor pattern is formed together with a dummy conductor pattern formed outside the wiring circuit board, thereby achieving uniformization of the thickness of the conductor pattern (for example, refer to Patent Document 1 below).

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-094222 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In the wiring circuit board described in Patent Document 1, for terminals connected to electronic components, it is desired to further improve the dimensional accuracy of the thickness.

[0009] The present invention provides a wiring circuit board and a method for manufacturing the wiring circuit board capable of improving the dimensional accuracy of the thickness of the terminals.

[0010] Solutions to the Problems

[0011] The present invention [1] includes a wiring circuit board having: an insulating layer; a conductor pattern located on the insulating layer and having terminals; and a dummy conductor pattern disposed separately from the conductor pattern on the insulating layer, the dummy conductor pattern being disposed within a circular region having a diameter of 3.5 mm with the terminals located at the center in a plane direction, which is a direction in which the dummy conductor pattern extends on the surface of the insulating layer.

[0012] According to such a structure, the wiring circuit board includes a dummy conductor pattern.

[0013] Therefore, compared with a structure in which a dummy conductor pattern is formed outside the wiring circuit board (for example, a frame of a wiring circuit board assembly sheet), the dummy conductor pattern is disposed closer to the conductor pattern.

[0014] Moreover, the dummy conductor pattern is disposed within a circular region having a diameter of 3.5 mm with the terminals located at the center.

[0015] Therefore, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0016] Based on the wiring circuit board described in [1] above, in the present invention [2], the sum of the area of the dummy conductor pattern and the area of the terminal within the circular region is 5% or more of the area of the circular region.

[0017] According to such a structure, the dummy conductor pattern is arranged such that the terminal and the dummy conductor pattern occupy an area of 5% or more of the circular region.

[0018] Thereby, it is possible to suppress the deviation of the thickness of the terminal from the design value.

[0019] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0020] Based on the wiring circuit board described in [1] above, in the present invention [3], the terminal has: a first conductor layer having a first thickness; and a second conductor layer located on the first conductor layer and having a second thickness different from the first thickness. The dummy conductor pattern has the first thickness, and the sum of the area of the dummy conductor pattern and the area of the first conductor layer within the circular region is 5% or more of the area of the circular region.

[0021] According to such a structure, the dummy conductor pattern is arranged such that the first conductor layer of the terminal and the dummy conductor pattern occupy an area of 5% or more of the circular region.

[0022] Thereby, it is possible to suppress the deviation of the thickness of the first conductor layer of the terminal from the design value.

[0023] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0024] Based on the wiring circuit board described in [1] above, in the present invention [4], the terminal has: a first conductor layer having a first thickness; and a second conductor layer located on the first conductor layer and having a second thickness different from the first thickness. The dummy conductor pattern has the second thickness, and the sum of the area of the dummy conductor pattern and the area of the second conductor layer within the circular region is 5% or more of the area of the circular region.

[0025] According to such a structure, the dummy conductor pattern is arranged such that the second conductor layer of the terminal and the dummy conductor pattern occupy an area of 5% or more of the circular region.

[0026] Thereby, it is possible to suppress the deviation of the thickness of the second conductor layer of the terminal from the design value.

[0027] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0028] Based on the wiring circuit board described in the above [1], in the present invention [5], the terminal has: a first conductor layer having a first thickness; and a second conductor layer located on the first conductor layer and having a second thickness different from the first thickness. The dummy conductor pattern has: a dummy first conductor layer having the first thickness; and a dummy second conductor layer located on the dummy first conductor layer and having the second thickness. The sum of the area of the dummy first conductor layer and the area of the first conductor layer within the circular region is 5% or more of the area of the circular region, and the sum of the area of the dummy second conductor layer and the area of the second conductor layer within the circular region is 5% or more of the area of the circular region.

[0029] According to such a structure, the dummy first conductor layer is arranged such that the second conductor layer of the terminal and the dummy first conductor layer occupy an area of 5% or more of the circular region.

[0030] Thereby, it is possible to suppress the deviation of the thickness of the first conductor layer of the terminal from the design value.

[0031] Moreover, the dummy second conductor layer is arranged such that the second conductor layer of the terminal and the dummy second conductor layer occupy an area of 5% or more of the circular region.

[0032] Thereby, it is possible to suppress the deviation of the thickness of the second conductor layer of the terminal from the design value.

[0033] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0034] The present invention [6] includes a method for manufacturing a wiring circuit board, which is the method for manufacturing the wiring circuit board described in the above [1] or [2]. In this method for manufacturing a wiring circuit board, it includes: an insulating layer forming step in which the insulating layer is formed; and a pattern forming step in which the conductor pattern is formed on the insulating layer, and the dummy conductor pattern is formed together with the conductor pattern.

[0035] According to such a method, in the pattern forming step, it is possible to suppress the deviation of the thickness of the terminal from the design value.

[0036] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0037] The present invention [7] includes a method for manufacturing a wiring circuit board, which is the method for manufacturing a wiring circuit board described in the above [3]. Among them, the method for manufacturing this wiring circuit board includes: an insulating layer forming step in which the insulating layer is formed; a first pattern forming step in which the first conductor layer is formed on the insulating layer, and the dummy conductor pattern is formed together with the first conductor layer; and a second pattern forming step in which the second conductor layer is formed on the first conductor layer.

[0038] According to such a method, in the first pattern forming step, the deviation of the thickness of the first conductor layer from the design value can be suppressed.

[0039] As a result, the dimensional accuracy of the thickness of the terminal can be improved.

[0040] The present invention [8] includes a method for manufacturing a wiring circuit board, which is the method for manufacturing a wiring circuit board described in the above [4]. Among them, the method for manufacturing this wiring circuit board includes: an insulating layer forming step in which the insulating layer is formed; a first pattern forming step in which the first conductor layer is formed on the insulating layer; and a second pattern forming step in which the second conductor layer is formed on the first conductor layer, and the dummy conductor pattern is formed together with the second conductor layer.

[0041] According to such a method, in the second pattern forming step, the deviation of the thickness of the second conductor layer from the design value can be suppressed.

[0042] As a result, the dimensional accuracy of the thickness of the terminal can be improved.

[0043] The present invention [9] includes a method for manufacturing a wiring circuit board, which is the method for manufacturing a wiring circuit board described in the above [5]. Among them, the method for manufacturing this wiring circuit board includes: an insulating layer forming step in which the insulating layer is formed; a first pattern forming step in which the first conductor layer is formed on the insulating layer, and the dummy first conductor layer is formed together with the first conductor layer; and a second pattern forming step in which the second conductor layer is formed on the first conductor layer, and the dummy second conductor layer is formed together with the second conductor layer.

[0044] According to such a method, in the first pattern forming step, the deviation of the thickness of the first conductor layer from the design value can be suppressed.

[0045] Moreover, in the second pattern forming step, the deviation of the thickness of the second conductor layer from the design value can also be suppressed.

[0046] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal.

[0047] Effects of the Invention

[0048] According to the wiring circuit board and the method for manufacturing the wiring circuit board of the present invention, it is possible to improve the dimensional accuracy of the thickness of the terminal. Description of the Drawings

[0049] Figure 1 is a top view of a wiring circuit board according to an embodiment of the present invention.

[0050] Figure 2 is Figure 1 a cross-sectional view taken along line A-A of the wiring circuit board shown.

[0051] Figures 3A to 3D is for explaining Figure 1 a process chart of the method for manufacturing the wiring circuit board shown, Figure 3A indicating the first insulating layer forming process, Figure 3B indicating the first pattern forming process, Figure 3C indicating the second pattern forming process, Figure 3D indicating the etching process.

[0052] Figure 4 is an explanatory diagram for explaining the modification example (1).

[0053] Figure 5 is an explanatory diagram for explaining the modification example (2).

[0054] Figure 6 is an explanatory diagram for explaining the modification example (3).

[0055] Figure 7 is an explanatory diagram for explaining the modification example (4).

[0056] Figure 8 is an explanatory diagram for explaining the modification example (5).

[0057] Explanation of Reference Numerals

[0058] 1, wiring circuit board; 12, first insulating layer; 13, conductor pattern; 131C, terminal; 1311, first conductor layer; 1312, second conductor layer; 14A, dummy conductor pattern; 141, dummy first conductor layer; 142, dummy second conductor layer; R3, circular region. Detailed Description of the Invention

[0059] 1. Wiring Circuit Board

[0060] As Figure 1As shown, the wiring circuit board 1 extends in the first direction and the second direction. In the present embodiment, the wiring circuit board 1 has a substantially rectangular shape. In addition, the shape of the wiring circuit board 1 is not limited. The wiring circuit board 1 can connect the first electronic component and the second electronic component.

[0061] As Figure 2 shown, in the present embodiment, the wiring circuit board 1 has a metal support layer 11, a first insulating layer 12 as an example of an insulating layer, a conductor pattern 13, a plurality of dummy conductor patterns 14A, 14B, and a second insulating layer 15.

[0062] (1) Support layer

[0063] The support layer 11 supports the first insulating layer 12, the conductor pattern 13, and the second insulating layer 15. As the material of the support layer 11, for example, stainless steel and copper alloy can be cited.

[0064] (2) First insulating layer

[0065] The first insulating layer 12 is located on the support layer 11 in the thickness direction of the wiring circuit board 1. The thickness direction is orthogonal to the first direction and the second direction. The first insulating layer extends in the first direction and the second direction. That is, the first direction and the second direction are the directions in which the surface of the first insulating layer 12 extends, and are an example of a plane direction. The first insulating layer 12 is located between the support layer 11 and the conductor pattern 13 in the thickness direction. The first insulating layer 12 insulates the support layer 11 from the conductor pattern 13. The first insulating layer 12 is made of resin. As the resin, for example, polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester can be cited.

[0066] (3) Conductor pattern

[0067] As Figure 2 shown, the conductor pattern 13 is located on the first insulating layer 12 in the thickness direction. The conductor pattern 13 is located on the side opposite to the support layer 11 with respect to the first insulating layer 12 in the thickness direction. The conductor pattern 13 is made of metal. As the metal, for example, copper, silver, gold, iron, aluminum, chromium, and their alloys can be cited. As the metal, copper is preferably selected.

[0068] As Figure 1 shown, the conductor pattern 13 has a plurality of terminals 131A, 131B, 131C, 131D, 131E, a plurality of terminals 132A, 132B, 132C, 132D, 132E, and a plurality of wirings 133A, 133B, 133C, 133D, 133E.

[0069] (3-1) Terminals 131A, 131B, 131C, 131D, 131E

[0070] Terminals 131A, 131B, 131C, 131D, and 131E are connected to the first electronic component. Terminals 131A, 131B, 131C, 131D, and 131E are located at one end of the wiring circuit board 1 in the second direction. Terminals 131A, 131B, 131C, 131D, and 131E are arranged in the first direction. Terminals 131A, 131B, 131C, 131D, and 131E are arranged in the order of terminal 131A, terminal 131B, terminal 131C, terminal 131D, and terminal 131E from one end of the wiring circuit board 1 toward the other end in the first direction. Terminals 131A, 131B, 131C, 131D, and 131E each have a square pad shape.

[0071] Terminals 131A, 131B, 131C, 131D, and 131E are each spaced apart from each other in the first direction. The interval between terminal 131B and terminal 131C and the interval between terminal 131C and terminal 131D are longer than the interval between terminal 131A and terminal 131B and the interval between terminal 131D and terminal 131E.

[0072] Terminal 131A is located at the center of region R1. Region R1 is a circle with a diameter of 3.5 mm. The center of region R1 coincides with the center C1 of terminal 131A. Center C1 is located at the center of terminal 131A in the first direction and is the center of terminal 131A in the second direction. Terminal 131B is located within region R1. Terminals 131C, 131D, and 131E are located outside region R1.

[0073] Terminal 131B is located at the center of region R2. Region R2 is a circle with a diameter of 3.5 mm. The center of region R2 coincides with the center C2 of terminal 131B. Center C2 is located at the center of terminal 131B in the first direction and is the center of terminal 131B in the second direction. Terminal 131A is located within region R2. Terminals 131C, 131D, and 131E are located outside region R2.

[0074] Terminal 131C is located at the center of region R3. Region R3 is a circle with a diameter of 3.5 mm. The center of region R3 coincides with the center C3 of terminal 131C. Center C3 is located at the center of terminal 131C in the first direction and is the center of terminal 131C in the second direction. Terminals 131A, 131B, 131D, and 131E are located outside region R3.

[0075] Terminal 131D is located at the center of region R4. Region R4 is a circle with a diameter of 3.5 mm. The center of region R4 coincides with the center C4 of terminal 131D. Center C4 is located at the center in the first direction of terminal 131D and is also at the center in the second direction of terminal 131D. Terminal 131E is located within region R4. Terminals 131A, 131B, and 131C are located outside region R4.

[0076] Terminal 131E is located at the center of region R5. Region R5 is a circle with a diameter of 3.5 mm. The center of region R5 coincides with the center C5 of terminal 131E. Center C5 is located at the center in the first direction of terminal 131E and is also at the center in the second direction of terminal 131E. Terminal 131D is located within region R5. Terminals 131A, 131B, and 131C are located outside region R5.

[0077] As Figure 2 shown, each of terminals 131A, 131B, 131C, 131D, and 131E has a first conductor layer 1311 and a second conductor layer 1312. In the present embodiment, each of terminals 131A, 131B, 131C, 131D, and 131E is composed of a first conductor layer 1311 and a second conductor layer 1312.

[0078] The first conductor layer 1311 is located on the first insulating layer 12 in the thickness direction. The first conductor layer 1311 has a first thickness.

[0079] The second conductor layer 1312 is located on the first conductor layer 1311 in the thickness direction. The second conductor layer 1312 has a second thickness. The second thickness is different from the first thickness. In the present embodiment, the second thickness is thicker than the first thickness.

[0080] The difference between the measured value and the designed value of the thickness of each of terminals 131A, 131B, 131C, 131D, and 131E is, for example, 10% or less with respect to the designed value, preferably 5% or less. There is no limit to the lower limit of the difference between the measured value and the designed value of the thickness of each of terminals 131A, 131B, 131C, 131D, and 131E. The difference between the measured value and the designed value of the thickness of each of terminals 131A, 131B, 131C, 131D, and 131E may also be 0%.

[0081] (3-2) Terminals 132A, 132B, 132C, 132D, 132E

[0082] As Figure 1As shown, terminals 132A, 132B, 132C, 132D, and 132E are located at the other end of the wiring circuit board 1 in the second direction. Terminals 132A, 132B, 132C, 132D, and 132E are connected to the second electronic component. In the present embodiment, terminals 132A, 132B, 132C, 132D, and 132E are arranged in the first direction. In addition, terminals 132A, 132B, 132C, 132D, and 132E may also be arranged in a direction different from the direction in which terminals 131A, 131B, 131C, 131D, and 131E are arranged. Each of terminals 132A, 132B, 132C, 132D, and 132E has a square pad shape. Terminals 132A, 132B, 132C, 132D, and 132E are spaced apart from each other in the first direction.

[0083] (3-3) wirings 133A, 133B, 133C, 133D, 133E

[0084] Wiring 133A electrically connects terminal 131A and terminal 132A. One end of wiring 133A is connected to terminal 131A. The other end of wiring 133A is connected to terminal 132A. A part of wiring 133A is located in regions R1 and R2.

[0085] Wiring 133B electrically connects terminal 131B and terminal 132B. One end of wiring 133B is connected to terminal 131B. The other end of wiring 133B is connected to terminal 132B. A part of wiring 133B is located in regions R1 and R2.

[0086] Wiring 133C electrically connects terminal 131C and terminal 132C. One end of wiring 133C is connected to terminal 131C. The other end of wiring 133C is connected to terminal 132C. A part of wiring 133C is located in region R3.

[0087] Wiring 133D electrically connects terminal 131D and terminal 132D. One end of wiring 133D is connected to terminal 131D. The other end of wiring 133D is connected to terminal 132D. A part of wiring 133D is located in regions R4 and R5.

[0088] Wiring 133E electrically connects terminal 131E and terminal 132E. One end of wiring 133E is connected to terminal 131E. The other end of wiring 133E is connected to terminal 132E. A part of wiring 133E is located in regions R4 and R5.

[0089] (4) dummy conductor pattern

[0090] The dummy conductor pattern 14A is disposed close to the terminal 131C. The dummy conductor pattern 14A is located within the region R3. A part of the dummy conductor pattern 14A may also be located outside the region R3. The dummy conductor pattern 14A is disposed separately from the conductor pattern 13. The dummy conductor pattern 14A is not used for connection to an electronic component. In other words, the dummy conductor pattern 14A is not connected to either the first electronic component or the second electronic component. The dummy conductor pattern 14A does not have a wiring. In the present embodiment, the dummy conductor pattern 14A extends in the second direction. The shape of the dummy conductor pattern 14A is not limited.

[0091] As Figure 2 shown, the dummy conductor pattern 14A is located on the first insulating layer 12. The dummy conductor pattern 14A has a dummy first conductor layer 141 and a dummy second conductor layer 142.

[0092] The dummy first conductor layer 141 is located on the first insulating layer 12 in the thickness direction. The dummy first conductor layer 141 has a first thickness.

[0093] The dummy second conductor layer 142 is located on the dummy first conductor layer 141 in the thickness direction. The dummy second conductor layer 142 has a second thickness.

[0094] As Figure 1 shown, "the sum of the area A1 of the dummy first conductor layer 141 within the region R3 and the area A2 of the first conductor layer 1311 of the terminal 131C" is, for example, 5% or more, preferably 10% or more, more preferably 25% or more of the area A0 of the region R3.

[0095] "The sum of the area A1 of the dummy first conductor layer 141 within the region R3 and the area A2 of the first conductor layer 1311 of the terminal 131C" is, for example, less than 100%, preferably 95% or less, more preferably 70% or less, and further preferably 50% or less of the area A0 of the region R3.

[0096] In addition, "the sum of the area A1 of the dummy first conductor layer 141 within the region R3, the area A2 of the first conductor layer 1311 of the terminal 131C, and the area A3 of the wiring 133C within the region R3" is, for example, 5% or more, preferably 10% or more, more preferably 25% or more of the area A0 of the region R3.

[0097] In addition, "the sum of the area A1 of the dummy first conductor layer 141 within the region R3, the area A2 of the first conductor layer 1311 of the terminal 131C, and the area A3 of the wiring 133C within the region R3" is, for example, less than 100%, preferably 95% or less, more preferably 70% or less, and further preferably 50% or less of the area A0 of the region R3.

[0098] The sum of the area A11 of the dummy second conductor layer 142 in region R3 and the area A12 of the second conductor layer 1312 of the terminal 131C is, for example, 5% or more, preferably 10% or more, and more preferably 25% or more of the area of region R3.

[0099] The sum of the area A11 of the dummy second conductor layer 142 in region R3 and the area A12 of the second conductor layer 1312 of the terminal 131C is, for example, less than 100%, preferably 95% or less, more preferably 70% or less, and further preferably 50% or less of the area of region R3.

[0100] In addition, the sum of the area of the first conductor layer 1311 of the terminal 131A and the area of the first conductor layer 1311 of the terminal 131B is, for example, 5% or more, preferably 10% or more, and more preferably 25% or more of the area of region R1.

[0101] Furthermore, the sum of the area of the first conductor layer 1311 of the terminal 131A and the area of the first conductor layer 1311 of the terminal 131B is, for example, less than 100%, preferably 95% or less, more preferably 70% or less, and further preferably 50% or less of the area of region R1.

[0102] The difference between the percentage of the sum of the area A11 of the dummy second conductor layer 142 in region R3 and the area A12 of the second conductor layer 1312 of the terminal 131C with respect to the area of region R3 and the percentage of the sum of the area of the first conductor layer 1311 of the terminal 131A and the area of the first conductor layer 1311 of the terminal 131B with respect to the area of region R1 is, for example, 50% or less, preferably 30% or less.

[0103] There is no limit to the lower limit of the difference between the percentage of the sum of the area A11 of the dummy second conductor layer 142 in region R3 and the area A12 of the second conductor layer 1312 of the terminal 131C with respect to the area of region R3 and the percentage of the sum of the area of the first conductor layer 1311 of the terminal 131A and the area of the first conductor layer 1311 of the terminal 131B in region R1 with respect to the area of region R1. The difference between the percentage of the sum of the area A11 of the dummy second conductor layer 142 in region R3 and the area A12 of the second conductor layer 1312 of the terminal 131C with respect to the area of region R3 and the percentage of the sum of the area of the first conductor layer 1311 of the terminal 131A and the area of the first conductor layer 1311 of the terminal 131B in region R1 with respect to the area of region R1 can also be 0.

[0104] The dummy conductor pattern 14B is disposed close to the terminal 132C. The description of the dummy conductor pattern 14B is the same as that of the dummy conductor pattern 14A. Therefore, the description of the dummy conductor pattern 14B is omitted.

[0105] (5) Second insulating layer

[0106] As Figure 1 shown, the second insulating layer 15 covers the wirings 133A, 133B, 133C, 133D, and 133E. The second insulating layer 15 is located above the first insulating layer 12 in the thickness direction. In addition, the second insulating layer 15 does not cover the terminals 131A, 131B, 131C, 131D, 131E and the terminals 132A, 132B, 132C, 132D, 132E. The second insulating layer 15 is made of resin. Examples of the resin include polyimide, maleimide, epoxy resin, polybenzoxazole, and polyester.

[0107] 2. Manufacturing method of the wiring circuit board

[0108] Next, the manufacturing method of the wiring circuit board 1 will be described.

[0109] The manufacturing method of the wiring circuit board 1 includes a first insulating layer forming step (refer to Figure 3A ), a pattern forming step (refer to Figure 3B , Figure 3C ), a second insulating layer forming step, and an etching step (refer to Figure 3D ).

[0110] (1) First insulating layer forming step

[0111] As Figure 3A shown, in the first insulating layer forming step, the first insulating layer 12 is formed on the base material S. The base material S is the material of the support layer 11 of the wiring circuit board 1 (refer to Figure 2 ). The base material S is a metal foil made of the metal forming the support layer 11.

[0112] In the first insulating layer forming step, the first insulating layer 12 is formed on the product area P of the base material S. The product area P is the area that becomes the wiring circuit board 1.

[0113] In the first insulating layer forming step, first, a solution (varnish) of a photosensitive resin is coated on the base material S and dried to form a photosensitive resin coating film. Then, the photosensitive resin coating film is exposed and developed. Thereby, the first insulating layer 12 is formed on the base material S.

[0114] (2) Pattern forming step

[0115] Next, as Figure 3B andFigure 3C As shown, in the pattern formation process, a conductor pattern 13 is formed on the first insulating layer 12, and dummy conductor patterns 14A and 14B are formed together with the conductor pattern 13. In the present embodiment, the pattern formation process includes a first pattern formation process (refer to Figure 3B ) and a second pattern formation process (refer to Figure 3C ). That is, the manufacturing method of the wiring circuit board 1 includes a first pattern formation process and a second pattern formation process.

[0116] As Figure 3B shown, in the first pattern formation process, a first conductor layer 1311 is formed on the first insulating layer 12, and a dummy first conductor layer 141 is formed together with the first conductor layer 1311.

[0117] Specifically, in the first pattern formation process, first, a seed layer is formed on the surface of the first insulating layer 12 and the substrate S. The seed layer is formed by, for example, sputtering. As the material of the seed layer, for example, chromium, copper, nickel, titanium, and their alloys can be cited.

[0118] Next, an anti-plating layer is bonded on the first insulating layer 12 and the substrate S on which the seed layer is formed. Next, the anti-plating layer is exposed in a state where the portions for forming the first conductor layer 1311 and the dummy first conductor layer 141 are shielded from light. Next, the exposed anti-plating layer is developed.

[0119] Thereby, the anti-plating layer of the shielded portion, that is, the portions for forming the first conductor layer 1311 and the dummy first conductor layer 141, is removed, and the seed layer is exposed. On the other hand, the anti-plating layer of the exposed portion, that is, the portion where the first conductor layer 1311 and the dummy first conductor layer 141 are not formed, remains.

[0120] Next, the first conductor layer 1311 and the dummy first conductor layer 141 are formed on the exposed seed layer by electroplating.

[0121] At this time, the first conductor layer 1311 is formed together with the dummy first conductor layer 141. Therefore, in the electroplating solution, it is possible to suppress the metal ion concentration around the first conductor layer 1311 from becoming too high. As a result, it is possible to suppress the thickness of the first conductor layer 1311 from becoming thicker than the design value.

[0122] After the electroplating is completed, the anti-plating layer is peeled off.

[0123] Next, as Figure 3C shown, in the second pattern formation process, a second conductor layer 1312 is formed on the first conductor layer 1311, and a dummy second conductor layer 142 is formed together with the second conductor layer 1312.

[0124] Specifically, an anti-plating layer is bonded onto the first insulating layer 12, the first conductor layer 1311, the dummy first conductor layer 141, and the substrate S. Next, with the portions where the second conductor layer 1312 and the dummy second conductor layer 142 are to be formed shielded from light, the anti-plating layer is exposed. Next, the exposed anti-plating layer is developed.

[0125] Thereby, the anti-plating layer on the shielded portions, i.e., the portions where the second conductor layer 1312 and the dummy second conductor layer 142 are to be formed, is removed, exposing the first conductor layer 1311 and the dummy first conductor layer 141. On the other hand, the anti-plating layer on the exposed portions, i.e., the portions where the second conductor layer 1312 and the dummy second conductor layer 142 are not to be formed, remains.

[0126] Next, by electroplating, the second conductor layer 1312 is formed on the exposed first conductor layer 1311, and the dummy second conductor layer 142 is formed on the exposed dummy first conductor layer 141.

[0127] At this time, the second conductor layer 1312 and the dummy second conductor layer 142 are formed together. Therefore, in the electroplating solution, it is possible to suppress the metal ion concentration around the second conductor layer 1312 from becoming too high. As a result, it is possible to suppress the thickness of the second conductor layer 1312 from becoming thicker than the design value.

[0128] After electroplating is completed, the anti-plating layer is peeled off, and the exposed seed layer is removed by etching.

[0129] (4) Second Insulating Layer Formation Process

[0130] Next, in the second insulating layer formation process, as Figure 1 shown, the second insulating layer 15 is formed on the first insulating layer 12 and the conductor pattern 13.

[0131] In the second insulating layer formation process, first, a solution (varnish) of a photosensitive resin is coated on the first insulating layer 12 and the conductor pattern 13 and dried to form a coating film of the photosensitive resin. Next, the coating film of the photosensitive resin is exposed and developed. Thereby, the second insulating layer 15 is formed.

[0132] (5) Etching Process

[0133] Next, as Figure 3D shown, in the etching process, the substrate S around the product area P is removed by etching. Thereby, the wiring circuit board 1 is obtained.

[0134] 3. Function and Effect

[0135] (1) As Figure 1 shown, the wiring circuit board 1 includes a dummy conductor pattern 14A.

[0136] Therefore, compared with the structure in which the dummy conductor pattern 14A is formed outside the wiring circuit board 1, the dummy conductor pattern 14A is disposed closer to the conductor pattern 13.

[0137] Moreover, the dummy conductor pattern 14A is located within a circular region R3 having a diameter of 3.5 mm centered on the terminal 131C.

[0138] Therefore, it is possible to improve the dimensional accuracy of the thickness of the terminal 131C.

[0139] (2) According to the wiring circuit board 1, as Figure 1 shown, the dummy first conductor layer 141 is provided in such a manner that the first conductor layer 1311 of the terminal 131C and the dummy first conductor layer 141 occupy an area of more than 5% of the region R3.

[0140] Thereby, it is possible to suppress the deviation of the thickness of the first conductor layer 1311 of the terminal 131C from the design value.

[0141] Moreover, the dummy second conductor layer 142 is provided in such a manner that the second conductor layer 1312 of the terminal 131C and the dummy second conductor layer 142 occupy an area of more than 5% of the region R3.

[0142] Thereby, it is also possible to suppress the deviation of the thickness of the second conductor layer 1312 of the terminal 131C from the design value.

[0143] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal 131C.

[0144] 4. Modification

[0145] Hereinafter, with reference to Figures 4 to 7 , a modification of the wiring circuit board will be described. In the following modification, the same reference numerals are given to the same components as those in the above-described embodiment, and the description thereof is omitted.

[0146] (1) As Figure 4 shown, the terminals 131A, 131B, 131C, 131D, and 131E may also be made of a single conductor layer. In this case, the dummy conductor pattern 14A is also made of a single conductor layer.

[0147] In this case, if the sum of the area of the dummy conductor pattern 14A within the region R3 and the area of the terminal 131C is more than 5% of the area of the region R3, it is possible to suppress the deviation of the thickness of the terminal 131C from the design value.

[0148] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal 131C.

[0149] (2) As Figure 5As shown, the dummy conductor pattern 14A may also not have the dummy second conductor layer 142 and may be made only of the dummy first conductor layer 141.

[0150] In this case, in the first pattern forming process, the first conductor layer 1311 is formed together with the dummy conductor pattern 14A.

[0151] The dummy conductor pattern 14A has the same first thickness as the first conductor layer 1311.

[0152] In addition, the sum of the area of the dummy conductor pattern 14A in the region R3 and the area of the first conductor layer 1311 is 5% or more of the area of the region R3.

[0153] Therefore, in the first pattern forming process, it is possible to suppress the thickness of the first conductor layer 1311 from deviating from the design value.

[0154] Moreover, in the second pattern forming process, the second conductor layer 1312 is formed on the first conductor layer 1311.

[0155] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal 131C.

[0156] (3) As Figure 6 shown, the dummy conductor pattern 14A may also not have the dummy first conductor layer 141 and may be made only of the dummy second conductor layer 142.

[0157] In this case, in the second pattern forming process, the second conductor layer 1312 is formed together with the dummy conductor pattern 14A.

[0158] The dummy conductor pattern 14A has the same second thickness as the second conductor layer 1312.

[0159] In addition, the sum of the area of the dummy conductor pattern 14A in the region R3 and the area of the second conductor layer 1312 is 5% or more of the area of the region R3.

[0160] Therefore, in the second pattern forming process, it is possible to suppress the thickness of the second conductor layer 1312 from deviating from the design value.

[0161] As a result, it is possible to improve the dimensional accuracy of the thickness of the terminal 131C.

[0162] (4) As Figure 7As shown, the dummy conductor pattern 14A can also be formed across a plurality of terminals 131C and 131D. In this case, the dummy conductor pattern 14A extends in the direction in which the plurality of terminals 131C and 131D are arranged (in this modification, the first direction). In addition, a part of the dummy conductor pattern 14A may be located within the region R3. In this modification, one end portion of the dummy conductor pattern 14A is located within the region R3, and the other end portion of the dummy conductor pattern 14A is located within the region R4.

[0163] In this modification, the same operational effects as those of the above-described embodiment can also be obtained.

[0164] (5) As Figure 8 shown, the wiring circuit board 1 may also have a metallic ground layer 100 between the support layer 11 and the first insulating layer 12. In this case, the conductor pattern 13 also has a ground wiring (not shown), and the ground wiring is connected to the ground layer 100 through a through hole of the first insulating layer 12.

[0165]

Embodiment

[0166] Next, the present invention will be described based on embodiments and comparative examples. The present invention is not limited to the following embodiments. In addition, the specific numerical values such as physical property values and parameters used in the following description can be replaced with the upper limit values (numerical values defined as "below" and "less than") or lower limit values (numerical values defined as "above" and "greater than") of the corresponding physical property values and parameters described in the above "Detailed Description".

[0167] 1. Manufacture of Wiring Circuit Board

[0168] The wiring circuit boards of the respective embodiments and the respective comparative examples were manufactured.

[0169] (1) Respective Embodiments

[0170] First, a solution (varnish) of a photosensitive resin was coated on a metal foil as a base material and dried to form a photosensitive resin coating film.

[0171] Next, the photosensitive resin coating film was exposed and developed to form a first insulating layer on the base material (first insulating layer forming step, refer to Figure 3A ).

[0172] Next, a seed layer was formed on the surfaces of the first insulating layer and the base material by sputtering.

[0173] Next, an anti-plating layer was bonded onto the first insulating layer and the metal foil on which the seed layer was formed.

[0174] Next, while making the percentage (area ratio) of "the sum of the area of the dummy conductor pattern and the area of the terminal" with respect to the area of the circular region having a diameter of 3.5 mm with the terminal at the center be the value shown in Table 1 below, in a state where the portions of the conductor pattern (design value of the terminal thickness: 10 μm) and the dummy conductor pattern are shielded from light, the anti-plating layer is exposed.

[0175] Next, the exposed anti-plating layer is developed to remove the anti-plating layer in the portions where the conductor pattern and the dummy conductor pattern are formed.

[0176] Next, by electroplating, a conductor pattern and a dummy conductor pattern are formed on the seed layer exposed from the anti-plating layer (pattern formation process, refer to Figure 4 ). After the electroplating is completed, the anti-plating layer is peeled off, and the exposed seed layer is removed by etching.

[0177] Next, a solution (varnish) of a photosensitive resin is applied onto the first insulating layer and the conductor pattern and dried to form a photosensitive resin coating film. Next, the photosensitive resin coating film is exposed and developed to form the second insulating layer.

[0178] Then, the substrate is etched along the outer shape of the wiring circuit substrate (etching process) to obtain the wiring circuit substrate.

[0179] (2) Comparative Example

[0180] A wiring circuit substrate is obtained in the same manner as in each of the examples, except that no dummy conductor pattern is formed. In addition, in the case where no dummy conductor pattern is formed, the area ratio is the percentage of the area of the terminal with respect to the area of the circular region having a diameter of 3.5 mm with the terminal at the center, and is 3%.

[0181] 2. Evaluation

[0182] The thickness of the terminals of the wiring circuit substrates of each of the examples and the comparative example is measured. The difference between the measured thickness and the design value (10 μm) is shown in Table 1. In addition, a positive value indicates that the terminal is formed thicker than the design value, and a negative value indicates that the terminal is formed thinner than the design value.

[0183] Table 1

[0184] Area ratio Difference from the design value (μm) Example 1 10％ 0.09 Example 2 21％ 0.20 Example 3 38％ -0，02 Example 4 60％ -0.75 Comparative example 3％ 2.03

[0185] Furthermore, the above invention is provided as an exemplary embodiment of the present invention, but this is merely an example and should not be construed in a limiting sense. Modification examples of the present invention that are obvious to those skilled in the art are included within the scope of the foregoing claims.

[0186] Industrial Applicability

[0187] The wiring circuit board of the present invention can be used for connection with electronic components.

Claims

1. A wiring circuit substrate, wherein: The wiring circuit substrate has: Insulation layer; a conductor pattern, which is located on the insulating layer and has terminals; and a dummy conductor pattern, which is arranged on the insulating layer separately from the conductor pattern, The dummy conductor pattern is arranged in a circular region with a diameter of 3.5 mm in which the terminal is located at the center in the direction in which the surface of the insulating layer extends, that is, in the plane direction.

2. The wiring circuit substrate according to claim 1, wherein A total of an area of ​​the dummy conductor pattern and an area of ​​the terminal within the circular region is equal to or greater than 5% of an area of ​​the circular region.

3. The wired circuit substrate according to claim 1, wherein: The terminal has: a first conductor layer having a first thickness; and a second conductor layer, which is located on the first conductor layer and has a second thickness different from the first thickness, The dummy conductor pattern has the first thickness, A total of an area of ​​the dummy conductor pattern and an area of ​​the first conductor layer in the circular region is equal to or greater than 5% of an area of ​​the circular region.

4. The wired circuit substrate according to claim 1, wherein: The terminal has: a first conductor layer having a first thickness; and a second conductor layer, which is located on the first conductor layer and has a second thickness different from the first thickness, The dummy conductor pattern has the second thickness, A total of an area of ​​the dummy conductor pattern and an area of ​​the second conductor layer in the circular region is equal to or greater than 5% of an area of ​​the circular region.

5. The wired circuit substrate according to claim 1, wherein: The terminal has: a first conductor layer having a first thickness; and a second conductor layer, which is located on the first conductor layer and has a second thickness different from the first thickness, The dummy conductor pattern has: a dummy first conductor layer having the first thickness; and a dummy second conductor layer, which is located on the dummy first conductor layer and has the second thickness, The sum of the area of ​​the dummy first conductor layer and the area of ​​the first conductor layer in the circular region is 5% or more of the area of ​​the circular region. A total of an area of ​​the dummy second conductor layer and an area of ​​the second conductor layer in the circular region is equal to or greater than 5% of an area of ​​the circular region.

6. A method for manufacturing a wiring circuit substrate, which is the method for manufacturing a wiring circuit substrate according to claim 1 or 2, wherein: The manufacturing method of the wiring circuit substrate comprises: an insulating layer forming step of forming the insulating layer; and A pattern forming step in which the conductor pattern is formed on the insulating layer, and the dummy conductor pattern is formed together with the conductor pattern.

7. A method for manufacturing a wiring circuit substrate, which is the method for manufacturing a wiring circuit substrate according to claim 3, wherein: The manufacturing method of the wiring circuit substrate comprises: an insulating layer forming step, in which the insulating layer is formed; a first pattern forming step of forming the first conductor layer on the insulating layer, wherein the dummy conductor pattern is formed together with the first conductor layer; and A second patterning step is performed in which the second conductor layer is formed on the first conductor layer.

8. A method for manufacturing a wired circuit substrate, which is the method for manufacturing a wired circuit substrate according to claim 4, wherein: The manufacturing method of the wiring circuit substrate comprises: an insulating layer forming step, in which the insulating layer is formed; a first patterning step of forming the first conductor layer on the insulating layer; and and a second pattern forming step of forming the second conductor layer on the first conductor layer, wherein the dummy conductor pattern is formed together with the second conductor layer.

9. A method for manufacturing a wired circuit substrate, which is the method for manufacturing a wired circuit substrate according to claim 5, wherein: The manufacturing method of the wiring circuit substrate comprises: an insulating layer forming step, in which the insulating layer is formed; a first pattern forming step of forming the first conductor layer on the insulating layer, wherein the dummy first conductor layer is formed together with the first conductor layer; and A second patterning step is performed in which the second conductor layer is formed on the first conductor layer, and the dummy second conductor layer is formed together with the second conductor layer.

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