Photoinduced adjustment ferroelectric tunnel junction memory and preparation method thereof

Abstract

The invention discloses a photoinduced adjustment ferroelectric tunnel junction memory and a preparation method thereof, relates to the technical field of memories, and aims to solve the problem that sensing, storage and calculation integration cannot be realized by a ferroelectric memory in the prior art. The ferroelectric memory includes: a substrate; the ferroelectric layer is formed on the substrate, the photoelectric trapping layer is formed on the ferroelectric layer, and the upper electrode is formed on the photoelectric trapping layer; or, the photoelectric trapping layer is formed on the substrate, the ferroelectric layer is formed on the photoelectric trapping layer, and the upper electrode is formed on the ferroelectric layer; the photoelectric trapping layer is used for trapping photon-generated carriers. According to the ferroelectric tunnel junction memory provided by the invention, sensing, storage and calculation integration of the ferroelectric memory can be realized by introducing the photoelectric capture layer.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and in particular, to a ferroelectric tunnel junction memory with photoinduced regulation and a preparation method thereof. Background Art

[0002] The optoelectronic responses of most existing ferroelectric memories are based on non-CMOS-compatible processes, which are difficult to integrate and not easily applicable to the work of memory-computation integration. Moreover, the current responses to optical pulses in most works are not satisfactory (not obvious or too long in time), which is not conducive to the performance requirements of the current memory-computation integration. In addition, the operating voltage of the current ferroelectric memory is too large, which is not conducive to low-power applications.

[0003] There is an urgent need in this field for a ferroelectric memory that meets the basic requirements of memory-computation integration. Summary of the Invention

[0004] The purpose of the present invention is to provide a ferroelectric tunnel junction memory with photoinduced regulation and a preparation method thereof, for realizing the memory-computation integration of the ferroelectric memory.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] In the first aspect, the present invention provides a ferroelectric tunnel junction memory with photoinduced regulation, including:

[0007] A substrate;

[0008] A ferroelectric layer formed on the substrate, a photoinduced charge trapping layer formed on the ferroelectric layer, and a top electrode formed on the photoinduced charge trapping layer;

[0009] Or,

[0010] The photoinduced charge trapping layer formed on the substrate, the ferroelectric layer formed on the photoinduced charge trapping layer, and the top electrode formed on the ferroelectric layer;

[0011] The photoinduced charge trapping layer is used for trapping photo-generated carriers.

[0012] Optionally, the material of the photoinduced charge trapping layer is a semiconductor oxide.

[0013] Optionally, the material of the substrate is germanium.

[0014] Optionally, the semiconductor oxide is TiO 2 .

[0015] Optionally, the material of the ferroelectric layer is a hafnium-based ferroelectric material.

[0016] In the second aspect, the present invention also provides a preparation method of a ferroelectric tunnel junction memory with photoinduced regulation, including:

[0017] Form a ferroelectric layer on a substrate;

[0018] Form a photoexcitation trapping layer on the ferroelectric layer; the photoexcitation trapping layer is used to trap photo-generated carriers;

[0019] Fabricate an upper electrode on the photoexcitation trapping layer;

[0020] Or,

[0021] Form the photoexcitation trapping layer on the substrate;

[0022] Form the ferroelectric layer on the photoexcitation trapping layer;

[0023] Fabricate the upper electrode on the ferroelectric layer.

[0024] Optionally, forming the photoexcitation trapping layer includes:

[0025] Grow an electrode layer with a thickness of 10 - 100 nm; the material of the electrode layer is titanium nitride or tungsten.

[0026] Anneal the device after growing the electrode layer;

[0027] After the annealing treatment, wet-etch the electrode layer to form the photoexcitation trapping layer.

[0028] Optionally, the annealing time during the annealing treatment is 15 - 50 s.

[0029] Optionally, the annealing temperature during the annealing treatment is 300 - 800 °C.

[0030] Optionally, forming the ferroelectric layer on the substrate includes:

[0031] Based on a deposition temperature of 200 - 260 °C, deposit a hafnium zirconium oxide thin film with a thickness of 3 - 10 nm on a germanium substrate by ALD deposition method to form the ferroelectric layer.

[0032] Compared with the prior art, the present invention provides a photoinduced regulated ferroelectric tunnel junction memory and a preparation method thereof. Based on the CMOS-compatible process, the ferroelectric tunnel junction memory innovatively introduces a photoinduced charge trapping layer to construct an opto-electric dual modulation interface. Through the synergistic effect of photoinduced excitation and electric field regulation, the ferroelectric tunnel junction memory exhibits the plasticity characteristics of a biomimetic neural synapse: when a light pulse is applied, the photo-generated carriers generated by the photoinduced charge trapping layer form an enhanced polarization shielding effect, inducing the conductance state of the ferroelectric layer to evolve towards the high-conductance direction; while the electric pulse realizes the reversible modulation of the conductance state through the dynamic balance of carrier trapping / release at the interface, generating an inhibitory polarization regulation. This continuous conductance state change of dual-mode modulation can accurately simulate the weight update mechanism of biological synapses, and its dynamic response characteristics highly coincide with the spike-timing dependent plasticity (STDP) required for neuromorphic computing. Through the spatio-temporal encoding of opto-electric signals, the ferroelectric tunnel junction memory device can realize the functional integration of optical sensing, non-volatile storage, and analog computing in a single physical structure, providing a hardware foundation for constructing an integrated sensing, storage, and computing architecture, and is particularly suitable for neuromorphic computing scenarios such as artificial vision systems and spiking neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present invention. A part of the present invention, the schematic embodiments and descriptions thereof are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0034] Figure 1 FIG. 1 is one of the schematic structural diagrams of the ferroelectric memory provided by an embodiment of the present invention;

[0035] Figure 2 FIG. 2 is the second schematic structural diagram of the ferroelectric memory provided by an embodiment of the present invention;

[0036] Figure 3 FIG. 3 is one of the schematic flowcharts of the preparation method of the ferroelectric memory provided by an embodiment of the present invention;

[0037] Figure 4 FIG. 4 is the second schematic flowchart of the preparation method of the ferroelectric memory provided by an embodiment of the present invention;

[0038] Figure 5 FIG. 5 is a comparison curve diagram of the change of the storage window of the ferroelectric memory provided in the first specific embodiment of the present invention under dark conditions and light conditions;

[0039] Figure 6 FIG. 6 is a pulse-conductance relationship diagram of the ferroelectric memory provided in the first specific embodiment of the present invention under optical enhancement conditions and electrical inhibition conditions.

[0040] Reference numerals: 10 - substrate; 11 - germanium substrate; 20 - ferroelectric layer; 30 - photo - charge - trapping layer; 31 - HZO thin - film layer; 40 - upper electrode. Detailed implementation manners

[0041] For the convenience of clearly describing the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their sequence. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and "first", "second", etc. do not necessarily mean different.

[0042] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific way.

[0043] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist.

[0044] In a first aspect, as Figure 1 shown, an embodiment of the present invention provides a photo - regulated ferroelectric tunnel - junction memory, which may include: a substrate 10, a ferroelectric layer 20 formed on the substrate 10, a photo - charge - trapping layer 30 formed on the ferroelectric layer 20, and an upper electrode 40 formed on the photo - charge - trapping layer 30. Among them, the photo - charge - trapping layer 30 is used to trap photo - generated carriers.

[0045] Alternatively, an embodiment of the present invention provides a photo - regulated ferroelectric tunnel - junction memory, which may include: a substrate, a photo - charge - trapping layer formed on the substrate; a ferroelectric layer formed on the photo - charge - trapping layer, and an upper electrode formed on the ferroelectric layer. Among them, the photo - charge - trapping layer is used to trap photo - generated carriers. For example Figure 2 shown, a photo - regulated ferroelectric tunnel - junction memory may include a germanium substrate 11, a photo - charge - trapping layer 30 formed on the germanium substrate 11, an HZO thin - film layer 31 formed on the photo - charge - trapping layer 30, and an upper electrode 40 formed on the HZO thin - film layer 31. Among them, the HZO thin - film layer 31 serves as the ferroelectric layer.

[0046] It should be noted that the ferroelectric memory in this embodiment is fabricated based on a CMOS - compatible process.

[0047] The ferroelectric layer has ferroelectric properties and exhibits spontaneous polarization. Its polarization state can be regulated by factors such as electric field, stress, or temperature. The change in the polarization state of the ferroelectric layer affects its electrical properties, such as conductivity. Different conductivity states can be used to store different data, realizing the data storage function. At the same time, the change in its polarization state and the corresponding change in electrical properties can be used to simulate logical operations and participate in the calculation process.

[0048] The core function of the photoinduced charge trapping layer is to absorb photons and generate photoinduced carriers (electron-hole pairs), and then trap and store these carriers for subsequent signal processing and storage. When irradiated with light, the photoinduced charge trapping layer generates photoinduced carriers. On the one hand, it can shield the polarization of the ferroelectric layer. On the other hand, based on the photoinduced carriers and the externally applied electric field (this externally applied electric field is realized based on the top electrode), the polarization of the ferroelectric layer can be reversed. By regulating the polarization of the ferroelectric layer, the electrical properties of the ferroelectric layer are further affected, achieving the purpose of controlling electrical properties such as the conductivity of the memory.

[0049] The top electrode is mainly used to apply an external electric field, interact with the ferroelectric layer and the photoinduced charge trapping layer, and cooperate with the photoinduced charge trapping layer to control the polarization state of the ferroelectric layer. At the same time, the electrode also serves as the input and output terminals of electrical signals, used to read and write data in the memory and participate in the electrical signal transmission during the calculation process.

[0050] Analysis of technical effects: In some ferroelectric memories in the prior art, the ferroelectric layer is often located between two electrode layers, and the polarization state of the ferroelectric layer is regulated by the externally applied electric field applied by the electrodes. Although this structure of ferroelectric memory can achieve the integration of storage and computing for some functions, compared with memory devices with photo-response, the dimension of signal processing is relatively single, and it cannot make full use of the rich information carried by optical signals, which limits the application of the storage-computation integrated system in optical information processing. Another part of the ferroelectric memories in the prior art has photo-response, but these ferroelectric memories are fabricated based on non-CMOS-compatible processes. Due to the limitations of non-CMOS-compatible processes, it also leads to difficulties in integrating storage units and computing units, and it is not easy to be applied in the work of storage-computation integration.

[0051] To solve the above problems, this embodiment provides a ferroelectric memory. On the basis of CMOS compatibility, a photoinduced charge trapping layer is introduced into the ferroelectric memory to meet the basic requirements of integrated sensing and computing. The working principle is as follows: When light irradiates the photoinduced charge trapping layer, photo-generated carriers are generated. After these photo-generated carriers are trapped by the photoinduced charge trapping layer, they can affect the polarization state of the ferroelectric layer, realizing polarization shielding of the ferroelectric layer. Or, under the combined action of photo-generated carriers and an externally applied electric field, polarization reversal in the ferroelectric layer is achieved. The change in the polarization state of the ferroelectric layer will cause a change in its conductance, and the change in conductance can correspond to different data storage states (for example, high conductance represents "1" and low conductance represents "0"), realizing data storage; when an input electrical signal is applied, the change in the conductance state of the ferroelectric layer can simulate the logic operation process. For example, the binary resistance states (high / low resistance states) of ferroelectric tunnel junctions are used to achieve analog computing through tunneling current difference, supporting in-situ logic operations (such as XOR), thereby realizing the computing function. In this way, the ferroelectric memory in this embodiment realizes the requirements of integrated sensing and computing.

[0052] Optionally, the material of the ferroelectric layer is a hafnium-based ferroelectric material. Compared with other ferroelectric materials, hafnium-based ferroelectric materials have unique ferroelectric properties, such as reversible spontaneous polarization characteristics, and can change the polarization state under the action of an electric field, thereby realizing data writing and reading. For example, the ferroelectric layer is a HZO thin film layer.

[0053] Optionally, the material of the photoinduced charge trapping layer is a semiconductor oxide such as TiO 2 This. Compared with the materials of other photoinduced charge trapping layers such as silicon (Si), germanium (Ge), compound semiconductors (such as GaAs, InP, etc.), such as TiO 2 Has the following advantages: First, the CMOS (complementary metal oxide semiconductor) compatible process is adopted in this embodiment. TiO 2 Has good compatibility with the CMOS (complementary metal oxide semiconductor) process, can be prepared and processed on the CMOS process line, and can conveniently integrate the optoelectronic function into the existing CMOS circuit to realize functions such as integrated sensing and computing. However, some compound semiconductor materials have poor compatibility with the CMOS process and require the development of special integration processes to achieve combination with CMOS circuits; Second, TiO 2 Has good chemical stability and corrosion resistance, can remain stable in some corrosive environments, is not easily oxidized or react with other chemical substances, and can better protect its own structure and performance in various chemical environments such as acids and bases that the optoelectronic sensor may come into contact with, ensuring the stability of optoelectronic performance, while silicon, germanium, etc. may undergo surface corrosion in certain chemical environments; Third, TiO 2It has a suitable energy band structure, good absorption capacity for ultraviolet light and some visible light, can effectively absorb photon energy, and can convert the absorbed light energy into chemical energy or electrical energy, etc. It has important applications in the fields of photocatalysis and photoelectric conversion. Its light absorption capacity is different from that of silicon, germanium, etc. in some specific wavelength ranges and has advantages; Fourth, TiO 2 Under certain conditions, it can have better carrier transport performance. After proper doping or surface treatment, it can achieve rapid photogenerated carrier transport, reduce the recombination probability of carriers, and thus improve the photoelectric conversion efficiency. Compared with silicon, germanium, etc., it has unique advantages in certain mechanisms of carrier transport. Fifth, TiO 2 It has high thermal stability, can maintain stable physical and chemical properties in high-temperature environments, is not prone to thermal deformation or chemical reactions, can withstand high temperatures, and ensures the stable performance of the photoelectric capture layer under high-temperature conditions. Its thermal stability is better than that of silicon, germanium, etc., and similar to TiN and W, it can meet some high-temperature photoelectric application scenarios.

[0054] For example, the material of the substrate is germanium. Compared with substrates of other materials, the advantages of using germanium as the substrate base are: 1. The ferroelectric memory in this embodiment can adjust the substrate conductivity according to the actual process conditions, and its conductivity can be precisely controlled by doping the germanium substrate with different types and concentrations. This enables the germanium substrate to better adapt to different circuit designs and application requirements. For example, a high doping concentration can be used to improve the conductivity in the part where low resistance connection is required, while low doping or intrinsic germanium can be used in the area where isolation or insulation is required; 2. There is good lattice matching and chemical compatibility between germanium and hafnium-based ferroelectric materials. Good lattice matching can reduce the lattice mismatch stress at the interface and reduce the defect density, thereby improving the quality and performance of the ferroelectric layer; 3. Germanium has higher electron and hole mobility. Higher carrier mobility means that the device formed on the germanium substrate can achieve faster electron transmission speed, which helps to improve the read and write speed and operating frequency of the ferroelectric memory, reduce the delay of data processing, and thus improve the performance of the entire memory; 4. The upper electrode uses conductive materials such as TiN and W, and the germanium substrate also has good compatibility with these electrode materials. They can form good ohmic contacts, reduce contact resistance, facilitate the injection and collection of electrons, and improve the electrical performance of the device. 5. The process flow includes a rapid thermal annealing step, and the germanium substrate can withstand the temperature range required by the process (300-800°C) without significant structural changes or performance degradation. Thermal annealing is essential for activating the ferroelectricity of hafnium-based ferroelectric materials. The stability of the germanium substrate during thermal annealing ensures that the ferroelectric layer can fully exert its performance.

[0055] For example, the thickness of the upper electrode is 10 to 100 nm.

[0056] Optionally, the material of the upper electrode is a material that easily captures oxygen, such as Ti.

[0057] The material of the upper electrode is limited to a material that easily captures oxygen because the stability of the semiconductor oxide (i.e., the photoexcitation capture layer) needs to be further improved before the upper electrode is formed, and the material that easily captures oxygen can further stabilize, for example, TiO 2 this layer of semiconductor oxide, improving the stability of the photoexcitation capture layer.

[0058] It should be noted that the photoexcitation capture layer in this embodiment is obtained by wet etching of the sacrificial layer, and the sacrificial layer can be an electrode layer. For example, the material of the electrode layer is titanium nitride or tungsten.

[0059] In a second aspect, for example Figure 3 as shown, the embodiment of the present invention further provides a method for manufacturing a ferroelectric memory, which may include:

[0060] Step 110: Form a ferroelectric layer on a substrate;

[0061] Step 120: Form a photoexcitation capture layer on the ferroelectric layer; the photoexcitation capture layer is used to capture photo-generated carriers;

[0062] Step 130: Prepare an upper electrode on the photoexcitation capture layer.

[0063] Alternatively, the manufacturing method includes:

[0064] Form a photoexcitation capture layer on a substrate;

[0065] Form a ferroelectric layer on the photoexcitation capture layer;

[0066] Prepare the upper electrode on the ferroelectric layer.

[0067] Step 110 may specifically include: Based on a deposition temperature of 200 - 260 °C, use ALD deposition method to deposit a hafnium zirconium oxide thin film with a thickness of 3 - 10 nm on a germanium substrate to form a ferroelectric layer.

[0068] For example Figure 4 as shown, Step 120 may further include:

[0069] Step 121: Grow an electrode layer with a thickness of 10 - 100 nm on the ferroelectric layer; the material of the electrode layer is titanium nitride or tungsten;

[0070] Step 122: Anneal the device after growing the electrode layer; wherein, the annealing time during annealing is 15 - 50 s; the annealing temperature is 300 - 800 °C;

[0071] Step 123: After annealing, wet-etch the electrode layer to form a photoexcitation capture layer.

[0072] The preparation process of the photo-induced regulated ferroelectric tunnel junction memory will be elaborated in detail below in conjunction with Specific Embodiment 1. In Specific Embodiment 1, the preparation method of the photo-induced regulated ferroelectric tunnel junction memory includes the following specific steps:

[0073] (1) Place the Ge (germanium) wafer in a hydrofluoric acid (HF) solution for cleaning. The substrate conductivity, HF solution concentration, and cleaning duration can be adjusted according to actual process conditions.

[0074] (2) Deposit an HZO thin film layer (ferroelectric layer) on the Ge surface; the deposition temperature is 200 - 260 °C, and the thickness of the HZO thin film layer is 3 - 10 nm.

[0075] (3) Grow an electrode layer on the HZO thin film layer. The thickness of the electrode layer is 10 - 100 nm. The material of the electrode layer is TiN.

[0076] (4) Perform rapid thermal annealing on the device using nitrogen; the temperature range is 300 - 800 °C, and the time is 15 s - 50 s.

[0077] (5) Immerse the annealed device in 50% H2O2 at normal temperature and pressure for 1 - 5 hours, and then perform wet etching treatment to form a photoinduced charge trapping layer on the upper interface.

[0078] (6) Prepare the upper electrode for the sample with the photoinduced charge trapping layer. The deposition thickness of the upper electrode is 10 nm - 100 nm. The material of the upper electrode is an oxygen - scavenging material, such as Ti.

[0079] It should be noted that the electrode layer in step (3) serves as a sacrificial layer (in semiconductor manufacturing and other processes, a sacrificial layer is a temporarily added material layer that is introduced at a specific process stage, mainly to assist in achieving some specific manufacturing steps or protecting certain areas, and will be removed or consumed through specific process steps after completing its mission). In step (5), the Ti element in TiN can react with H 2 O 2 to generate TiO 2 , and the reaction principle is as follows: 2TiN + 5H 2 O 2 = 2TiO 2 + N 2 ↑ + 5H 2 O. And in step (6), the upper electrode Ti, as an oxygen - scavenging material, will further stabilize the semiconductor oxide layer like TiO 2 . Acting together with the TiO 2 generated in step 5, TiO 2Shift in the direction that is more conducive to the formation of the optoelectronic capture layer, and ultimately achieve a stable optoelectronic capture layer.

[0080] In this embodiment, the oxygen - scavenging material Ti electrode can further stabilize TiO 2 This layer of semiconductor oxide is mainly based on the following principles: First, the shift of the redox balance: Oxygen - scavenging materials such as Ti have strong reducibility. In the system in contact with TiO 2 Due to its strong affinity for oxygen, it tends to obtain oxygen atoms from the surrounding environment and undergoes an oxidation reaction to form titanium oxides. When there is TiO 2 present, the oxygen in TiO 2 may have a certain degree of activity and mobility. The process of oxygen scavenging by materials such as Ti will break the original redox balance, prompting the oxygen in TiO 2 to combine with Ti to form more stable titanium - oxygen bonds, thus making the existence state of TiO 2 in the system more stable; Second, inhibiting the phase change and decomposition of TiO 2 TiO 2 may undergo phase changes under different conditions, such as the transformation from the anatase phase to the rutile phase, or may undergo decomposition reactions in some cases. Oxygen - scavenging materials such as Ti in the system can form a certain interaction with TiO 2 This interaction will affect the atomic arrangement and chemical bond energy inside TiO 2 making the crystal structure of TiO 2 more stable and inhibiting its phase change or decomposition. From an energy perspective, the presence of materials such as Ti reduces the overall energy of the system, making TiO 2 in a more stable energy state; Third, forming a composite structure to enhance stability: After the interaction between oxygen - scavenging materials such as Ti and TiO 2 a composite structure may be formed at the interface. This composite structure can have unique physical and chemical properties, which can enhance the interaction between TiO 2 and the surrounding environment and improve its stability in the whole system. For example, in this composite structure, the electron cloud distribution may change, making the charge distribution on the surface of TiO 2 more uniform, reducing the chemical reaction activity caused by uneven charge, and thus making TiO 2 more stable; Fourth, filling lattice defects: There may be some lattice defects in the TiO 2 crystal, such as oxygen vacancies. These defects will affect the stability and performance of TiO 2 When oxygen - scavenging materials such as Ti act on TiO 2 their atoms may enter TiO 2In the lattice, these defect positions are filled, so that the lattice structure of TiO 2 is more complete and its stability is improved.

[0081] The ferroelectric memory obtained by using the preparation method in the first specific embodiment is tested to obtain Figure 5 , Figure 6 .

[0082] Figure 5 shows the ferroelectric hysteresis loop of the ferroelectric material in the ferroelectric memory prepared in the first specific embodiment. The abscissa of this graph is voltage (in V), and the ordinate is polarization (in μC / cm 2 ). Figure 5 There are two curves in it: the black curve and the red curve. The black curve represents the relationship between the polarization of the ferroelectric material and the voltage under dark conditions. The red curve represents the relationship between the polarization of the ferroelectric material and the voltage under light illumination. Compared with the curve under dark conditions, the curve under light illumination has changed significantly, that is, the storage window has changed significantly after illumination. Under dark conditions (black line), the hysteresis loop is full, and the voltage range corresponding to the remanent polarization is large, that is, the storage window is large; under light illumination conditions (red line), the hysteresis loop becomes narrower, the voltage range corresponding to the remanent polarization becomes smaller, and the storage window is significantly reduced. This is because light illumination generates photo-generated carriers, which may neutralize some of the polarization charges, weaken the internal electric field of the ferroelectric memory, reduce the potential barrier required for polarization reversal, cause changes in the resistance state of the tunnel junction, and reflect that the polarization state is regulated by photo-generated carriers.

[0083] Figure 6 including the left and right figures, which are used to study the conductance characteristics of the material under different conditions. Among them, the condition of the left figure is optical potentiation, the abscissa is the number of pulses, indicating the number of pulses applied; the ordinate is conductance, in nanoSiemens; data points: the green squares represent the measured conductance values. As the number of pulses increases, the conductance values generally show an upward trend, indicating that under the action of optical potentiation, as the number of pulses applied increases, the conductivity of the material increases. There is a schematic diagram of a green pulse waveform in the lower left corner of the figure, indicating the form of the pulse applied in the experiment. The condition of the right figure is electrical depression, the abscissa is also the number of pulses; the ordinate is conductance, in nanoSiemens; the blue dots represent the measured conductance values. As the number of pulses increases, the conductance values generally show a downward trend, meaning that under the action of electrical depression, as the number of pulses applied increases, the conductivity of the material decreases. There is a schematic diagram of a blue pulse waveform in the upper right corner of the figure, indicating the form of the pulse applied in the experiment. Overall, Figure 6The change of conductance with the number of pulses of the ferroelectric memory prepared in the first specific embodiment is shown by comparison under two different conditions of optical enhancement and electrical inhibition, which is used to understand the optoelectronic regulation characteristics of the material.

[0084] As mentioned in the background art, the optoelectronic responses of most existing ferroelectric memories are based on non-CMOS-compatible processes, which are difficult to integrate and not easily applied to the work of in-memory computing. Moreover, the current responses to optical pulses of most works are not satisfactory (not obvious or too long in time), which is not conducive to the current performance requirements of in-memory computing. In addition, the current operating voltage of ferroelectric memories is too large, which is not conducive to low-power applications. However, through Figure 6 it can be seen that the ferroelectric memory prepared in the first specific embodiment of the present invention has the performance of rapid adjustment by optical pulses. The state of the device can be modulated by optical pulses with different wavelengths and different times, effectively adjusting the storage window of the device. The ferroelectric memory device can perform modulation response in an extremely short time and be reset by electrical pulses. The processed device can have a low write voltage of 2V and a low read voltage of 0.05 - 0.2V.

[0085] The ferroelectric memory device prepared in the first specific embodiment has a significant and continuous response to optical signals, and the conductance can be continuously adjusted by optical pulses. The maximum 2Pr of the device forming the optical trapping layer is approximately 50 μC / cm2, which further reduces power consumption on the basis of non-volatility and meets the current basis for realizing the functions of sensing and in-memory computing.

[0086] Next, in combination with the second specific embodiment, the preparation process of the optically tunable ferroelectric tunnel junction memory will be elaborated in detail. In the second specific embodiment, the preparation method of the optically tunable ferroelectric tunnel junction memory includes the following specific steps:

[0087] 1) Place the Ge (germanium) wafer in a hydrofluoric acid (HF) solution for cleaning, and the substrate conductivity, HF solution concentration, and cleaning duration can be adjusted according to actual process conditions.

[0088] 2) Deposit a semiconductor oxide layer as an optical trapping layer on the Ge wafer by ALD deposition method;

[0089] 3) Deposit an HZO thin film layer (ferroelectric layer) on the optical trapping layer; the deposition temperature is 200 - 260 °C, and the thickness of the HZO thin film layer is 3 - 10 nm.

[0090] 4) Prepare the upper electrode on the HZO thin film layer, and the deposition thickness of the upper electrode is 10 nm - 100 nm.

[0091] Although the present invention has been described in connection with various embodiments, it will be understood by those skilled in the art that other variations of the disclosed embodiments can be understood and effected while practicing the claimed invention, by studying the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not indicate that these measures cannot be combined to advantage.

[0092] Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded merely as illustrative of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A photo-regulated ferroelectric tunnel junction memory, characterized in that: include: substrate; A ferroelectric layer formed on the substrate, a photoelectric capture layer formed on the ferroelectric layer, and an upper electrode formed on the photoelectric capture layer; or, The photoelectric trapping layer formed on the substrate, the ferroelectric layer formed on the photoelectric trapping layer, and the upper electrode formed on the ferroelectric layer; The photoelectric capture layer is used to capture photogenerated carriers.

2. The photo-regulated ferroelectric tunnel junction memory according to claim 1, characterized in that: The material of the photoelectric capture layer is semiconductor oxide.

3. The photo-regulated ferroelectric tunnel junction memory according to claim 1, characterized in that: The material of the substrate is germanium.

4. The photo-regulated ferroelectric tunnel junction memory according to claim 2, characterized in that: The semiconductor oxide is TiO2.

5. The photo-regulated ferroelectric tunnel junction memory according to claim 1, characterized in that: The material of the ferroelectric layer is hafnium-based ferroelectric material.

6. A method for preparing a photo-regulated ferroelectric tunnel junction memory, characterized in that: include: forming a ferroelectric layer on a substrate; forming a photoelectric trapping layer on the ferroelectric layer; The photoelectric capture layer is used to capture photogenerated carriers; preparing an upper electrode on the photoelectric capture layer; or, forming the photoelectric capture layer on the substrate; forming the ferroelectric layer on the photoelectric trapping layer; The upper electrode is formed on the ferroelectric layer.

7. The method for preparing the photo-regulated ferroelectric tunnel junction memory according to claim 6, characterized in that: The step of forming a photoelectric capture layer comprises: Growing an electrode layer with a thickness of 10 to 100 nm; the material of the electrode layer is titanium nitride or tungsten; Annealing the device after growing the electrode layer; After the annealing treatment, the electrode layer is wet-etched to form the photoelectric capture layer.

8. The method for preparing the photo-regulated ferroelectric tunnel junction memory according to claim 7, characterized in that: The annealing time during the annealing treatment is 15 to 50 seconds.

9. The method for preparing a photo-regulated ferroelectric tunnel junction memory according to claim 7, characterized in that: The annealing temperature during the annealing treatment is 300 to 800°C.

10. The method for preparing the photo-regulated ferroelectric tunnel junction memory according to claim 6, characterized in that: The step of forming a ferroelectric layer on a substrate comprises: Based on a deposition temperature of 200-260° C., an ALD deposition method is used to deposit a hafnium zirconium oxide thin film with a thickness of 3-10 nm on a germanium substrate to form the ferroelectric layer.

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