FCBGA packaging body stacked packaging structure and preparation method thereof

Abstract

The invention provides an FCBGA packaging body stack packaging structure and a preparation method thereof.The stack packaging structure is characterized in that an FCBGA packaging body is installed on a PCB, the FCBGA packaging body comprises an HBM chip and an SOC chip which are stacked on a glass substrate in the vertical direction, one side of the HBM chip and one side of the SOC chip are each provided with a micro-channel, the glass substrate is provided with a substrate micro-channel for cooling liquid to flow through, and the substrate micro-channel is provided with a substrate micro-channel for cooling liquid to flow through. And the substrate micro-channel is communicated with the micro-channels of the HBM chip and the SOC chip. The PCB is provided with a cooling liquid inlet and a cooling liquid outlet, the cooling liquid inlet is communicated with the second inlet in the back face of the glass substrate, and the cooling liquid outlet is communicated with the second outlet in the back face of the glass substrate. The invention further discloses a method for preparing the stacked packaging structure. According to the invention, the micro-channel is in direct contact with the back surface of each chip, and heat dissipation is directly carried out on the chip at the packaging middle position through liquid cooling heat dissipation, so that the packaging heat dissipation capability is improved, and the working performance of the high-performance chip is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of advanced packaging products, and more particularly to a stacked packaging structure of an FCBGA package and a preparation method thereof. Background Art

[0002] In the field of semiconductor packaging technology, the demand for devices such as communication, high-speed computing, and AI supercomputing in high-frequency fields has increased for chips with ultra-low signal loss factors, ultra-high density, ultra-high speed, ultra-low latency, and a large number of interconnected chips. Therefore, 3D packaging has become the focus of the current industry. Compared with 2.5D packaging, the principle of 3D packaging is to fabricate transistor structures on chips and use vias to connect the electronic signals of different chips above and below, so as to directly stack memories or other chips vertically on top. 3D packaging has a smaller area and lower power consumption and is used for ultra-high bandwidth. However, how to solve the insulation problem under ultra-high density wiring, the heat accumulation problem of ultra-high density chips, and realize the packaging of a large number of chips has become an important challenge.

[0003] On the one hand, in the existing 3D packaging, the chips are vertically stacked on top of each other. The chips located in the middle are limited by the packaging structure and can only conduct heat through the chips, resulting in low heat dissipation efficiency and serious heat accumulation inside the chips, which affects the chip working efficiency. Moreover, the traditional heat dissipation method only contacts the top of the chip, and only the top contact with the chip can be effectively cooled.

[0004] On the other hand, there are insulation problems in the signal transmission of the existing silicon interposer lines, with large signal attenuation, loss, and large incident signal loss. The silicon-based interposer process is complex, resulting in high costs; due to large warping, it is impossible to have an ultra-thin thickness and a large size, which affects the packaging ability of ultra-large sizes and a large number of chips.

[0005] Furthermore, traditional embedded packaging is mainly embedded in substrates and PCBs. Limited by the manufacturing capabilities of substrates and PCBs, it results in low interconnect density, long transmission paths, low transmission rates, large signal delays, and large packaging volumes, and cannot meet the high-density, high-speed, and low-latency interconnect requirements of high-frequency and high-speed electronic devices.

[0006] Therefore, there is an urgent need for a new 3D packaging structure to solve the above problems. Summary of the Invention

[0007] In order to solve the above problems, the present invention provides an FCBGA package stacking package structure and a preparation method thereof, which realizes chip 3D vertical interconnection through glass-based through-hole technology and embedded packaging technology, can realize face-to-face 3D vertical interconnection of chips at a relatively low cost, realize ultra-short transmission path between chips, improve 3D vertical interconnection density and transmission rate, reduce signal delay, and reduce package volume, so as to meet the high-density, high-speed and low-latency interconnection requirements of high-frequency and high-speed electronic equipment; at the same time, a new type of liquid-cooled microchannel auxiliary heat dissipation cover is used for heat dissipation, which has a better heat dissipation effect.

[0008] In a first aspect, the present invention provides an FCBGA package, which includes an HBM chip and a SOC chip stacked vertically on a glass substrate, a microchannel is provided on one side of the HBM chip and the SOC chip, and the glass substrate is provided with a substrate microchannel for cooling liquid to flow through, and the substrate microchannel is connected to the microchannels of the HBM chip and the SOC chip.

[0009] Preferably, the FCBGA package specifically includes: A first glass-based interposer is embedded with a SOC chip, a front side and a back side of the SOC chip are respectively provided with redistribution layers, the redistribution layers are interconnected, micro-bumps are arranged on the redistribution layers, and a first microchannel is arranged between the back side of the SOC chip and the redistribution layers; A second glass-based interposer is embedded with an HBM chip, a passivation layer and micro-bumps are provided on the front side of the HBM chip, and a second micro-channel is provided on the back side of the HBM chip; A glass substrate is provided with a circuit layer, a substrate microchannel and a substrate conductive through hole; the substrate microchannel includes a first substrate microchannel and a second substrate microchannel, the first substrate microchannel forms a first inlet on the front side of the glass substrate and a second inlet on the back side of the glass substrate; the second substrate microchannel forms a first outlet on the front side of the glass substrate and a second outlet on the back side of the glass substrate; in, The second glass-based interposer is flipped onto the front side of the SOC chip of the first glass-based interposer, and then flipped onto the front side of the glass substrate, capacitors are mounted on the front side of the glass substrate, and balls are planted on the back side of the glass substrate to form an FCBGA package; In the FCBGA package, the inlet of the second microchannel is connected to the inlet of the first microchannel and the first inlet of the substrate microchannel, and the outlet of the second microchannel is connected to the outlet of the first microchannel and the first outlet of the substrate microchannel to form a cooling channel.

[0010] Preferably, it also includes a heat dissipation cover arranged on the front side of the glass substrate, and the heat dissipation cover covers the first glass-based interlayer, the second glass-based interlayer, the capacitor and the front side of the glass substrate.

[0011] In a second aspect, the present invention further provides a stacked package structure, in which the above-mentioned FCBGA package is soldered on a PCB board. The PCB board is provided with a coolant inlet and a coolant outlet. The coolant inlet is connected to a second inlet on the back surface of the glass substrate, and the coolant outlet is connected to a second outlet on the back surface of the glass substrate.

[0012] In a third aspect, the present invention also discloses a method for preparing the above-mentioned stacked package structure, which includes the following steps: S1. Form a first microchannel, a first chip pre-set cavity, and a first conductive via in a first glass-based interposer. Embed an SOC chip in the first chip pre-set cavity. The front and back surfaces of the SOC chip are respectively provided with a redistribution layer, and the redistribution layers are interconnected through the first conductive via. Microbumps are provided on the redistribution layer, and the first microchannel is arranged between the back surface of the SOC chip and the redistribution layer; S2. Form a second microchannel and a second chip pre-set cavity in a second glass-based interposer. Embed a flip-chip HBM chip in the second chip pre-set cavity. The front surface of the HBM chip is provided with a passivation layer and microbumps, and the back surface of the HBM chip is close to the second microchannel; S3. Form a circuit layer, a substrate microchannel, and a substrate conductive via in the glass substrate; the substrate microchannel includes a first substrate microchannel and a second substrate microchannel. The first substrate microchannel forms a first inlet on the front surface of the glass substrate and a second inlet on the back surface of the glass substrate; the second substrate microchannel forms a first outlet on the front surface of the glass substrate and a second outlet on the back surface of the glass substrate; S4. After inverting the second glass-based interposer in S2 on the front side of the SOC chip of the first glass-based interposer in S1, the whole is then inverted on the front surface of the glass substrate. Mount a capacitor on the front surface of the glass substrate and implant balls on the back surface of the glass substrate to form an FCBGA package; In the FCBGA package, the inlet of the second microchannel is connected to the inlet of the first microchannel and the first inlet of the substrate microchannel, and the outlet of the second microchannel is connected to the outlet of the first microchannel and the first outlet of the substrate microchannel to form a cooling channel; S5. Solder the FCBGA package obtained in step S4 on a PCB board. The PCB board is provided with a coolant inlet and a coolant outlet. The coolant inlet is connected to the second inlet on the back surface of the glass substrate, and the coolant outlet is connected to the second outlet on the back surface of the glass substrate.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention realizes 3D vertical interconnection of chips through glass-based via technology and embedded packaging technology, can achieve face-to-face 3D vertical interconnection of chips at a lower cost, realize an ultra-short transmission path between chips, improve the 3D vertical interconnection density and transmission rate, reduce signal delay, reduce the package volume, and meet the high-density, high-speed, and low-latency interconnection requirements of high-frequency and high-speed electronic devices.

[0014] The present invention manufactures microchannels in a first glass-based interposer, a second glass-based interposer, and a glass substrate. The microchannels pass through the entire 3D package and are connected. The microchannels are in direct contact with the backs of each chip. Liquid cooling is used to directly dissipate heat from the chip in the middle of the 3D package, thereby improving the heat dissipation capacity of the package and thus improving chip performance. The requirements for ultra-high density and high heat generation chip design and packaging of high-frequency and high-speed electronic equipment are met, and the working performance of high-performance chips is improved.

[0015] The present invention uses glass insulator as the base material of the interposer and substrate of 3D packaging. Compared with silicon-based materials, glass-based interposers are used. Compared with silicon-based interposers, the glass-based interposer benefits from the easy acquisition of large-size ultra-thin panel glass and the absence of the need to deposit an insulating layer. The production cost of the glass adapter is only about 1 / 8 of that of the silicon-based interposer. The ultra-thin adapter does not require a thinning process, and the packaging process is simple, which can effectively reduce the cost of 3D packaging. The glass substrate substrate loss and parasitic effects are greatly reduced, ensuring the integrity of the transmission signal and reducing the signal loss factor. Based on this advantage, a higher density of wiring interconnection is achieved, and it has excellent electrical, thermal, and mechanical properties. It has good mechanical stability. Even when the thickness of the adapter is less than 100µm, the warping performance is good, and it has the advantage of low warping. It can achieve ultra-large size, ultra-thin packaging thickness, and ultra-large area packaging, thereby achieving ultra-multi-chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of the FCBGA package in Example 1 of the present invention; Figure 2 is a schematic structural diagram of the first glass-based interposer in Example 1 of the present invention; Figure 3 is a schematic diagram of the structure of the embedded SOC chip in Embodiment 1 of the present invention; Figure 4 is a schematic structural diagram of the second glass-based interposer in Example 1 of the present invention; Figure 5 is a schematic structural diagram of a glass substrate in Example 1 of the present invention; Figure 6 2 is a schematic diagram of a structure in which a second glass-based interposer is invertedly mounted on a first glass-based interposer in Example 1 of the present invention; Figure 7 yes Figure 6 Schematic diagram of the structure after plastic packaging; Figure 8 Yes Figure 7 Schematic diagram of the structure in which the wafer is cut into individual chips and then flipped onto a glass substrate; Figure 9It is a schematic structural diagram of soldering an FCBGA package onto a PCB board in Embodiment 2 of the present invention; Figure 10 It is a schematic diagram of a stacked package structure in Embodiment 2 of the present invention.

[0017] Label description: glass substrate 1, first glass-based interposer 2, second glass-based interposer 3, SOC chip 4, redistribution layer 5, microbump 6, first microchannel 7, HBM chip 8, passivation layer 9, second microchannel 10, substrate microchannel 11, circuit layer 12, molding compound layer 13, capacitor 14, heat sink cover 15, PCB board 16, first base glass layer 201, first top glass layer 202, first conductive via 203, first chip pre-placement cavity 401, inlet 701 of the first microchannel, second base glass layer 301, second top glass layer 302, inlet 1001, outlet 1002, second chip pre-placement cavity 801, first substrate microchannel 1101, second substrate microchannel 1102, first inlet 1103, second inlet 1104, first outlet 1105, second outlet 1106, third base glass layer 101, third top glass layer 102, substrate conductive via 103, coolant inlet 1601, coolant outlet 1602, first opposing opening 1603, coolant inlet 1601, second opposing opening 1604. Detailed implementation manners

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0020] In the present invention, the first glass-based interposer, the second glass-based interposer, and the glass substrate are all made of glass. Using glass insulators as the interposer and substrate base materials for 3D packaging, compared with silicon-based materials, using a glass-based interposer, compared with a silicon-based interposer, benefits from the easy availability of large-size ultra-thin panel glass and the elimination of the need to deposit an insulating layer. The manufacturing cost of the glass interposer is only about 1 / 8 of that of the silicon-based interposer. The ultra-thin interposer does not require a thinning process, and the packaging process flow is simple, which can effectively reduce the 3D packaging cost.

[0021] Example 1: FCBGA Package and Its Manufacturing Method This example provides an FCBGA package, and its structural schematic diagram is as Figure 1 shown. Specifically, it includes an HBM chip 8 and an SOC chip 4 stacked vertically on a glass substrate 1. Microchannels are provided on one side of both the HBM chip 8 and the SOC chip 4. The glass substrate 1 is provided with a substrate microchannel 11 for coolant to flow through, and the substrate microchannel 11 communicates with the microchannels of the HBM chip 8 and the SOC chip 4.

[0022] To achieve the above structure, the FCBGA package specifically includes: a first glass-based interposer 2, a second glass-based interposer 3, and a glass substrate 1.

[0023] As Figures 2-3 shown, the first glass-based interposer 2 has an SOC chip 4 embedded in it. Redistribution layers 5 are provided on the front and back of the SOC chip 4 respectively, and the redistribution layers 5 are interconnected. Microbumps 6 are provided on the redistribution layers 5. A first microchannel 7 is provided between the back of the SOC chip 4 and the redistribution layer 5.

[0024] When specifically manufacturing the first glass-based interposer 2, its flowchart is as Figure 2 shown. The first glass-based interposer 2 is divided into a bonded first base glass layer 201 and a first top glass layer 202. As Figure 2 shown in a, the structures are all made of glass materials. As Figure 2 shown in b, before bonding, first form the first microchannel 7 on the first base glass layer 201 through drilling or etching technology, form a first chip pre-placement cavity 401 on the first top glass layer 202 through drilling or etching technology, and then bond the first base glass layer 201 and the first top glass layer 202. Multiple through-holes are formed at the same position of the bonded first base glass layer 201 and the first top glass layer 202 through drilling or etching technology, and a conductive layer is made in the through-holes to form a first conductive through-hole 203. Finally, prepare an inlet and an outlet at both ends of the first microchannel 7 through drilling or etching technology, and the inlet 701 and the outlet 702 of the first microchannel penetrate the first glass-based interposer 2.

[0025] After that, as Figure 3 shown in 3a - 3c, embed the SOC chip 4 in the first chip pre-placement cavity 401. Redistribution layers 5 are provided on the front and back of the SOC chip 4 respectively, and the redistribution layers 5 are interconnected through the first conductive through-hole 203. Microbumps 6 are provided on the redistribution layers 5, and the first microchannel 7 is between the back of the SOC chip 4 and the redistribution layer 5.

[0026] As Figure 4As shown, the second glass-based interposer 3 has an HBM chip 8 embedded therein. A passivation layer 9 and microbumps 6 are provided on the front side of the HBM chip 8, and a second microchannel 10 is provided on the back side of the HBM chip 8.

[0027] When specifically fabricating the second glass-based interposer 3, its flowchart is as shown in Figure 4 Figures 4a - 4d. The second glass-based interposer 3 is also divided into a bonded second base glass layer 301 and a second top glass layer 302. Before bonding, the second microchannel 10 is formed on the second base glass layer 301 by drilling or etching techniques, and a second chip pre-set cavity 801 is formed on the second top glass layer 302 by drilling or etching techniques. Then, the second base glass layer 301 and the second top glass layer 302 are bonded. Finally, an inlet 1001 and an outlet 1002 are fabricated at both ends of the second microchannel 10 by drilling or etching techniques. The inlet and outlet of the second microchannel 10 only penetrate the second top glass layer 302.

[0028] After that, a flip-chip HBM chip 8 is embedded in the second chip pre-set cavity 801. A passivation layer 9 and microbumps 6 are provided on the front side of the HBM chip 8, and the back side of the HBM chip 8 is close to the second microchannel 10. Extended inlets 1001 and outlets 1002 are fabricated by electroplating at both ends of the second microchannel 10.

[0029] As shown in Figure 5 Figure 5, the glass substrate 1 is provided with a circuit layer 12, a substrate microchannel 11, and a substrate conductive via 103. The substrate microchannel 11 includes a first substrate microchannel 1101 and a second substrate microchannel 1102. The first substrate microchannel 1101 forms a first inlet 1103 on the front side of the glass substrate 1 and a second inlet 1104 on the back side of the glass substrate 1. The second substrate microchannel 1102 forms a first outlet 1105 on the front side of the glass substrate 1 and a second outlet 1106 on the back side of the glass substrate 1.

[0030] When specifically fabricating the glass substrate 1, as shown in Figure 5 Figure 6a, the glass substrate 1 is also divided into a bonded third base glass layer 101 and a third top glass layer 102. Before bonding, the substrate microchannel 11 is formed on the third base glass layer 101 by drilling or etching techniques. The substrate microchannel 11 includes a first substrate microchannel 1101 and a second substrate microchannel 1102 that are symmetrically arranged left and right. Then, the third base glass layer 101 and the third top glass layer 102 are bonded, as shown in Figure 5 Figure 6b. A plurality of through holes are formed at the same positions of the bonded third base glass layer 101 and the third top glass layer 102 by drilling or etching techniques. A conductive layer is fabricated in the through holes by a deposition process to form the substrate conductive via 103, as shown in Figure 5As shown in Figure c. A circuit layer 12 is formed within the bonded third substrate glass layer 101 and third top glass layer 102. Through drilling or etching techniques, a first substrate microchannel 1101 forms a first inlet 1103 on the front side of the glass substrate 1 and a second inlet 1104 on the back side of the glass substrate 1; a second substrate microchannel 1102 forms a first outlet 1105 on the front side of the glass substrate 1 and a second outlet 1106 on the back side of the glass substrate 1, as Figure 5 shown in Figure d.

[0031] After that, as Figure 6 shown in Figures 6a and 6b, the second glass-based interposer 3 is flipped and placed on the front side of the SOC chip 4 of the first glass-based interposer 2. The inlet 1001 of the second microchannel 10 is in communication with the inlet 701 of the first microchannel 7, and the outlet of the second microchannel 10 is in communication with the outlet of the first microchannel 7.

[0032] After connection, as Figure 7 shown, an insulating material is filled in the microbump 6 region on the front side of the HBM chip 8, and a molding layer 13 is formed around the second glass-based interposer 3 with its upper surface exposed. The material used for the molding layer 13 is an epoxy molding compound to form a molded wafer; then the entire wafer is thinned through a grinding process until the surface of the second substrate glass layer 301 is exposed, forming the combined entire wafer.

[0033] Finally, as Figure 8 shown, the aforementioned entire wafer is diced into individual chips and then flip-chip mounted one by one on the front side of the glass substrate 1 according to the map. The inlet of the first microchannel 7 is in communication with the first inlet 1103 of the first substrate microchannel 1101 in the substrate microchannel 11, and the outlet of the first microchannel 7 is in communication with the first outlet 1105 of the second substrate microchannel 1102 in the substrate microchannel 11.

[0034] Then an insulating material is filled in the redistribution layer 5 and microbump 6 regions on the back side of the SOC chip 4, a capacitor 14 is mounted on the front side of the glass substrate 1 through SMT technology, and then a heat sink cover 15 is installed. The heat sink cover 15 covers the front sides of the first glass-based interposer 2, the second glass-based interposer 3, the capacitor 14, and the glass substrate 1. Finally, balls are implanted on the back side of the glass substrate 1 to form the structure of the FCBGA package as Figure 1 shown.

[0035] During the preparation process of the FCBGA package, the inlet of the second microchannel 10 is in communication with the inlet of the first microchannel 7 and the first inlet 1103 of the substrate microchannel 11, and the outlet of the second microchannel 10 is in communication with the outlet of the first microchannel 7 and the first outlet 1105 of the substrate microchannel 11, forming a cooling channel through which a coolant passes.

[0036] During the specific implementation process, the position of the first microchannel 7 is set at the center of the SOC chip 4, and the position of the second microchannel 10 is set at the center of the HBM chip 8. In this way, when the package is working, the coolant in the first microchannel 7 and the second microchannel 10 can directly take away the internal heat, achieving fast and effective heat dissipation. The substrate microchannel 11 is also set in the middle position. Of course, multiple microchannels can also be set according to actual needs to assist in heat dissipation.

[0037] In this embodiment, the settings of the first microchannel 7, the second microchannel 10, and the substrate microchannel 11 directly and maximally help the working HBM chip 8 and SOC chip 4 to dissipate heat, improving the heat dissipation effect of the package and the working performance of high-performance chips.

[0038] In this embodiment, through the technology of setting through holes on the glass substrate, 3D vertical interconnection of chips is realized, which can achieve face-to-face 3D vertical interconnection of chips at a relatively low cost, realize an ultra-short transmission path between chips, improve the 3D vertical interconnection density and transmission rate, reduce signal delay, reduce the package volume, and meet the high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic devices.

[0039] Embodiment 2: Stacked packaging structure with an FCBGA package The stacked packaging structure disclosed in this embodiment is to weld the FCBGA package in Embodiment 1 on the PCB board 16. The PCB board 16 in this embodiment is as Figure 9 shown, and is provided with a coolant inlet 1601 and a coolant outlet 1602. After installing the FCBGA package, the coolant inlet 1601 communicates with the second inlet 1104 on the back of the glass substrate 1 of the FCBGA package, and the coolant outlet 1602 communicates with the second outlet 1106 on the back of the glass substrate 1.

[0040] Specifically, as Figure 10 shown, the coolant inlet 1601 and the coolant outlet 1602 are arranged on the left and right sides of the PCB board 16. The coolant inlet 1601 extends along the through hole to the first opposed opening 1603. The coolant inlet 1601 communicates with an external circulation pump body (not shown in the figure), and the first opposed opening 1603 communicates with the second inlet 1104 on the back of the glass substrate 1; the coolant outlet 1602 extends along the through hole to the second opposed opening 1604. The coolant outlet 1602 communicates with the external circulation pump body, and the second opposed opening 1604 communicates with the second outlet 1106 on the back of the glass substrate 1.

[0041] In the stacked package structure, the external circulation pump body causes the coolant to be introduced from the coolant inlet 1601 into the second inlet 1104 on the back of the glass substrate 1, flow into the cooling channels in the FCBGA package body, and finally flow out from the second outlet 1106 on the back of the glass substrate 1 and out from the coolant outlet 1602. The flow channel of the coolant is as shown in the schematic diagram of the red line with arrows in Figure 9 Figure Figure 9 .

[0042] In this embodiment, microchannels are fabricated in the first glass-based interposer 2, the second glass-based interposer 3, and the glass substrate 1. The microchannels are connected and pass through the entire 3D package. The microchannels are in direct contact with the back of each chip, and the liquid cooling heat dissipation directly cools the chips at the middle position of the 3D package, improving the heat dissipation capacity of the package, thereby improving the chip performance, meeting the chip design and packaging requirements of high-frequency and high-speed electronic devices with ultra-high density and high heat generation, and improving the working performance of high-performance chips.

[0043] The above are only some embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the creative concept of the present invention, other deformations and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. A FCBGA package, characterized in that: It comprises an HBM chip and a SOC chip stacked vertically on a glass substrate, wherein one side of the HBM chip and the SOC chip are both provided with a microchannel, the glass substrate is provided with a substrate microchannel for cooling liquid to flow through, and the substrate microchannel is connected with the microchannels of the HBM chip and the SOC chip.

2. The FCBGA package according to claim 1, characterized in that: The FCBGA package specifically includes: A first glass-based interposer is embedded with a SOC chip, a front side and a back side of the SOC chip are respectively provided with redistribution layers, the redistribution layers are interconnected, micro-bumps are arranged on the redistribution layers, and a first microchannel is arranged between the back side of the SOC chip and the redistribution layers; A second glass-based interposer is embedded with an HBM chip, a passivation layer and micro-bumps are provided on the front side of the HBM chip, and a second micro-channel is provided on the back side of the HBM chip; A glass substrate is provided with a circuit layer, a substrate microchannel and a substrate conductive through hole; the substrate microchannel includes a first substrate microchannel and a second substrate microchannel, the first substrate microchannel forms a first inlet on the front side of the glass substrate and a second inlet on the back side of the glass substrate; the second substrate microchannel forms a first outlet on the front side of the glass substrate and a second outlet on the back side of the glass substrate; in, The second glass-based interposer is flipped onto the front side of the SOC chip of the first glass-based interposer, and then flipped onto the front side of the glass substrate, capacitors are mounted on the front side of the glass substrate, and balls are planted on the back side of the glass substrate to form an FCBGA package; In the FCBGA package, the inlet of the second microchannel is connected to the inlet of the first microchannel and the first inlet of the substrate microchannel, and the outlet of the second microchannel is connected to the outlet of the first microchannel and the first outlet of the substrate microchannel to form a cooling channel.

3. The FCBGA package according to claim 2, characterized in that: It also includes a heat dissipation cover arranged on the front side of the glass substrate, wherein the heat dissipation cover covers the first glass-based intermediate layer, the second glass-based intermediate layer, the capacitor and the front side of the glass substrate.

4. A stacked package structure, characterized in that: The FCBGA package according to any one of claims 1 to 3 is welded on a PCB board, the PCB board is provided with a coolant inlet and a coolant outlet, the coolant inlet is connected to the second inlet on the back of the glass substrate, and the coolant outlet is connected to the second outlet on the back of the glass substrate.

5. A method for preparing a package-on-package structure as claimed in claim 4, characterized in that: The following steps are involved: S1, forming a first microchannel, a first chip pre-cavity and a first conductive through hole in a first glass-based interposer, embedding a SOC chip in the first chip pre-cavity, respectively providing redistribution layers on the front and back of the SOC chip, interconnecting the redistribution layers through the first conductive through hole, providing microbumps on the redistribution layers, and providing the first microchannel between the back of the SOC chip and the redistribution layers; S2, forming a second microchannel and a second chip pre-cavity in the second glass-based interposer, embedding a normal-mounted HBM chip in the second chip pre-cavity, with a passivation layer and micro-bumps on the front of the HBM chip, and the back of the HBM chip close to the second microchannel; S3, forming a circuit layer, a substrate microchannel and a substrate conductive through hole in the glass substrate; the substrate microchannel includes a first substrate microchannel and a second substrate microchannel, the first substrate microchannel forms a first inlet on the front side of the glass substrate and a second inlet on the back side of the glass substrate; the second substrate microchannel forms a first outlet on the front side of the glass substrate and a second outlet on the back side of the glass substrate; S4, after flipping the second glass-based interposer in S2 on the front side of the SOC chip of the first glass-based interposer in S1, the whole is flipped on the front side of the glass substrate, a capacitor is mounted on the front side of the glass substrate, and a ball is planted on the back side of the glass substrate to form an FCBGA package; In the FCBGA package, the inlet of the second microchannel is connected to the inlet of the first microchannel and the first inlet of the substrate microchannel, and the outlet of the second microchannel is connected to the outlet of the first microchannel and the first outlet of the substrate microchannel to form a cooling channel; S5, soldering the FCBGA package of step S4 onto a PCB board, wherein the PCB board is provided with a coolant inlet and a coolant outlet, wherein the coolant inlet is connected to a second inlet on the back side of the glass substrate, and the coolant outlet is connected to a second outlet on the back side of the glass substrate.

6. The method according to claim 5, characterized in that The first glass-based intermediary layer, the second glass-based intermediary layer and the glass substrate are all made of glass.

7. The method according to claim 6, characterized in that In step S1, the first glass-based intermediate layer is divided into a bonded first base glass layer and a first top glass layer, the first base glass layer is provided with a first microchannel, the first top glass layer is provided with a first chip pre-cavity, and a first conductive through hole is formed at the same position of the first base glass layer and the first top glass layer.

8. The method according to claim 7, characterized in that In step S2, the second glass-based interposer is divided into a bonded second base glass layer and a second top glass layer, the second base glass layer is provided with a second microchannel, and the second top glass layer is provided with a first chip pre-cavity.

9. The method according to claim 7, characterized in that: In step S4, after the second glass-based interposer is flipped on the front side of the SOC chip of the first glass-based interposer, the micro-bump area on the front side of the HBM chip is filled with insulating material, a plastic sealing layer is formed around the second glass-based interposer and its upper surface is exposed, and then it is cut into single chips and flipped on the front side of the glass substrate; Filling the redistribution layer and micro-bump area on the back of the SOC chip with insulating material; After mounting the capacitor on the front side of the glass substrate, a heat dissipation cover is installed, which covers the first glass-based interposer, the second glass-based interposer, the capacitor and the front side of the glass substrate, and finally a ball is planted on the back side of the glass substrate to form an FCBGA package.

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