High-withstand-voltage low-loss super-junction IGBT device and manufacturing method thereof

Abstract

The invention provides a high-withstand-voltage low-loss super-junction IGBT device and a manufacturing method thereof.According to the device, a trench gate is arranged between a P column and a P region, the P column is prevented from being directly connected with the P region and an emitting electrode, the hole extraction effect in the conduction state is eliminated, meanwhile, a PMOS structure with a gate source short circuit is introduced, in the turn-off process, the PMOS structure is conducted to form a hole extraction channel, and therefore the hole extraction effect is improved. Extraction of excess carriers is accelerated, and turn-off loss is reduced. The manufacturing method comprises the steps of forming an N-type substrate, extending an N-type drift region, etching a P-type column region trench, filling P-type doped silicon, forming a P-body region, etching a gate trench, growing a gate oxide layer, depositing polycrystalline silicon, forming a contact region through ion implantation, forming an N-type implantation layer and a P region through extension, growing an emitter oxide layer, and forming a P + collector region through ion implantation. And depositing metal to manufacture an emitter and a collector, and the like. The device shows excellent performance in both on and off states, the on-voltage drop is reduced, the off loss is reduced by 15%, and the device has a good application prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and particularly relates to a high-voltage-resistant and low-loss superjunction IGBT device and a manufacturing method thereof. Background Art

[0002] In power devices, there is a proportional relationship limitation between the breakdown voltage and the on-resistance, which is usually referred to as the "silicon limit". To break this limitation, the superjunction theory was proposed. This theory optimizes the electric field distribution by introducing a structure with alternating N-columns and P-columns inside the drift region, and utilizes the lateral depletion effect of the N-columns and P-columns to achieve higher breakdown voltage performance. The superjunction structure was initially applied to MOSFETs, forming superjunction MOS devices. This structure not only improves the forward conduction characteristics, but also reduces the chip area and increases the power density. Subsequently, the superjunction theory was also applied to IGBTs, forming superjunction IGBTs.

[0003] The structure of traditional superjunction IGBT devices is similar to that of superjunction MOS, where the P-columns are directly connected to the P-region. Different from superjunction MOS, in superjunction IGBTs during operation, both electrons and holes participate in carrier transport. During the carrier transport process, holes, as minority carriers, are injected from the collector into the N-column region and are easily extracted by the P-columns, and then flow into the emitter through the P-region. Due to the existence of the hole extraction path formed by the P-columns and the P-region, the hole storage effect in the drift region of superjunction IGBTs during conduction is weak, resulting in the conductance modulation effect in the drift region not reaching the expected level, and thus the on-state voltage drop is large.

[0004] Compared with the traditional superjunction IGBT structure, the existing superjunction IGBT structure adopts a floating P-column design and introduces a highly doped N-type injection layer above the drift region to separate the P-columns from the P-region, avoiding the direct connection between the P-columns and the P-region (as Figure 1 shown). This design can prevent the holes in the drift region from being extracted to the emitter through the P-region during the on-state, thereby improving the conductance modulation effect in the drift region and enhancing the overall performance of the device. However, due to the existence of the floating P-columns, during turn-off, the holes in the P-column region cannot be extracted by the emitter and can only be eliminated through recombination. This not only prolongs the turn-off time of the device but also increases the loss. Summary of the Invention

[0005] To solve the above technical problems, the present invention disposes a trench gate between the P-columns and the P-region to prevent the direct connection between the P-columns and the P-region and the emitter, and eliminates the extraction effect of holes through the P-columns and the P-body during the on-state. Additionally, an emitter, an N-type injection layer, and a P-region are introduced above the P-body region on the left side of the trench gate to jointly form a PMOS structure with shorted gate and source.

[0006] To achieve the above object, a high-voltage withstand and low-loss superjunction IGBT device structure provided by the present invention includes: a collector metal, a P+ collector region, and an N-type field stop layer sequentially arranged from bottom to top. Above the N-type field stop layer, there are superjunction N-type columns and superjunction P-type columns. Above the superjunction N-type columns and superjunction P-type columns, there is a first trench structure, and the first trench structure includes a gate oxide layer and a gate electrode; above the superjunction N-type columns and superjunction P-type columns, there is a P-body region; above the right side of the P-body region, there are an N+ emitter region and a P+ emitter region; above the left side of the P-body region, there are an N-type implantation layer and a P region; on the right side of the N-type implantation layer and the P region, there is an oxide layer, and on the left side, there is a second trench structure, and the second trench structure includes an oxide layer and an emitter, jointly constituting a PMOS structure with shorted gate and source.

[0007] Preferably, the depth of the gate electrode is greater than the junction depth of the P-body region.

[0008] Preferably, the superjunction N-type columns and superjunction P-type columns meet the charge balance requirement.

[0009] Preferably, the thickness of the oxide layer is adjustable to control the channel turn-on voltage of the PMOS structure.

[0010] The present invention also provides a manufacturing method of a high-voltage withstand and low-loss superjunction IGBT device, including the following steps:

[0011] S1, using an N-type doped single-crystal silicon wafer as a substrate to form an N-type substrate;

[0012] S2, through an epitaxial process, an N-type drift region is epitaxially formed above the N-type field stop layer 1;

[0013] S3, depositing, photolithographing, and etching on the surface of the silicon wafer to etch out a P-type column region trench;

[0014] S4, epitaxially filling P-type doped silicon in the P-type column region trench, and then removing the excess P-type doped silicon by chemical mechanical polishing;

[0015] S5, epitaxially growing P-type silicon on the silicon wafer, and then reverse-etching the excess silicon on the surface to form a P-body region;

[0016] S6, protecting the surface of the silicon wafer, photolithographing a window and performing trench etching, and etching the depth of the gate trench to be 200 - 400 nm;

[0017] S7, growing a sacrificial oxide layer on the sidewalls of the trench in oxygen at 1050°C - 1150°C, then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewalls of the trench in oxygen at 1050°C - 1150°C;

[0018] S8. Deposit polysilicon to fill the gate trenches, remove the excess polysilicon outside the trenches by chemical mechanical planarization, grow an oxide layer on the top of the polysilicon inside the trenches, and then remove the excess oxide layer by chemical mechanical planarization;

[0019] S9. Obtain the N+ contact region by ion implanting N-type impurities, with the ion implantation energy being 60 - 100 keV and the ion implantation dose being 1014 - 1015 / cm 2 , obtain the P+ contact region by ion implanting P-type impurities, with the ion implantation energy being 50 - 100 keV and the ion implantation dose being 1014 - 1015 / cm 2 ;

[0020] S10. Oxidize to form an oxide layer, and perform photolithography and etching to create windows;

[0021] S11. Through the epitaxial process, epitaxially form an N-type implantation layer and a P region above the silicon wafer, and then remove the excess P-type doped silicon by chemical mechanical polishing;

[0022] S12. Perform photolithography and etching to create windows, and grow an emitter oxide layer on the sidewalls of the trenches in oxygen;

[0023] S13. Perform photolithography and etching to remove the excess emitter oxide layer;

[0024] S14. On the back side of the silicon wafer, ion implant P-type impurities to fabricate the P+ collector region, with the ion implantation energy being 50 - 100 keV and the ion implantation dose being 1012 - 1015 / cm 2 , and use laser annealing;

[0025] S15. Deposit metal on the front side of the device to fabricate the emitter metal, and deposit metal on the back side to fabricate the collector metal.

[0026] Preferably, in step S7, the thickness of the gate oxide layer is 100 - 200 nm.

[0027] Preferably, in step S8, the thickness of the excess polysilicon outside the trenches is 300 - 500 nm.

[0028] Preferably, in step S9, the N-type impurity is phosphorus and the P-type impurity is boron.

[0029] Preferably, in step S11, the doping concentration of the N-type implantation layer is 1016 - 1017 / cm 3 .

[0030] Preferably, in step S14, the temperature of the laser annealing is 1000°C - 1200°C and the time is 10 - 30 seconds.

[0031] Compared with the related technologies, a high-voltage withstand and low-loss superjunction IGBT device and a manufacturing method thereof provided by the present invention have the following beneficial effects:

[0032] By adjusting the position of the trench gate, the P-body and the P-type columns are made floating. This design prevents the direct extraction of holes in the P-type columns in the on state, and a strong conductivity modulation effect occurs in the drift region, reducing the on-state voltage drop. At the same time, by using the PMOS structure with the gate-source short-circuited, in the off state, the inversion of the N-type injection layer causes the parasitic PMOS to turn on, accelerating the extraction of excess carriers in the P-body and the P-type columns and reducing the off time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of the half-cell structure of an existing superjunction IGBT device;

[0034] Figure 2 is a schematic diagram of the half-cell structure of a high-voltage withstand and low-loss superjunction IGBT device proposed by the present invention;

[0035] Figure 3 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming an N-type substrate;

[0036] Figure 4 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming an N-type drift region;

[0037] Figure 5 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after etching the trench in the P-type column region;

[0038] Figure 6 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming the P-type column;

[0039] Figure 7 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming the P-body region;

[0040] Figure 8 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming the gate trench;

[0041] Figure 9 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming the gate oxide layer;

[0042] Figure 10 is a process schematic diagram of a high-voltage withstand and low-loss superjunction IGBT of the present invention after forming the polysilicon gate;

[0043] Figure 11Schematic diagram of the process after forming the P+ contact region and the N+ contact region of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0044] Figure 12 Schematic diagram of the process after forming the oxide layer of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0045] Figure 13 Schematic diagram of the process after forming the N-type injection layer and the P region of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0046] Figure 14 Schematic diagram of the process after forming the emitter oxide layer of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0047] Figure 15 Schematic diagram of the process after removing the redundant emitter oxide layer of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0048] Figure 16 Schematic diagram of the process after forming the P+ collector region of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0049] Figure 17 Schematic diagram of the process after forming the metal collector and the metal emitter of a high-voltage withstand and low-loss superjunction IGBT according to the present invention;

[0050] Figure 18 For Figure 1 The existing structure (ST_1) and Figure 2 Comparison diagram of the simulated turn-off waveforms of the new structure (ST_2) of the present invention;

[0051] Figure 19 Internal current distribution of the new structure (ST_2) of the present invention at different times during the turn-off process;

[0052] Figure 20 For Figure 1 The existing structure (ST_1) and Figure 2 Trade-off relationship diagram of the simulated on-state saturation voltage Vcesat and the turn-off loss Eoff of the new structure (ST_2) of the present invention. Detailed implementation mode

[0053] The following combines the attached Figure 1 To the attached Figure 20 Make a further detailed description of the present invention:

[0054] A high-voltage withstand and low-loss superjunction IGBT device structure provided by the present invention, such as Figure 2As shown in the figure, it includes: collector metal 14, P+ collector region 13, and N-type field stop layer 1 arranged successively from bottom to top. Above the N-type field stop layer 1, there are superjunction N-type columns 2 and superjunction P-type columns 3. Above the superjunction N-type columns 2 and superjunction P-type columns, there is a first trench structure, and the first trench structure includes a gate oxide layer 5 and a gate electrode 6. Above the superjunction N-type columns 2 and superjunction P-type columns, there is a P-body region 4. Above the right side of the P-body region 4, there are an N+ emitter region 8 and a P+ emitter region 7. Above the left side of the P-body region 4, there are an N-type implantation layer 10 and a P region 11. On the right side of the N-type implantation layer 10 and the P region 11, there is an oxide layer 9, and on the left side, there is a second trench structure, and the second trench structure includes an oxide layer 12 and an emitter 15, which together form a PMOS structure with shorted gate and source.

[0055] In this embodiment, the depth of the gate electrode 6 is greater than the junction depth of the P-body region 4.

[0056] The superjunction N-type columns 2 and superjunction P-type columns 3 meet the charge balance requirement.

[0057] The thickness of the oxide layer 12 is adjustable to control the channel turn-on voltage of the PMOS structure.

[0058] The working principle of the present invention:

[0059] When the collector metal 14 of the device is connected to a high potential, the emitter metal 15 is connected to a low potential, and a high potential is applied to the gate electrode 6, the device operates in the on state. At this time, the parasitic PMOS structure is in the off state, the left P-body region 4 and the P-type column 3 in the drift region are in a floating state, and the N-type implantation layer 10 acts as a hole barrier. This enables the hole concentration in the left P-body region 4 and the P-type column 3 to be increased, thereby enhancing the conductance modulation ability of the drift region when the device is on, and thus optimizing the electrical performance of this structure in the forward on state. When the collector metal 14 of the device is connected to a high potential, the emitter metal 15 is connected to a low potential, and a low potential is applied to the gate electrode 6, the device enters the off process. At this time, the potentials of the floating left P-body region 4, the P-type column 3, and the P region 11 above the N-type implantation layer 10 will gradually increase. When the potential reaches the threshold voltage of the parasitic PMOS, the N-type implantation layer 10 will undergo an inversion phenomenon, and the PMOS structure will conduct accordingly. During the off process, a hole path is formed from the P-type column 3, through the left P-body region 4, the N-type implantation layer 10, the P region 11 to the emitter 15, effectively accelerating the extraction of excess carriers in the left P-body region 4 and the P-type column 3, and thus accelerating the turn-off speed of the device.

[0060] This embodiment also provides a manufacturing method for a high-voltage-resistant and low-loss superjunction IGBT device, including the following steps:

[0061] Step S1, asFigure 3 As shown, an N-type doped single-crystalline silicon wafer is used as a substrate to form an N-type substrate;

[0062] Step S2, as Figure 4 shown, an N-type drift region is epitaxially formed above the N-type field stop layer through an epitaxial process;

[0063] Step S3, as Figure 5 shown, deposition, photolithography, and etching are performed on the surface of the silicon wafer to etch out a P-type column region trench;

[0064] Step S4, as Figure 6 shown, P-type doped silicon is epitaxially filled in the P-type column region trench, and then the excess P-type doped silicon is removed by chemical mechanical polishing;

[0065] Step S5, as Figure 7 shown, P-type silicon is epitaxially grown on the silicon wafer, and then the excess silicon on the surface is etched back to form a P-body region;

[0066] Step S6, as Figure 8 shown, the surface of the silicon wafer is protected, a window is lithographed and trench etching is performed to etch out a gate trench, and the depth of the gate trench is 260 nm;

[0067] Step S7, as Figure 9 shown, a sacrificial oxide layer is grown on the sidewalls of the trench in oxygen at 1050 °C to 1150 °C, then the sacrificial oxide layer is removed, and then a gate oxide layer is grown on the sidewalls of the trench in oxygen at 1050 °C to 1150 °C, and the thickness of the gate oxide layer is 120 nm;

[0068] Step S8, as Figure 10 shown, polysilicon is deposited to fill the gate trench, the excess polysilicon outside the trench is removed by chemical mechanical planarization, an oxide layer is grown on the top of the polysilicon in the trench, and then the excess oxide layer is removed by chemical mechanical planarization; the thickness of the excess polysilicon outside the trench is 400 nm.

[0069] Step S9, as Figure 11 shown, an N+ contact region is obtained by ion implantation of N-type impurities, the ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , a P+ contact region is obtained by ion implantation of P-type impurities, the ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; the N-type impurity is phosphorus, and the P-type impurity is boron;

[0070] Step S10, asFigure 12 As shown, an oxide layer is formed by oxidation, and windows are formed through photolithography and etching;

[0071] Step S11, as Figure 13 shown, through an epitaxial process, an N-type implantation layer and a P region are epitaxially formed above the silicon wafer, and then the excess P-type doped silicon is removed by chemical mechanical polishing. The doping concentration of the N-type implantation layer is 2*10 16 / cm 3 ;

[0072] Step S12, as Figure 14 shown, through photolithography and etching, windows are formed, and an emitter oxide layer is grown on the sidewalls of the trenches in oxygen;

[0073] Step S13, as Figure 15 shown, through photolithography and etching, the excess emitter oxide layer is removed;

[0074] Step S14, as Figure 16 shown, on the back of the silicon wafer, P-type impurities are implanted to form a P+ collector region. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 , and laser annealing is adopted. The temperature of the laser annealing is 1000°C - 1200°C, and the time is 10 - 30 seconds;

[0075] Step S15, as Figure 17 shown, metal is deposited on the front of the device to make the emitter metal, and metal is deposited on the back to make the collector metal.

[0076] To verify the improvement of the present invention, Figures 18 to 20 shows Figure 1 the simulation comparison diagram between the existing structure (ST_1) and Figure 2 the new structure (ST_2) of the present invention.

[0077] Figure 18 For Figure 1 the simulation turn-off waveform comparison diagram between the existing structure (ST_1) and Figure 2 the new structure (ST_2) of the present invention, the external gate voltage before turn-off is 15V. As can be seen from Figure 18 the figure, when the externally applied control gate signal drops from 15V to 0V, both the Ic and Vc of the new structure (ST_2) of the present invention drop and turn off earlier than those of the existing structure (ST_1). Due to the inversion of the N-type implantation layer in the new structure (ST_2) of the present invention, when the parasitic PMOS reaches the threshold voltage, an additional hole extraction channel is formed. Therefore, compared with the existing structure (ST_1), the turn-off speed of the device can be increased.

[0078] Figure 19 ForFigure 2 Internal current distribution of the new structure (ST_2) of the present invention at different times during the turn-off process. (a) shows the time T = 3.005e-5 s, (b) shows the time T = 3.016e-5 s, (c) shows the time T = 3.020e-5 s, and (d) shows the time T = 3.025e-5 s.

[0079] When the device is turned on, as Figure 19 (a) shows, at T = 3.005e-5 s, the parasitic PMOS is in the off state, and the current path inside the device is collector - N-type field stop layer - N-type column region and P-type column region - P region - emitter. When the gate voltage of the device starts to decrease, the parasitic PMOS channel starts to invert. As Figure 19 (b) shows, at T = 3.016e-5 s, part of the current flows from the drift region through the PMOS to the emitter. When the time further progresses, the PMOS is fully turned on. As Figure 19 (c) shows, at T = 3.020e-5 s, a large number of excess carriers in the drift region are transported to the emitter through the hole extraction path formed by the PMOS, which speeds up the turn-off speed of the APMT-SJ-IGBT device and reduces the turn-off loss of this structure. After turn-off, as Figure 19 (d) shows, at T = 3.025e-5 s.

[0080] Figure 20 For Figure 1 the existing structure (ST_1) and Figure 2 the trade-off relationship diagram of the simulated on-state saturation voltage Vcesat and turn-off loss Eoff of the new structure (ST_2) of the present invention. The turn-on current density is 200 A / cm 2 It can be seen from the figure that the new structure (ST_2) of the present invention has a better trade-off relationship between on-state voltage drop and turn-off loss than the existing structure (ST_1). Under the same Von, compared with the existing structure (ST_1), the Eoff of the new structure (ST_2) of the present invention is reduced by 15%.

[0081] In the prior art, the superjunction IGBT device has the problem of relatively large turn-off loss. For example, Figure 1 when the existing structure (ST_1) is turned off, the holes in the P column cannot be effectively extracted, which prolongs the turn-off time and increases the loss.

[0082] Compared with the prior art, the present invention blocks the direct extraction of holes by arranging trench gates between the P column and the P region, significantly enhancing the conductivity modulation ability of the drift region. At the same time, a PMOS structure with gate-source short-circuit is introduced to form a hole extraction path during turn-off, accelerating the extraction of excess carriers and reducing the turn-off loss.

[0083] The above are only embodiments of the present invention, and do not thus limit the patent scope of the present invention. Any equivalent structural or equivalent process transformations made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A high withstand voltage and low loss super junction IGBT device, characterized in that: include: A collector metal, a P+ collector region, and an N-type field stop layer are arranged in sequence from bottom to top; a super junction N-type column and a super junction P-type column are arranged above the N-type field stop layer; a first trench structure is located above the super junction N-type column and the super junction P-type column, and the first trench structure includes a gate oxide layer and a gate electrode; a P-body region is arranged above the super junction N-type column and the super junction P-type column; an N+ emitter region and a P+ emitter region are arranged above the right side of the P-body region; an N-type injection layer and a P region are arranged above the left side of the P-body region; the right side of the N-type injection layer and the P region is an oxide layer, and the left side is a second trench structure, and the second trench structure includes an oxide layer and an emitter, which together constitute a PMOS structure with a gate-source short circuit.

2. A high withstand voltage and low loss super junction IGBT device according to claim 1, characterized in that: The depth of the gate electrode is greater than the junction depth of the P-body region.

3. The high withstand voltage and low loss super junction IGBT device according to claim 1, characterized in that: The super junction N-type column and the super junction P-type column meet the charge balance requirement.

4. The high withstand voltage and low loss super junction IGBT device according to claim 1, characterized in that: The thickness of the oxide layer can be adjusted to control the channel turn-on voltage of the PMOS structure.

5. A method for manufacturing a high-voltage and low-loss super-junction IGBT device, characterized in that: The following steps are involved: S1, using an N-type doped single crystal silicon wafer as a substrate to form an N-type substrate; S2, epitaxially forming an N-type drift region on the N-type field stop layer 1 through an epitaxial process; S3, performing deposition, photolithography, and etching on the surface of the silicon wafer to etch out a P-type column region groove; S4, epitaxially filling the P-type column region trench with P-type doped silicon, and then removing excess P-type doped silicon by chemical mechanical polishing; S5, epitaxially growing P-type silicon on the silicon wafer, and then reverse-etching the excess silicon on the surface to form a P-body region; S6, protecting the surface of the silicon wafer, photolithography a window and performing trench etching, and etching the gate trench to a depth of 200 to 400 nm; S7, growing a sacrificial oxide layer on the sidewall of the trench in oxygen at 1050° C. to 1150° C., then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewall of the trench in oxygen at 1050° C. to 1150° C.; S8, depositing polysilicon to fill the gate trench, removing excess polysilicon outside the trench by chemical mechanical planarization, growing an oxide layer on top of the polysilicon in the trench, and then removing excess oxide layer by chemical mechanical planarization; S9, N+ contact region is obtained by ion implantation of N-type impurities, the ion implantation energy is 60-100 keV, and the ion implantation dose is 1014-1015 / cm 2 , ion implantation of P-type impurities to obtain P+ contact area, ion implantation energy is 50-100 keV, ion implantation dose is 1014-1015 / cm 2 ; S10, oxidation to form an oxide layer, and photolithography and etching to form a window; S11, epitaxially forming an N-type implantation layer and a P region on the silicon wafer through an epitaxial process, and then removing excess P-type doped silicon through chemical mechanical polishing; S12, after photolithography and etching of windows, an emitter oxide layer is grown on the sidewalls of the trench in oxygen; S13, photolithography and etching of the redundant emitter oxide layer; S14, on the back side of the silicon wafer, ion implantation of P-type impurities is performed to obtain a P+ collector region, the ion implantation energy is 50-100 keV, and the ion implantation dose is 1012-1015 / cm 2 , laser annealing is used; S15, depositing metal on the front side of the device to make an emitter metal, and depositing metal on the back side of the device to make a collector metal.

6. The method for manufacturing a high-voltage and low-loss super junction IGBT device according to claim 5, characterized in that: In step S7, the thickness of the sacrificial oxide layer is 100-200 nm.

7. The method for manufacturing a high-voltage and low-loss super junction IGBT device according to claim 5, characterized in that: In step S8, the thickness of the excess polysilicon outside the trench is 300-500 nm.

8. The method for manufacturing a high-voltage and low-loss super junction IGBT device according to claim 5, characterized in that: In step S9, the N-type impurity is phosphorus, and the P-type impurity is boron.

9. The method for manufacturing a high-voltage and low-loss super junction IGBT device according to claim 5, characterized in that: In step S11, the doping concentration of the N-type injection layer is 1016-1017 / cm 3 .

10. The method for manufacturing a high-voltage and low-loss super junction IGBT device according to claim 5, characterized in that: In step S14, the laser annealing is performed at a temperature of 1000° C. to 1200° C. for a time of 10 to 30 seconds.

Images