Power semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a power semiconductor device, comprising: a substrate including a first substrate, an insulating buried layer, and a second substrate, the insulating buried layer being located between the first substrate and the second substrate, the second substrate including a first surface and a second surface opposite to the first surface; a drift region provided in the second substrate and extending from the first surface into the second substrate, the drift region having a first conductivity type; a trench gate structure and a trench drain structure, the trench gate structure and the trench drain structure being spaced apart in a second direction in the drift region, both the trench gate structure and the trench drain structure extending from the first surface into the second substrate, a first direction and the second direction being perpendicular; at least one first trench isolation structure provided in the drift region and extending from the second surface into the second substrate to optimize the specific on-resistance of the device while increasing the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a lateral power semiconductor device and a method for preparing the same. Background Art

[0002] In the design of power semiconductor devices such as lateral double-diffused MOSFET (LDMOS), the coordinated optimization of breakdown voltage (BV) and specific on-resistance (Ronsp) is a key challenge to improve the performance of power semiconductor devices. From the perspective of the physical properties of power semiconductor devices, the enhancement of breakdown voltage usually requires increasing the drift region length or reducing the doping concentration, but this will lead to a significant increase in specific on-resistance, thus forming a classic proportional relationship between the two, Ronsp ∝ BV. 2.5 .

[0003] In order to break through this limitation, a composite structure of a trench gate (TG) structure and a trench drain (TD) structure has been introduced into the design of power semiconductor devices. The TG structure optimizes the carrier transport characteristics by enhancing the gate's ability to regulate the electric field in the drift region, while the TD structure uses three-dimensional electric field distribution to improve the withstand voltage characteristics, which can theoretically achieve a synergistic effect of Ronsp reduction and BV improvement. However, in practical applications, the introduction of the TD structure will cause new electric field concentration problems. Part of the drift region at the end of the trench drain structure (that is, part of the drift region of the trench drain structure facing the trench gate structure and close to the insulating buried layer of the substrate) will form a local electric field peak, causing the device to undergo avalanche breakdown before reaching the ideal breakdown voltage, ultimately limiting the overall breakdown voltage (VB) improvement effect of the device.

[0004] Therefore, how to alleviate the electric field concentration effect at the end of the trench-drain structure while maintaining the low specific on-resistance advantage of the TG-TD structure has become a core technical bottleneck that needs to be urgently solved in the field of power semiconductor devices. Summary of the invention

[0005] The present invention provides a power semiconductor device and a preparation method thereof, so as to solve the problem of how to improve the breakdown voltage of the device and optimize the specific on-resistance of the device at the same time.

[0006] In a first aspect, a power semiconductor device is provided, comprising:

[0007] A substrate, including a first substrate, an insulating buried layer, and a second substrate, the insulating buried layer being located between the first substrate and the second substrate, the second substrate including a first surface away from the insulating buried layer and a second surface opposite to the first surface, the first surface and the second surface being spaced apart in a first direction;

[0008] A drift region, the drift region being disposed in the second substrate and extending from the first surface into the second substrate, the drift region having a first conductivity type;

[0009] A trench gate structure and a trench drain structure, the trench gate structure and the trench drain structure being spaced apart in a second direction in the drift region, both the trench gate structure and the trench drain structure extending from the first surface into the second substrate, the first direction and the second direction being perpendicular;

[0010] At least one first trench isolation structure, the first trench isolation structure being disposed in the drift region and adjacent to the trench drain structure, and the first trench isolation structure extending from the second surface into the second substrate, in the second direction, the distance between the first trench isolation structure and the trench gate structure being greater than the distance between the first trench isolation structure and the trench drain structure.

[0011] In some embodiments of the present application, it further includes:

[0012] A source region, disposed between the trench gate structure and the trench drain structure and adjacent to the trench gate structure, and extending from the first surface into the drift region;

[0013] At least one second trench isolation structure, which is disposed in the drift region between the source region and the trench drain structure and extends from the first surface into the interior of the drift region.

[0014] In some embodiments of the present application, the projection of the first trench isolation structure on the second surface and the projection of the second trench isolation structure on the second surface partially overlap.

[0015] In some embodiments of the present application, in the first direction, there is a space between the bottom of the second trench isolation structure facing away from the first surface and the top of the first trench isolation structure facing away from the insulating buried layer; and / or

[0016] In the second direction, the distance between the second trench isolation structure and the trench gate structure is less than the distance between the second trench isolation structure and the trench drain structure.

[0017] In some embodiments of the present application, the drift region extends from the first surface to the second surface;

[0018] The trench-gate structure includes a gate trench and a gate electrode. The gate trench extends from the first surface to the insulating buried layer, and the gate electrode is disposed in the gate trench;

[0019] The trench-drain structure includes a drain trench, a drain electrode, and a drain region. The drain trench extends from the first surface to the insulating buried layer, the drain electrode is disposed in the drain trench, and the drain region is disposed in the drift region on the side of the trench-drain structure facing the trench-gate structure. The drain region is in contact connection with the drain electrode;

[0020] At least one of the first trench isolation structures is in contact with the drain region of the trench-drain structure, or there is a gap between the first trench isolation structure and the drain region of the trench-drain structure.

[0021] In some embodiments of the present application, it further includes:

[0022] A body region extends from the first surface into the drift region, and the body region is adjacent to the trench-gate structure. The body region has a second conductivity type;

[0023] Wherein, the distance between the top of the first trench isolation structure on the side away from the second surface and the first surface is greater than the depth of the body region.

[0024] In a second aspect, a method for manufacturing a power semiconductor device is provided, including:

[0025] Providing a first substrate, on the surface of which a first insulating buried layer is covered;

[0026] Providing a second substrate, the second substrate includes a first surface and a second surface which are oppositely arranged. At least one first trench is formed in the second substrate, and the first trench extends from the second surface into the second substrate. Wherein, the first surface and the second surface are spaced apart in a first direction;

[0027] Forming a second insulating buried layer to fill the first trench to form a first trench isolation structure, and the second insulating buried layer also covers the second surface of the second substrate;

[0028] Bonding the side of the second substrate formed with the second insulating buried layer and the side of the first substrate formed with the first insulating buried layer, and the first insulating buried layer and the second insulating buried layer constitute an insulating buried layer;

[0029] Forming a drift region extending from the first surface of the second substrate into the second substrate, wherein the drift region has a first conductivity type;

[0030] A trench gate structure and a trench drain structure are respectively formed to extend from the first surface of the second substrate into the second substrate, wherein the trench gate structure and the trench drain structure are spaced apart in a second direction in the drift region, the first trench isolation structure is disposed in the drift region on a side of the trench drain structure facing the trench upper structure and adjacent to the trench drain structure, and the first trench isolation structure extends from the second surface into the second substrate. In the second direction, the distance between the first trench isolation structure and the trench gate structure is greater than the distance between the first trench isolation structure and the trench drain structure.

[0031] In some embodiments of the present application, it further includes:

[0032] Etch the second substrate from the first surface to form at least one second trench;

[0033] Fill the second trench with an isolation material to form at least one second trench isolation structure, wherein the second trench isolation structure is disposed between the trench gate structure and the trench drain structure;

[0034] Wherein, the projection of the first trench isolation structure on the second surface and the projection of the second trench isolation structure on the second surface partially overlap; and / or

[0035] In the first direction, there is a space between the bottom of the second trench isolation structure facing away from the first surface and the top of the first trench isolation structure facing away from the insulating buried layer; and / or

[0036] In the second direction, the distance between the second trench isolation structure and the trench gate structure is less than the distance between the second trench isolation structure and the trench drain structure.

[0037] In some embodiments of the present application, forming a trench gate structure and a trench drain structure that respectively extend from the second surface of the second substrate into the second substrate includes:

[0038] Etch the second substrate to form a gate trench and a drain trench that respectively penetrate the second substrate;

[0039] Form a gate dielectric layer on the sidewalls of the gate trench and the drain trench and on the first surface of the second substrate;

[0040] Inject doping ions into the drift region on a side of the drain trench close to the gate trench by inclined ion implantation to form a drain region;

[0041] Remove the gate dielectric layer on the sidewall of the drain trench;

[0042] Form a gate electrode material layer to fill the gate trench and the drain trench respectively, so as to form a gate electrode located in the gate trench and a drain electrode located in the drain trench.

[0043] At least one of the first trench isolation structures is in contact with the drain region of the trench-drain structure, or there is a gap between the first trench isolation structure and the drain region of the trench-drain structure.

[0044] In some embodiments of the present application, the method further includes:

[0045] Before forming the trench-gate structure and the trench-drain structure, form a body region extending from the first surface into the drift region, and the body region is adjacent to the trench-gate structure, and the body region has a second conductivity type;

[0046] After forming the trench-gate structure and the trench-drain structure, form a source region in the body region by ion implantation, wherein,

[0047] The distance between the top of the first trench isolation structure on the side away from the second surface and the first surface is greater than the depth of the body region.

[0048] The power semiconductor device and its manufacturing method of the present invention. In this power semiconductor device, by setting a first trench isolation structure in the drift region and being adjacent to the trench-drain structure (by setting a first trench isolation structure in the drift region at the end of the trench-drain structure), the co-optimization of the specific on-resistance and breakdown voltage of the power semiconductor device is achieved. Specifically, firstly, the breakdown characteristics are improved: Since the dielectric constant of the insulating medium (also called isolation material) in the first trench isolation structure is lower than the dielectric constant of the second substrate, the high electric field peak region at the end of the trench-drain structure is borne by the insulating medium, effectively reducing the electric field intensity borne by the drift region and making the electric field distribution more gentle. Thus, the avalanche breakdown point is transferred from the end of the trench-drain structure of the traditional structure to the trench isolation structure, and finally the breakdown voltage of the device is significantly improved. Secondly, the conduction characteristics are improved: The reduction of the electric field in the drift region allows the doping concentration of the drift region to be increased on the premise of ensuring the same breakdown voltage. The higher carrier concentration directly reduces the specific on-resistance of the device, and at the same time, the additional current path formed by the conductive medium further optimizes the conduction characteristics. This dual-path conduction mechanism enables the device to achieve a better balance between conduction loss and blocking ability. In this way, while maintaining the lateral dimension advantage of the device, the device in this embodiment successfully breaks through the positive correlation contradiction between the breakdown voltage and the specific on-resistance in traditional lateral devices, providing a better device solution for high-voltage integrated circuits and power system integration. Description of the Drawings

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0050] Figure 1 The structure diagram of a power semiconductor device in the related art is shown;

[0051] Figure 2 Shows Figure 1 The electric field distribution of the power semiconductor device;

[0052] Figure 3 The structure diagram of a power semiconductor device in an embodiment of the present invention is shown;

[0053] Figure 4 The structure diagram of a power semiconductor device in another embodiment of the present invention is shown;

[0054] Figure 5 The structure diagram of a power semiconductor device in still another embodiment of the present invention is shown;

[0055] Figure 6 Shows Figure 5 The electric field distribution of the power semiconductor device;

[0056] Figure 7 Shows Figure 5 The current distribution of the power semiconductor device;

[0057] Figure 8 The flowchart of a preparation method of a power semiconductor device in an embodiment of the present invention is shown;

[0058] Figure 9A The structure diagram of the first substrate of a preparation method of a power semiconductor device in an embodiment of the present invention is shown;

[0059] Figure 9B The structure diagram of the second substrate of a preparation method of a lateral double-diffused metal oxide power semiconductor device in an embodiment of the present invention is shown;

[0060] Figures 10 to 19 The cross-sectional view of the structure obtained by sequentially implementing a preparation method of a power semiconductor device in an embodiment of the present invention is shown;

[0061] Explanation of reference numerals:

[0062] 1. Substrate; 11. First substrate; 12. Second substrate; 13. Insulating buried layer; 13a. First insulating buried layer; 13b. Second insulating buried layer; 2. Drift region; 21. First surface; 22. Second surface; 31. First trench isolation structure; 32. Second trench isolation structure; 4. Body region; 40. Pad isolation layer; 5. Source region; 51. Contact region; 6. Trench gate structure; 60. Gate trench; 61. Gate dielectric layer; 62. Gate electrode; 7. Trench drain structure; 70. Drain trench; 71. Drain region; 72. Drain electrode; 85. Source connection structure; 86. Gate connection structure; 87. Drain connection structure. Detailed implementation manners

[0063] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

[0064] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the figures indicate like elements.

[0065] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0066] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatial relationship terms are intended to include different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, then an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0067] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0068] See Figure 1 , Figure 1The structural schematic diagram of a power semiconductor device in the related art is shown. This device is a structural schematic diagram of a power semiconductor device that combines a trench gate (TG) structure and a trench drain (TD) structure. The device includes a substrate 1, which sequentially includes a first substrate 11, an insulating buried layer 13, and a second substrate 12 from bottom to top. A body region 4, a drift region 2, a trench gate structure 6 penetrating the second substrate 12, and a trench drain structure 7 are formed in the second substrate 12. Among them, both the body region 4 and the drift region 2 are located between the trench gate structure 6 and the trench drain structure 7. An active region 5 is formed in the body region 4, and the source region 5 is adjacent to the trench gate structure 6. The TG structure includes a gate trench and a gate electrode 62. The gate electrode 62 is disposed in the gate trench, and a gate dielectric layer 61 is further disposed on the sidewall of the gate trench. The gate dielectric layer 61 is located between the gate electrode 62 and the second substrate 12. A gate connection structure 86 is disposed at the top of the gate trench to lead out the gate electrode 62 and electrically connect it to an external circuit. The TD structure is parallel to the TG structure and includes a drain trench, a drain electrode 72, and a drain region 71. The drain electrode 72 is disposed in the drain trench, and the drain region 71 is disposed in the drift region 2 on the side of the trench drain structure 7 facing the trench gate structure 6 and is in contact with the drain electrode 72. A drain connection structure 87 is disposed at the top of the drain trench, and the drain connection structure 87 is electrically connected to the drain electrode 72.

[0069] In the on-state, the TG structure is located outside the source region 5, thereby forming a longitudinal channel. A high-concentration electron accumulation layer is induced through the strong-field effect, promoting the formation of a longitudinal continuous current expansion path between the channel region (body region 4) and the drift region 2, reducing the specific on-resistance, and at the same time maintaining a relatively high breakdown voltage (BV). The TD structure can receive electrons drifted from the source region 5 in a wider range, increasing the longitudinal current conduction region. This conduction mechanism, in cooperation with the symmetric parallel layout of the TG structure and the TD structure, shortens the current lateral conduction path and further reduces the specific on-resistance. However, the global expansion of the current path brings new challenges while improving the on-state performance: Although the current conduction paths distributed throughout the drift region 2 increase the conduction cross-section, they also disperse the current conduction paths throughout the entire drift region 2, resulting in a significant reduction in the current density, thereby limiting the device performance.

[0070] The longitudinal extension characteristic of the TG structure has a dual effect in the blocking state: on the one hand, it improves the electric field uniformity through the electric field regulation effect penetrating the drift region 2, and the breakdown voltage can be increased; but on the other hand, its interaction with the TD structure instead strengthens the electric field concentration phenomenon near the trench gate structure 6 and at the end of the trench drain structure 7. See Figure 2 , Figure 2 is shown Figure 1The electric field distribution of the power semiconductor device. In the figure, it is shown that the electric field accumulates in the drift region 2 near the trench gate structure 6 in the upper red frame, and the electric field accumulates in the drift region 2 at the end of the trench drain structure 7 in the lower red frame.

[0071] Therefore, how to reasonably regulate the electric field distribution through structural optimization while maintaining a low specific on-resistance, especially eliminating the high electric field accumulation point at the end of the trench drain structure 7, so as to break through the performance limit of the breakdown voltage is the core technical bottleneck that the power semiconductor device urgently needs to solve.

[0072] To solve at least one of the above technical problems, the present application proposes a power semiconductor device and a manufacturing method thereof. The following will describe each embodiment of the present application with reference to the accompanying drawings. It should be noted that on the premise of no conflict, each embodiment can be combined with each other.

[0073] First, refer to Figure 3 , Figure 3 which shows a schematic structural diagram of a power semiconductor device in an embodiment of the present invention. It should be noted that in the embodiments of the present application, the power semiconductor device can be a Lateral Double-Diffused MOSFET (LDMOS for short). The device includes:

[0074] A substrate 1, including a first substrate 11, an insulating buried layer 13, and a second substrate 12. The insulating buried layer 13 is located between the first substrate 11 and the second substrate 12. The second substrate 12 includes a first surface 21 far from the insulating buried layer 13 and a second surface 22 opposite to the first surface 21. The first surface 21 and the second surface 22 are spaced apart in a first direction.

[0075] A drift region 2, which is disposed in the second substrate 12 and extends into the second substrate 12 from the first surface 21. The drift region 2 has a first conductivity type.

[0076] A trench gate structure 6 and a trench drain structure 7, which are spaced apart in a second direction in the drift region 2. The trench gate structure 6 and the trench drain structure 7 both extend from the first surface 21 into the second substrate 12. The first direction and the second direction are perpendicular.

[0077] At least one first trench isolation structure 31, which is disposed in the drift region 2 and adjacent to the trench drain structure 7, and the first trench isolation structure 31 extends into the second substrate 12 from the second surface 22. In the second direction, the distance between the first trench isolation structure 31 and the trench gate structure 6 is greater than the distance between the first trench isolation structure 31 and the trench drain structure 7.

[0078] Among them, the drift region 2, the trench gate (TG) structure, and the trench drain (TD) structure all extend from the first surface 21 of the second substrate 12 into the second substrate 12. The depths to which the drift region 2, the trench gate (TG) structure, and the trench drain (TD) structure extend respectively can be reasonably set according to actual needs. For example, they extend to contact the insulating buried layer 13.

[0079] Among them, an active region 5 is further formed in the second substrate 12. The source region 5 is disposed between the trench gate structure 6 and the trench drain structure 7 and is adjacent to the trench gate structure 6.

[0080] It can be understood that the number of the first trench isolation structures 31 inside the drift region 2 can be one (only one is shown in the figure) or multiple (two or more). In the second direction, the distance between the first trench isolation structure 31 and the trench gate structure 6 is greater than the distance between the first trench isolation structure 31 and the trench drain structure 7. That is, in the second direction, the first trench isolation structure 31 is disposed closer to the trench drain structure 7.

[0081] It is worth mentioning that in the embodiment of the present application, the first conductivity type can be N-type and the second conductivity type is P-type, or the first conductivity type can be P-type and the second conductivity type is N-type. Optionally, the source region and the drain region can both be N+-type doped regions, and the drift region can be N--type, and the doping concentration of the drift region is lower than that of the source region and the drain region.

[0082] In the power semiconductor device of this embodiment, by disposing the first trench isolation structure 31 in the drift region 2 and adjacent to the trench gate structure 6 (that is, disposing the first trench isolation structure 31 in the drift region 2 at the end of the trench drain structure 7), the first trench isolation structure 31 includes a first trench and a first insulating dielectric material (such as a low dielectric constant material such as silicon dioxide SiO2, fluorinated silicon dioxide FSG, etc.) filled in the first trench, realizing the co-optimization of the specific on-resistance and breakdown voltage of the power semiconductor device. Specifically, first, the breakdown characteristics are improved: Since the dielectric constant of the insulating dielectric in the first trench isolation structure 31 is lower than the dielectric constant of the semiconductor drift region 2, under reverse bias conditions, the high electric field peak region at the end of the trench drain structure 7 is borne by the insulating dielectric. This electric field redistribution mechanism effectively reduces the electric field intensity borne by the semiconductor material in the drift region 2, makes the electric field distribution more gentle, and thus transfers the avalanche breakdown point from the drift region at the end of the trench drain structure 7 of the traditional structure to the inside of the first trench isolation structure 31, finally significantly improving the breakdown voltage of the device. Second, the conduction characteristics are improved: The reduction of the electric field in the drift region 2 allows the doping concentration of the drift region 2 to be increased on the premise of ensuring the same breakdown voltage. The higher carrier concentration directly reduces the specific on-resistance of the device, and at the same time further optimizes the conduction characteristics by adjusting the current path through the first trench isolation structure 31. This dual-path conduction mechanism enables the device to achieve a better balance between conduction loss and blocking ability.

[0083] In one example, the trench gate structure 6 includes a gate trench and a gate electrode 62. The gate trench extends from the first surface 21 to the insulating buried layer 13, and the gate electrode 62 is disposed in the gate trench.

[0084] The trench drain structure 7 includes a drain trench, a drain electrode 72, and a drain region 71. The drain trench extends from the first surface 21 to the insulating buried layer 13, the drain electrode 72 is disposed in the drain trench, and the drain region 71 is disposed in the drift region 2 on the side of the trench drain structure 7 facing the trench gate structure 6. The drain region 71 is in contact connection with the drain electrode 72.

[0085] At least one first trench isolation structure 31 is in contact with the drain region 71 of the trench drain structure 7, or there is a gap between the first trench and the drain region 71 of the trench drain structure 7.

[0086] Wherein, the gate electrode 62 can be polysilicon or other conductive materials, and the drain electrode 72 can be polysilicon or materials such as metal.

[0087] It can be understood that whether the first trench isolation structure 31 is in contact with the drain region 71 of the trench drain structure 7 or there is a gap, it means that in the second direction, the distance between the first trench isolation structure 31 and the trench gate structure 6 is smaller than the distance between the first trench isolation structure 31 and the trench drain structure 7. Adopting this design structure is mainly based on the characteristic that the drift region 2 at the end of the trench drain structure 7 is prone to electric field concentration. By making the first trench isolation structure 31 closer to the trench drain structure 7, the electric field distribution in this region can be effectively optimized, thereby realizing the active regulation of the electric field in the drift region 2 at the end of the trench drain structure 7.

[0088] Of course, the first trench isolation structure 31 is formed by filling at least one first trench with a first insulating dielectric material. The first trench isolation structure 31 is in contact with the drain region 71 of the trench drain structure 7. The first insulating dielectric material with a low dielectric constant filled in the first trench plays a role in two aspects: one is to effectively relieve the electric field distortion at the edge of the drain region 71 by reducing the interface dielectric constant gradient, promoting the electric field distribution to be more uniform, thereby preventing the occurrence of local breakdown phenomena. The other is that the insulating dielectric with a low dielectric constant has the characteristic of high thermal conductivity, which helps the local hot spots to diffuse, and further enhances the thermal stability of the device.

[0089] See Figure 4 , Figure 4 shows a schematic structural diagram of a power semiconductor device in another embodiment of the present invention. The device includes: a substrate 1, a drift region 2, a trench gate structure 6, and a trench drain structure 7. In this embodiment, the substrate, the trench gate structure 6, and the trench drain structure 7 are the same as the corresponding functional structures in Figure 3 and will not be described in detail here.

[0090] Among them, the substrate 1 is a SOI (Silicon-On-Insulator) substrate, and the first substrate 11 provides physical support for the entire structure. The insulating buried layer 13 can be silicon oxide or other suitable insulating materials, and is used to isolate the second substrate 12 from the first substrate 11. The second substrate 12 is a silicon layer or other suitable semiconductor material.

[0091] In one example, the power semiconductor device further includes a body region 4 that extends from the first surface 21 into the drift region 2, and the body region 4 is adjacent to the trench gate structure 6. The body region 4 has a second conductivity type; wherein, the distance between the top of the first trench isolation structure 31 on the side far from the second surface 22 and the first surface 21 is greater than the depth of the body region 4.

[0092] Among them, the source region 5 is formed in the body region 4. The source region 5 and the contact region 51 are formed side by side in the body region. An anode connection structure 85 is connected to the tops of the source region 5 and the contact region 51 facing away from the second surface. The anode connection structure 85 can be used to electrically connect the source region 5 and the contact region 51 to an external circuit.

[0093] It can be understood that the number of the first trench isolation structures 31 inside the drift region 2 can be multiple (two or more, only two are shown in the figure). Optionally, the column of the first trench isolation structures 31 arranged longitudinally closest to the drain region 71 can be in contact with the drain region 71. The multiple first trench isolation structures 31 can be arranged horizontally, longitudinally, or in an array. For example, in the case where the multiple first trench isolation structures 31 are arranged in a row horizontally, the first trench isolation structure 31 closest to the drain region 71 can be in contact with the drain region 71 or spaced apart. For another example, in the case where the multiple first trench isolation structures 31 are arranged longitudinally or in an array, they can be in contact with or spaced apart. The shapes, sizes, and spacings of the multiple first trench isolation structures 31 can be the same, or can be designed into different shapes, sizes, and spacings according to the specific functional requirements of the device.

[0094] In the power semiconductor device of this embodiment, the first trench isolation structure 31 will generate new electric field peaks around it, and the electric field in the drift region 2 is actively modulated by means of these electric field peaks. The specific adjustment effects of multiple first trench isolation structures 31 can be precisely controlled by optimizing geometric parameters such as the spacing, depth, and aspect ratio of the multiple first trench isolation structures 31. The layout of the body region 4 and the second trench isolation structure jointly affects the carrier transport efficiency, and the current path can be optimized through the spatial relationship formed by the body region 4 and the first trench isolation structure 31. In addition, this device adopts an SOI substrate architecture, and the insulating buried layer 13 is used as the isolation medium between the first substrate 11 and the drift region 2. This structure utilizes the low conductivity characteristic of the insulating buried layer 13 to block the longitudinal leakage current path, making the electric field concentrated in the lateral drift region 2. Combined with the carrier concentration gradient design, the breakdown voltage of the device can be significantly improved. Thus, while maintaining the lateral size advantage of the device, the device of this embodiment successfully breaks through the positive correlation contradiction between the breakdown voltage and the specific on-resistance in traditional lateral devices, providing a better device solution for high-voltage integrated circuits and power system integration.

[0095] See Figure 5 , Figure 5 FIG. shows a schematic structural diagram of a power semiconductor device in another embodiment of the present invention. The device includes: a substrate 1, a drift region 2, a trench gate structure 6, and a trench drain structure 7. Among them, the substrate, the trench gate structure 6, and the trench drain structure 7 are the same as the corresponding functional structures in Figure 3 and will not be described in detail here.

[0096] The power semiconductor device in this embodiment further includes:

[0097] A source region 5 is disposed between the trench gate structure 6 and the trench drain structure 7 and adjacent to the trench gate structure 6, and extends from the first surface 21 into the drift region 2;

[0098] At least one second trench isolation structure 32 is disposed in the drift region 2 between the source region 5 and the trench drain structure 7 and extends from the first surface 21 into the drift region 2.

[0099] Among them, the second trench isolation structure 32 extends from the first surface 21 of the second substrate 12 into the drift region 2 and does not exceed the second surface 22.

[0100] A body region 4 extends from the first surface 21 into the drift region 2, and the body region 4 is adjacent to the trench gate structure 6. The body region 4 has a second conductivity type; among them, the distance between the top of the first trench isolation structure 31 on the side away from the second surface 22 and the first surface 21 is greater than the depth of the body region 4.

[0101] In the power semiconductor device of this embodiment, compared with Figure 3 and Figure 4For the device, a second trench isolation structure 32 is added to the drift region 2. The main function of the second trench isolation structure 32 is to form an electric field buffer layer and reduce the surface electric field of the drift region 2. The first trench isolation structure 31 and the second trench isolation structure 32 in the device cooperate to optimize the electric field distribution and carrier transport in the drift region 2. In terms of the electric field distribution: The first trench isolation structure 31 effectively transfers the peak electric field of the drain-end drift region 2 to the inside of the first trench isolation structure 31 through the first insulating dielectric material, significantly reducing the electric field concentration. The metal-insulator-semiconductor structure (MIS structure) constructed by the second trench isolation structure 32 produces an electric field buffering effect, significantly reducing the surface electric field intensity of the drift region 2. The cooperative action of the double trench isolation structure significantly improves the lateral / longitudinal electric field uniformity of the drift region 2, ultimately achieving a significant increase in the breakdown voltage BV. In terms of carrier transport: The insulating barrier of the first trench isolation structure 31 changes the carrier transport trajectory. When electrons move from the source to the drain, affected by the interface barrier of the first trench isolation structure 31, they mainly form an arc conduction path along the sidewall of the trench. The second trench isolation structure 32 produces a dynamic current concentration phenomenon through the cross-section modulation effect, increasing the effective current density under the rated working voltage. The cooperative action of the first trench isolation structure 31 and the second trench isolation structure 32 enables the device to achieve low on-state loss while maintaining high breakdown voltage, providing a better power conversion efficiency for high-frequency and high-voltage application scenarios. See Figure 6 And Figure 7 , Figure 6 shows Figure 5 the electric field distribution of the power semiconductor device. In the figure, the absolute value Abs(electric field) of the electric field of each part of the device is shown by different colors. Figure 7 shows Figure 5 the current path distribution of the power semiconductor device. In the figure, the doping concentration (Doping Concentration) of each part of the device is shown by different colors. By Figure 6 and Figure 7 it can be seen that the first trench isolation structure 31 effectively transfers the peak electric field of the end drift region 2 of the trench-drain structure to the inside of the first trench isolation structure 31 through the first insulating dielectric material, significantly reducing the electric field concentration. The current path distribution can be adjusted through the first trench isolation structure 31 and the second trench isolation structure 32. Compared with the current conduction path that is uniformly distributed throughout the drift region 2 in the related art, in the solution of this application, the current path distribution is relatively concentrated, so it is beneficial to increase the current density.

[0102] It should be noted that the insulating dielectrics in the first trench isolation structure 31 and the second trench isolation structure 32 can be the same material or different materials respectively. The first trench isolation structure 31 and the second trench isolation structure 32 can each be one or more. The arrangement of multiple first trench isolation structures 31 or multiple second trench isolation structures 32 can be arranged along the first direction, along the second direction, or in an array arrangement. Parameters such as the layout method (arrangement method, trench pitch), the number of trenches, and the trench size of the first trench isolation structure 31 and the second trench isolation structure 32 can all be flexibly adjusted according to specific designs and functional requirements.

[0103] In some embodiments, the projection of the first trench isolation structure 31 on the second surface 22 and the projection of the second trench isolation structure 32 on the second surface 22 partially overlap, or they may not overlap.

[0104] Among them, the fact that the projection of the first trench isolation structure 31 on the second surface 22 and the projection of the second trench isolation structure 32 on the second surface 22 partially overlap mainly means that the projections overlap at least in the second direction.

[0105] It can be understood that when the projections of the first trench isolation structure 31 and the second trench isolation structure 32 on the second surface 22 partially overlap, it means that a continuous electric field modulation region can be formed in the drift region 2. In this way, the electric field peaks can be suppressed simultaneously in the transverse and longitudinal directions of the drift region 2, reducing the concentration of the local electric field. This avoids the occurrence of avalanche breakdown when the device has not reached the ideal breakdown voltage, thereby improving the overall breakdown voltage BV of the device.

[0106] In some embodiments, in the first direction, there is a spaced arrangement between the bottom of the second trench isolation structure 32 facing away from the first surface 21 and the top of the first trench isolation structure 31 facing away from the insulating buried layer 13.

[0107] It can be understood that both the first trench isolation structure 31 and the second trench isolation structure 32 introduce new electric field peak points by means of a low dielectric constant insulating dielectric, thereby reducing the electric field intensity near each trench. In this way, there is a predetermined spacing between the first trench isolation structure 31 and the second trench isolation structure 32, and this spacing can prevent the overlap of their electric field peaks, making the electric field distribution in the drift region 2 more uniform. And the predetermined spacing can prevent the second trench isolation structure 32 from being too close to the first trench isolation structure 31, avoiding the complete blockage of the conductive channel in the drift region 2.

[0108] In some embodiments, in the second direction, the spacing between the second trench isolation structure 32 and the trench gate structure 6 is less than the spacing between the second trench isolation structure 32 and the trench drain structure 7.

[0109] It can be understood that this layout strategy is mainly based on the characteristic that the drift region 2 near the trench-gate structure 6 is prone to electric field concentration. By making the second trench isolation structure 32 closer to the trench-gate structure 6, the electric field distribution in this region can be effectively optimized, thereby achieving active control of the electric field in the drift region 2 near the trench-gate structure 6.

[0110] In some embodiments, the cross-sections of both the first trench isolation structure 31 and the second trench isolation structure 32 are rectangular structures or any other suitable shapes.

[0111] It can be understood that the first trench isolation structure 31 and the second trench isolation structure 32 adopt rectangular structures, which makes the distribution of the electric field at the trench edges more uniform, thereby reducing the risk of local electric field concentration. Moreover, the filled low-dielectric-constant medium can achieve a closer fitting effect by virtue of the regular shape of the rectangular structure, preventing problems such as dielectric layer voids or uneven thickness due to irregular trench shapes. In addition, from the perspective of process manufacturing, rectangular trenches have better controllability during the processing, and the control of the rectangular structure is more precise, which can ensure the stable formation of the trenches.

[0112] See Figures 8 to 19 , Figure 8 shows a flowchart of a method for manufacturing a power semiconductor device according to an embodiment of the present invention. The manufacturing method may include the following steps:

[0113] Step S801: Provide a first substrate 11, on the surface of which a first insulating buried layer 13a is covered. See Figure 9A as shown.

[0114] Among them, the first substrate 11 provides physical support for the entire structure and can be an N-type doped silicon substrate. The first insulating buried layer 13a can be silicon oxide or other suitable insulating materials.

[0115] Step S802: Provide a second substrate 12. The second substrate 12 includes a first surface 21 and a second surface 22 that are oppositely arranged. At least one first trench is formed in the second substrate 12, and the first trench extends from the second surface 22 into the second substrate 12. Among them, the first surface 21 and the second surface 22 are spaced apart in a first direction.

[0116] Among them, the second substrate 12 can be a single-crystalline silicon layer or other suitable semiconductor materials, and is used to form functional structures such as the drift region, body region, source region, trench-gate structure, and trench-drain structure of the power semiconductor device.

[0117] At least one first trench can be etched into the second substrate 12 from the second surface of the second substrate 12 through photolithography and etching processes, and the first trench is located at the end of the trench-drain structure to be formed subsequently.

[0118] Step S803: Form a second insulating buried layer 13b to fill the first trench to form a first trench isolation structure 31, and the second insulating buried layer 13b also covers the second surface 22 of the second substrate 12. See Figure 9B as shown.

[0119] After that, the first trench can be filled by depositing the second insulating buried layer 13b, and the second surface of the second substrate 12 can be covered. After the deposition process, the surface of the second insulating buried layer 13b can also be planarized by using, for example, chemical mechanical polishing and / or etching processes, so as to facilitate providing a flat surface for subsequent bonding. The second insulating buried layer 13b can be used as a bonding layer for subsequent bonding of the second substrate and the first substrate. The insulating buried layer 13b filled in the first trench can be used as an insulating dielectric layer.

[0120] Among them, the second insulating buried layer 13b can be silicon oxide, and any suitable method well-known to those skilled in the art can be used to form the second insulating buried layer 13b. Exemplarily, the second insulating buried layer 13b can be formed by deposition processes such as, but not limited to, chemical vapor deposition (CVD). Specifically, low-pressure chemical vapor deposition (LPVCD), atmospheric pressure chemical vapor deposition (APCVD), or plasma-enhanced chemical vapor deposition (PECVD) can be used. Alternatively, the second insulating buried layer 13b can also be formed by a high-temperature furnace tube thermal oxidation process. Preferably, the second insulating buried layer 13b is deposited by low-pressure chemical vapor deposition, so that a relatively dense second insulating buried layer 13b can be formed.

[0121] Step S804: Bond the side of the second substrate 12 with the second insulating buried layer 13b and the side of the first substrate 11 with the first insulating buried layer 13a. The first insulating buried layer 13a and the second insulating buried layer 13b constitute the insulating buried layer 13. See Figure 10 and Figure 11 as shown.

[0122] The second substrate 12 and the first substrate 11 can be bonded by any suitable method. For example, by direct bonding, both the first insulating buried layer 13a and the second insulating buried layer 13b can include silicon oxide. The side of the second substrate 12 with the second insulating buried layer 13b and the side of the first substrate 11 with the first insulating buried layer 13a are opposed and contacted, and annealing is performed at a high temperature, for example, at a temperature of 800°C - 1100°C, to enhance the bonding strength. Pressure can also be applied to the second substrate 12 and the first substrate 11 during bonding to further enhance the bonding strength.

[0123] Step S805, forming a drift region 2 extending from the first surface 21 of the second substrate 12 into the second substrate 12, wherein the drift region 2 has a first conductivity type, see Figure 11 shown.

[0124] In some embodiments, the drift region 2 can be formed by ion implantation. Exemplarily, photolithography is used to define the area where ions need to be implanted on the second substrate 12, that is, the predetermined drift region 2. Photoresist is used as a mask to protect the area where no implantation is required. Boron or phosphorus ions are implanted into the area defined by photolithography. The injection energy and dose determine the penetration depth and concentration distribution of the ions. During the injection process, the substrate temperature is kept at a low temperature to reduce the diffusion effect. The second substrate 12 after injection is annealed at high temperature to repair the lattice damage caused by ion implantation and activate the injected impurity atoms to make them effective electrical doping. The annealing temperature and time are determined according to the specific process requirements, usually around 1000°C. The conductivity type of the drift region 2 can be reasonably set according to actual needs, and is not specifically limited here.

[0125] Step S806, Figures 13 to 18 As shown, a trench gate structure 6 and a trench drain structure 7 are respectively formed to extend from the first surface 21 of the second substrate 12 into the second substrate 12 .

[0126] The trench gate structure 6 and the trench drain structure 7 are arranged in the drift region 2 at intervals in the second direction, the first trench isolation structure 31 is arranged in the drift region 2 on the side of the trench drain structure 7 facing the trench upper structure and is adjacent to the trench gate structure 6 (that is, it is arranged in a part of the drift region 2 at the end of the trench drain structure 7), and the first trench isolation structure 31 extends from the second surface 22 into the second substrate 12. In the second direction, the spacing between the first trench isolation structure 31 and the trench gate structure 6 is greater than the spacing between the first trench isolation structure 31 and the trench drain structure 7.

[0127] In some embodiments, after step S806 or before step S806, the method further includes:

[0128] Step S807, etching the second substrate 12 from the first surface 21 to form at least one second trench;

[0129] Step S808, filling the second trench with an isolation material (also referred to herein as an insulating dielectric layer) to form at least one second trench isolation structure 32, wherein the second trench isolation structure 32 is disposed between the trench gate structure 6 and the trench drain structure 7, for example, more specifically, between the source region 5 and the trench drain structure 7, see Figure 12As shown; wherein, the projection of the first trench isolation structure 31 on the second surface 22 and the projection of the second trench isolation structure 32 on the second surface 22 partially overlap; and / or, in the first direction, there is a spaced arrangement between the bottom of the second trench isolation structure 32 facing away from the first surface 21 and the top of the first trench isolation structure 31 facing away from the insulating buried layer; and / or, in the second direction, the distance between the second trench isolation structure 32 and the trench gate structure 6 is less than the distance between the second trench isolation structure 32 and the trench drain structure 7.

[0130] It should be noted that steps S807 and S808 can be after step 806, or between step S805 and step S806, that is, after forming the drift region 2, at least one second trench isolation structure 32 is formed in the drift region 2, see Figure 12 As shown. Before forming the trench gate structure 6 and the trench drain structure 7, the second trench isolation structure 32 is formed. Of course, if there is no second isolation trench structure in the drift region of the power semiconductor device to be prepared, there are no the above steps S807 and 808.

[0131] In some embodiments, the trench drain structure and the trench gate structure can be formed by any suitable method. For example, the above S806 can include:

[0132] S806a, etching the second substrate 12 to form a gate trench 60 and a drain trench 70 that respectively penetrate the second substrate 12. The regions of the second substrate 12 where the gate trench 60 and the drain trench 70 are to be formed can be defined by a photolithography process, and then the second substrate 12 is etched by a wet etching process or a dry etching process to form the gate trench 60 and the drain trench 70. Specifically, a dry etching process can be used, such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can be used, or more than one etching method can also be used.

[0133] S806b, forming a gate dielectric layer 61 on the sidewalls of the gate trench 60 and the drain trench 70 and on the first surface 21 of the second substrate 12, see Figure 15 As shown.

[0134] Among them, the gate dielectric layer can be silicon oxide or silicon oxynitride. A silicon oxide-based gate dielectric layer 61 can be formed by an oxidation process well-known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing oxidation (RTO), in-situ steam generation (ISSG), etc. Nitridation of the silicon oxide can form silicon oxynitride, where the nitridation process can be high-temperature furnace tube nitridation, rapid thermal annealing nitridation, or plasma nitridation. Of course, other nitridation processes can also be used, which will not be elaborated here.

[0135] S806c, doping ions are implanted into the drift region 2 on the side of the drain trench 70 close to the gate trench 60 by inclined ion implantation to form a drain region 71, see Figure 16 As shown, a high temperature drive-in is then performed to form a device drain region 71 .

[0136] The drain region may extend from the first surface to the second surface of the second substrate. The doping ions implanted by the oblique ion implantation may be reasonably selected according to actual needs. For example, if an N+ type drain region 71 is to be formed, it may be formed by implanting phosphorus or arsenic.

[0137] S806d, remove the gate dielectric layer 61 on the side wall of the drain trench 70. For example, a protective layer such as a photoresist layer can be first formed to cover the gate trench and the gate dielectric layer on the second substrate 12 to expose the gate dielectric layer in the drain trench. Then, the gate dielectric layer 61 on the side wall of the drain trench 70 is removed by, for example, wet etching or dry etching, and then the photoresist layer is removed.

[0138] S806e, forming a gate electrode material layer to fill the gate trench 60 and the drain trench 70 respectively, so as to form a gate electrode 62 located in the gate trench 60 and a drain electrode 72 located in the drain trench 70, see Figure 17 shown.

[0139] In one embodiment, the gate electrode material layer may be composed of polysilicon material, and metal, metal nitride, metal silicide or similar compounds may also be used as the material of the gate electrode material layer. The preferred method for forming the gate electrode material layer includes chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and general similar methods such as sputtering and physical vapor deposition (PVD) may also be used.

[0140] At least one first trench isolation structure 31 is in contact with the drain region 71 of the trench drain structure 7 , or there is a gap between the first trench isolation structure 31 and the drain region 71 of the trench drain structure 7 .

[0141] In some embodiments, before step S806, the process further includes: forming a body region 4 extending from the first surface 21 into the drift region 2, and the body region 4 is adjacent to the trench gate structure 6, and the body region 4 has a second conductivity type, see Figure 14 As shown, the distance between the top of the first trench isolation structure 31 away from the second surface 22 and the first surface 21 is greater than the depth of the body region 4 .

[0142] In some examples, the second trench isolation structure 32 may be located between the body region 4 and the trench drain structure 7, and the distance between it and the body region 4 is less than the distance between the second trench isolation structure 32 and the trench drain structure 7. Among them, the body region 4 is formed on the second substrate 12 by ion implantation. Exemplarily, P-type impurities are implanted into the body region 4 area of the second substrate 12. After implantation, the impurities are longitudinally diffused into the drift region 2 and laterally diffused near the edge of the drift region 2 through high-temperature annealing to form the body region 4 (P-well). In order to avoid damage to the second substrate 12 caused by ion implantation, a pad isolation layer 40 is required to protect the second substrate 12 before ion implantation to form the body region. At the same time, the pad isolation layer 40 can also define the diffusion depth of ions in the second substrate 12, that is, define the depth of the body region 4. Exemplarily, the specific preparation process of the body region 4 may include: etching the second substrate 12 to form a gate trench 60 and a drain trench 70 that respectively penetrate the second substrate 12, and forming a pad isolation layer 40 on the sidewalls of the gate trench 60 and the drain trench 70 and on the first surface 21 of the second substrate 12. See Figure 13 as shown. In addition, the pad isolation layer 40 can be formed by methods including but not limited to: chemical vapor deposition method and physical vapor deposition method. The material of the pad isolation layer 40 includes but not limited to silicon oxide or other suitable materials.

[0143] It should be noted that after the body region 4 is formed, during the subsequent step S806, the pad isolation layer 40 needs to be removed. After removing the substrate isolation layer, a gate dielectric layer 61 is formed on the sidewalls of the formed gate trench and drain trench and on the first surface 21 of the second substrate 12.

[0144] In some examples, the step of forming the body region 4 can also be implemented between step S806a and step S806b, or it can also be before the step of etching to form the gate trench 60 and the drain trench 70.

[0145] In one example, the method of the present application further includes: forming a source region 5 in the body region 4 by ion implantation, such as an N+ type source region.

[0146] Among them, after step S806, ion implantation (such as N-type doping ions or P-type doping ions) is respectively performed in the body region 4 to form a source region 5 and a contact region 51 arranged side by side. The contact region 51 is in contact with the body region 4. See Figure 18As shown, when the source region 5 and the contact region 51 are formed by ion implantation, the gate dielectric layer 61 formed on the first surface 21 of the second substrate 12 can protect the second substrate during the ion implantation process, avoiding damage to the substrate caused by ion implantation. After that, after the source region 5 and the contact region 51 are formed, the gate dielectric layer 61 on the first surface 21 of the second substrate 12 is removed by, for example, wet etching or dry etching. Optionally, the contact region 51 serves as the lead-out region of the body region, having the same conductivity type as the body region, but with a doping concentration higher than that of the body region.

[0147] In some embodiments, after step S806, the method of the present application further includes: as Figure 19 shown, a metal layer such as copper, aluminum, tungsten or other metal materials is deposited on the surface of the second substrate, and then by etching the metal layer, a gate connection structure 86, a source connection structure 85 and a drain connection structure 87 are respectively formed. Among them, the gate connection structure 86 is electrically connected to the trench gate structure 6, the source connection structure 85 is electrically connected to the source region 5 and the contact region 51, and the drain connection structure 87 is electrically connected to the drain electrode 72. Through such a setting, electrical connection with an external circuit can be achieved.

[0148] The method for manufacturing a power semiconductor device according to an embodiment of the present invention can be used to manufacture the power semiconductor device according to the embodiment of the present invention described above. The manufactured power semiconductor device has all the advantages of the device described above. For the sake of brevity, it will not be elaborated here. It is worth mentioning that, on the premise of not conflicting, the order of each step of the above manufacturing method can also be adjusted.

[0149] Although example embodiments have been described herein with reference to the drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present invention thereto. Those of ordinary skill in the art can make various changes and modifications therein without departing from the scope and spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as claimed in the appended claims.

[0150] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0151] Similarly, it should be understood that, for the sake of streamlining the present invention and aiding in the understanding of one or more of the various inventive aspects, in the description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the methods of the present invention should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, the inventive point lies in that the corresponding technical problems can be solved with features less than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, where each claim itself serves as a separate embodiment of the present invention.

[0152] Those skilled in the art will understand that, except where features are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0153] Furthermore, those skilled in the art will be able to understand that, although some embodiments herein include certain features included in other embodiments but not others, the combination of features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0154] It should be noted that the above embodiments illustrate the present invention rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not denote any order. These words can be construed as names.

Claims

1. A power semiconductor device, characterized in that, Comprising: A substrate, including a first substrate, an insulating buried layer, and a second substrate. The insulating buried layer is located between the first substrate and the second substrate. The second substrate includes a first surface away from the insulating buried layer and a second surface opposite to the first surface. The first surface and the second surface are spaced apart in a first direction. A drift region, which is disposed in the second substrate and extends from the first surface into the second substrate. The drift region has a first conductivity type. A trench gate structure and a trench drain structure, which are spaced apart in a second direction in the drift region. The trench gate structure and the trench drain structure both extend from the first surface into the second substrate. The first direction and the second direction are perpendicular. At least one first trench isolation structure, which is disposed in the drift region and adjacent to the trench drain structure, and the first trench isolation structure extends from the second surface into the second substrate. In the second direction, the distance between the first trench isolation structure and the trench gate structure is greater than the distance between the first trench isolation structure and the trench drain structure. In the first direction, the distance between the top of the first trench isolation structure on the side away from the second surface and the first surface is less than the depth of the trench drain structure.

2. The power semiconductor device according to claim 1, wherein, Further comprising: A source region, which is disposed between the trench gate structure and the trench drain structure and adjacent to the trench gate structure, and extends from the first surface into the drift region. At least one second trench isolation structure, which is disposed in the drift region between the source region and the trench drain structure and extends from the first surface into the interior of the drift region.

3. The power semiconductor device according to claim 2, wherein, The projection of the first trench isolation structure on the second surface and the projection of the second trench isolation structure on the second surface partially overlap.

4. The power semiconductor device according to claim 2, wherein In the first direction, there is a space between the bottom of the second trench isolation structure facing away from the first surface and the top of the first trench isolation structure facing away from the insulating buried layer. And / or In the second direction, the distance between the second trench isolation structure and the trench gate structure is less than the distance between the second trench isolation structure and the trench drain structure.

5. The power semiconductor device according to any one of claims 1 to 4, characterized in that The drift region extends from the first surface to the second surface. The trench gate structure includes a gate trench and a gate electrode. The gate trench extends from the first surface to the insulating buried layer, and the gate electrode is disposed in the gate trench. The trench drain structure includes a drain trench, a drain electrode, and a drain region. The drain trench extends from the first surface to the insulating buried layer, the drain electrode is disposed in the drain trench, and the drain region is disposed in the drift region on the side of the trench drain structure facing the trench gate structure. The drain region is in contact connection with the drain electrode. At least one of the first trench isolation structures is in contact with the drain region of the trench drain structure, or there is a gap between the first trench isolation structure and the drain region of the trench drain structure.

6. The power semiconductor device according to any one of claims 1 to 4, characterized in that, Further comprising: A body region extends from the first surface into the drift region, and the body region is adjacent to the trench gate structure. The body region has a second conductivity type; Wherein, the distance between the top of the first trench isolation structure on the side away from the second surface and the first surface is greater than the depth of the body region.

7. A method for manufacturing a power semiconductor device, characterized in that, Comprising: Providing a first substrate, on the surface of which a first insulating buried layer is covered; Providing a second substrate, which includes a first surface and a second surface arranged opposite to each other. At least one first trench is formed in the second substrate, and the first trench extends from the second surface into the second substrate. Wherein, the first surface and the second surface are spaced apart in a first direction; Forming a second insulating buried layer to fill the first trench to form a first trench isolation structure, and the second insulating buried layer also covers the second surface of the second substrate; Bonding the side of the second substrate formed with the second insulating buried layer and the side of the first substrate formed with the first insulating buried layer. The first insulating buried layer and the second insulating buried layer constitute an insulating buried layer; Forming a drift region extending from the first surface of the second substrate into the second substrate. Wherein, the drift region has a first conductivity type; Respectively forming a trench gate structure and a trench drain structure extending from the first surface of the second substrate into the second substrate. Wherein, the trench gate structure and the trench drain structure are spaced apart in a second direction in the drift region. The first trench isolation structure is disposed in the drift region on the side of the trench drain structure facing the trench upper structure and adjacent to the trench drain structure, and the first trench isolation structure extends from the second surface into the second substrate. In the second direction, the distance between the first trench isolation structure and the trench gate structure is greater than the distance between the first trench isolation structure and the trench drain structure.

8. The method for manufacturing a power semiconductor device according to claim 7, characterized in that, Further comprising: Etching the second substrate from the first surface to form at least one second trench; Filling an isolation material in the second trench to form at least one second trench isolation structure, wherein the second trench isolation structure is disposed between the trench gate structure and the trench drain structure; Wherein, the projection of the first trench isolation structure on the second surface and the projection of the second trench isolation structure on the second surface partially overlap; and / or In the first direction, the bottom of the second trench isolation structure facing away from the first surface and the top of the first trench isolation structure facing away from the insulating buried layer are spaced apart; and / or In the second direction, the distance between the second trench isolation structure and the trench gate structure is less than the distance between the second trench isolation structure and the trench drain structure.

9. The manufacturing method of the power semiconductor device according to claim 7, characterized in that, Respectively forming a trench gate structure and a trench drain structure extending from the second surface of the second substrate into the second substrate includes: Etching the second substrate to form a gate trench and a drain trench respectively penetrating the second substrate; Forming a gate dielectric layer on the sidewalls of the gate trench and the drain trench and on the first surface of the second substrate; Doping ions are implanted into the drift region on the side of the drain trench close to the gate trench by inclined ion implantation to form a drain region; The gate dielectric layer on the sidewall of the drain trench is removed; A gate electrode material layer is formed to fill the gate trench and the drain trench respectively, so as to form a gate electrode in the gate trench and a drain electrode in the drain trench; At least one of the first trench isolation structures is in contact with the drain region of the trench-drain structure, or there is a gap between the first trench isolation structure and the drain region of the trench-drain structure.

10. The manufacturing method of the power semiconductor device according to claim 9, characterized in that, The method further includes: Before forming the trench-gate structure and the trench-drain structure, a body region extending from the first surface into the drift region is formed, and the body region is adjacent to the trench-gate structure, and the body region has a second conductivity type; After forming the trench-gate structure and the trench-drain structure, a source region is formed in the body region by ion implantation, wherein The distance between the top of the first trench isolation structure on the side away from the second surface and the first surface is greater than the depth of the body region.

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