Solar cell, cell module and photovoltaic system

Abstract

The invention is applicable to the field of photovoltaic technology, and provides a solar cell, a cell module and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate comprises a first area and a second area, a P-type polycrystalline silicon layer is arranged in the first area, and an N-type polycrystalline silicon layer is arranged in the second area; the P-type polycrystalline silicon layer comprises a plurality of P-type crystal grains, a first crystal boundary is arranged between adjacent P-type crystal grains, the N-type polycrystalline silicon layer comprises a plurality of N-type crystal grains, a second crystal boundary is arranged between adjacent N-type crystal grains, and the width of the first crystal boundary is smaller than that of the second crystal boundary. According to the invention, recombination of holes at the grain boundary is reduced, the transmission efficiency of electrons is enhanced, the photoelectric conversion efficiency of the solar cell is improved, the overall stress of the silicon wafer is more balanced, the bending possibility of the silicon wafer is reduced, and the manufacturing yield of the solar cell is finally improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaics, and particularly relates to a solar cell, a battery module and a photovoltaic system. Background Art

[0002] As one of the most abundant renewable energy sources, solar energy has great development potential and application prospects. A solar cell is the core device for directly converting solar energy into electrical energy and is a key technology for realizing the efficient utilization of solar energy. The photoelectric conversion efficiency refers to the proportion of incident light energy converted into electrical energy by a solar cell and is the core index for measuring the performance of a solar cell. Improving the photoelectric conversion efficiency can increase the electrical energy output per unit area and reduce the power generation cost.

[0003] Currently, the photoelectric conversion efficiency of commercial silicon-based solar cell modules is about 20% - 25%. Improving the photoelectric conversion efficiency of solar cells is an important part of solar cell research and development. Improving the photoelectric conversion efficiency can increase the electrical energy output per unit area, reduce the power generation cost, thereby shortening the investment recovery period, enhancing the market competitiveness, and promoting the rapid development of the photovoltaic industry. Therefore, improving the photoelectric conversion efficiency of solar cells not only has important economic, environmental and technical significance, but also is the key to promoting the sustainable development of the photovoltaic industry. Summary of the Invention

[0004] The present invention provides a solar cell, aiming to improve the photoelectric conversion efficiency of the solar cell and solve the problem of low photoelectric conversion efficiency of the solar cell.

[0005] The present invention is implemented as follows. A solar cell includes:

[0006] A silicon substrate, the silicon substrate includes a first region and a second region, a P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region;

[0007] The P-type polysilicon layer includes a plurality of P-type grains, and there is a first grain boundary between adjacent P-type grains. The N-type polysilicon layer includes a plurality of N-type grains, and there is a second grain boundary between adjacent N-type grains. The width of the first grain boundary is less than the width of the second grain boundary.

[0008] Optionally, the silicon substrate has a light-facing surface and a backlight-facing surface disposed opposite to each other, and both the first region and the second region are disposed on the backlight-facing surface.

[0009] Optionally, the width of the first grain boundary is less than 10 nm.

[0010] Optionally, the width of the first grain boundary is 7 - 8 nm.

[0011] Optionally, the width of the second grain boundary is greater than 10 nm.

[0012] Optionally, the width of the second grain boundary is 10 to 22.

[0013] Optionally, the depth of the first grain boundary is less than that of the second grain boundary.

[0014] Optionally, the depth of the first grain boundary is less than 15 nm.

[0015] Optionally, the depth of the first grain boundary is 8 to 14 nm.

[0016] Optionally, the depth of the second grain boundary is greater than 10 nm.

[0017] Optionally, the depth of the second grain boundary is 15 to 24 nm.

[0018] Optionally, both the first region and the second region are matte surfaces.

[0019] Optionally, both the first region and the second region are polished surfaces.

[0020] An embodiment of the present invention further provides a battery assembly, including the above-mentioned solar cell.

[0021] An embodiment of the present invention further provides a photovoltaic system, including the above-mentioned battery assembly.

[0022] The beneficial effects achieved by the present invention are as follows. Since the first region and the second region are respectively provided on the silicon substrate, a P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains. A first grain boundary exists between adjacent P-type grains, and a second grain boundary exists between adjacent N-type grains. The width of the first grain boundary is less than that of the second grain boundary. The recombination of holes at the grain boundary is reduced, the electron transport efficiency is enhanced, the photoelectric conversion efficiency of the solar cell is improved. At the same time, the overall stress of the silicon wafer can be made more balanced, the possibility of silicon wafer bending is reduced, and finally the manufacturing yield of the solar cell is improved. Description of the Drawings

[0023] Figure 1 It is a first perspective enlarged schematic diagram of the matte P-type polysilicon layer 200K provided by an embodiment of the present invention;

[0024] Figure 2 It is a first perspective enlarged schematic diagram of the matte N-type polysilicon layer 200K provided by an embodiment of the present invention;

[0025] Figure 3 It is a first perspective enlarged schematic diagram of the polished P-type polysilicon layer 200K provided by an embodiment of the present invention;

[0026] Figure 4It is a first - perspective enlarged schematic view of the N - type polysilicon layer at 200K on the polished surface provided by an embodiment of the present invention;

[0027] Figure 5 It is a second - perspective enlarged schematic view of the P - type polysilicon layer at 200K on the polished surface provided by an embodiment of the present invention;

[0028] Figure 6 It is a second - perspective enlarged schematic view of the N - type polysilicon layer at 200K on the polished surface provided by an embodiment of the present invention.

[0029] Explanation of reference numerals:

[0030] 101, P - type grain; 102, first grain boundary; 201, N - type grain; 202, second grain boundary;

[0031] 30, protrusion; 40, depression. Detailed implementation manners

[0032] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as a limitation of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0033] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0034] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0035] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a connection that can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0036] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features therebetween. Moreover, the first feature being "above", "over", and "on" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "below", "beneath", and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0038] In the present invention, by respectively providing a first region and a second region on a silicon substrate, a P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains. There is a first grain boundary between adjacent P-type grains, and a second grain boundary between adjacent N-type grains, and the width of the first grain boundary is smaller than the width of the second grain boundary. The recombination of holes at the grain boundaries is reduced, the electron transport efficiency is enhanced, the photoelectric conversion efficiency of the solar cell is improved. At the same time, the overall stress of the silicon wafer can be made more balanced, the possibility of the silicon wafer bending is reduced, and finally the manufacturing yield of the solar cell is improved.

[0039] Embodiment

[0040] This embodiment provides a solar cell, which is characterized by comprising:

[0041] A silicon substrate, the silicon substrate includes a first region and a second region, a P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region;

[0042] The P-type polysilicon layer includes a plurality of P-type grains 101, there is a first grain boundary 102 between adjacent P-type grains 101, the N-type polysilicon layer includes a plurality of N-type grains 201, and there is a second grain boundary 202 between adjacent N-type grains 201. The width of the first grain boundary 102 is smaller than the width of the second grain boundary 202.

[0043] Two different regions, a first region and a second region, are arranged on the silicon substrate. The first region and the second region can be arranged on the same surface of the silicon substrate or on two opposite surfaces of the silicon substrate, which is not limited herein. A P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region. The P-type polysilicon layer and the N-type polysilicon layer form regions with different electrical characteristics, supporting the formation of a PN junction and the separation of carriers.

[0044] The P-type polysilicon layer can cover the entire first region or only a part of the first region. P-type polysilicon is a polysilicon material that has undergone specific doping treatment, and the doping element is usually an element that can provide holes (equivalent to positive charge carriers), such as boron (B), etc.

[0045] The P-type polysilicon layer is composed of a plurality of P-type grains 101. Grains are the basic units in the microstructure of polysilicon materials. The atomic arrangement within each P-type grain 101 has a certain regularity, but the orientations between different grains may be different, resulting in different shapes and sizes of each P-type grain 101. The shape of the P-type grain 101 can be approximately square, triangular, trapezoidal, approximately other polygons, or irregular shapes, which is not limited herein. In the first region, these P-type grains 101 are distributed throughout the P-type polysilicon layer.

[0046] The N-type polysilicon layer can cover the entire second region or only a part of the second region. N-type polysilicon is formed by doping elements that can provide electrons (negative charge carriers), and common doping elements such as phosphorus (P), etc.

[0047] The N-type polysilicon layer is also composed of a plurality of N-type grains 201. Similar to the P-type grains 101, the atomic arrangement within the N-type grains 201 is regular, but there are differences in the orientations between the grains, resulting in different shapes and sizes of each N-type grain 201. The shape of the N-type grain 201 can be approximately square, triangular, trapezoidal, approximately other polygons, or irregular shapes, which is not limited herein. In the second region, these N-type grains 201 are distributed throughout the N-type polysilicon layer.

[0048] A grain boundary is the interface between adjacent grains in a polycrystalline material. In a polycrystalline material, due to the different growth directions and crystal structures of the grains, grain boundaries are formed between adjacent grains. A grain boundary is a recombination center for charge carriers (electrons or holes), which can affect the conductivity and carrier lifetime of the material. Grain boundaries can impede the movement of dislocations, increasing the strength and hardness of the material, but an excessive number of grain boundaries may also lead to an increase in material brittleness.

[0049] The description that the width of the first grain boundary 102 is smaller than the width of the second grain boundary 202 is a description of the average state, that is, the average width of the first grain boundary 102 is smaller than the average width of the second grain boundary 202. The value of the average width can specifically adopt the mean method, that is, an equal number of grain boundaries are randomly selected in the first region and the second region respectively, and after summing the widths of the grain boundaries in each region and dividing by the number of grain boundaries, the average width can be calculated. It can be understood that the number of grain boundaries selected should not be too small, as it is likely to cause a large deviation in the results. In theory, the more grain boundaries are selected, the more accurate the calculation result will be, and the specific number can be selected according to the actual situation.

[0050] There may be individual cases where the grain boundary width of a P-type grain 101 is greater than that of an N-type grain 201, but the impact on the average trend is weak and will not be discussed separately.

[0051] There are a large number of lattice defects and impurities at the grain boundary. These defects and impurities will form energy traps. When electrons move in the silicon material, they may be trapped by these traps when encountering the grain boundary, thus hindering the normal transmission path of the electrons. Electrons need to spend more time and energy to bypass these traps or escape from the traps, which slows down the migration speed of the electrons and reduces the transmission efficiency.

[0052] For example, originally electrons could move quickly from one position to another along a relatively smooth path. However, after the grain boundary becomes wider, the electrons interact frequently with defects and impurities at the grain boundary, constantly changing their movement directions, resulting in a longer actual transmission time and a decrease in the overall transmission efficiency.

[0053] On the one hand, the P-type grain 101 is doped with P-type impurities (such as boron) and has hole conductivity. There are a large number of free electrons in the silicon material, and electrons become the majority carriers (majority carriers). Although the widening of the second grain boundary 202 will reduce the electron transmission efficiency, due to the large number of electrons in N-type silicon, even if some electrons are hindered at the grain boundary, there are still a large number of electrons that can successfully complete the transmission process and participate in the photoelectric conversion of the battery. That is to say, the overall supply of electrons is sufficient, and the loss of a small number of electrons at the second grain boundary 202 has little impact on the total amount of electron transmission in the entire N region.

[0054] From a macroscopic perspective, the overall efficiency of a solar cell mainly depends on the number of carriers that can effectively participate in the photoelectric conversion and their transport efficiency. In the N region, since there is an abundance of electrons, the reduction in electron transport efficiency caused by the widening of the second grain boundary 202 does not significantly affect the number of electrons that can ultimately reach the cell electrodes, and thus has little impact on the overall efficiency of the solar cell.

[0055] The P-type grains 101 are doped with P-type impurities (such as boron) and have hole conductivity. In P-type silicon, holes are the majority carriers, while electrons are the minority carriers. For the overall carrier balance in the P region, holes can be regarded as key "minor participants" in the photoelectric conversion process to a certain extent (here, compared with the large number of hole generation mechanisms in the P region, the number of holes participating in the effective photoelectric conversion process is limited). When the first grain boundary 102 widens, the situation is very different from that in the N region. Since holes are relatively key minority carriers (minority carriers) participating in the effective photoelectric conversion process in the P region, their number is relatively small. The increase in defects and impurities at the grain boundary caused by the widening of the first grain boundary 102 will greatly increase the probability of hole capture and recombination.

[0056] Once holes encounter traps at the grain boundary during the transport process, they are easily recombined and thus cannot reach the cell electrodes to participate in the photoelectric conversion. Moreover, due to the limited number of holes, the loss of each hole has a relatively large impact on the carrier transport and photoelectric conversion processes in the entire P region. Compared with the large number of electrons in the N region, the number of holes in the P region is small, and the hole loss caused by the widening of the first grain boundary 102 will significantly reduce the number of holes that can participate in the photoelectric conversion, thereby seriously affecting the overall efficiency of the solar cell. Therefore, a narrower first grain boundary 102 can reduce hole recombination at the grain boundary, thereby increasing the hole lifetime and the cell efficiency.

[0057] On the other hand, usually, the P region is slightly larger than the N region. This is because in the design of a solar cell, the P region is mainly responsible for absorbing photons and generating photoinduced carriers (electron-hole pairs). A larger P region area can increase the light absorption area, thereby increasing the number of photoinduced carriers generated, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. There are phenomena such as lattice distortion and impurity enrichment at the grain boundary, which will generate certain stress. Since the P region is slightly larger than the N region and the width of the first grain boundary is smaller than that of the second grain boundary, this makes the stress distribution of the entire silicon wafer more balanced.

[0058] In the larger P region, the stress generated by the narrower first grain boundary is relatively small. Although the grain boundary in the N region is wider, its area is relatively small, and the stress it generates can also balance the stress in the P region. When the internal stress distribution in the silicon wafer is uneven, an internal stress gradient will be generated, and this internal stress gradient will cause the silicon wafer to bend and deform. The bending of the silicon wafer will have a serious impact on subsequent battery manufacturing processes (such as lithography, coating, etc.), which may lead to a decrease in process accuracy, problems such as pattern alignment deviation and uneven film thickness, thereby reducing the performance and yield of solar cells.

[0059] When the grain boundary in the P region is smaller than that in the N region, making the overall stress more balanced, the possibility of the silicon wafer bending will be greatly reduced. The flat state of the silicon wafer is conducive to the precise implementation of subsequent processes, reducing process defects caused by the bending of the silicon wafer, thereby improving the manufacturing yield of solar cells, reducing production costs, and improving the quality and reliability of products.

[0060] In this embodiment, a first region and a second region are respectively provided on the silicon substrate. A P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201. There is a first grain boundary 102 between adjacent P-type grains 101, and there is a second grain boundary 202 between adjacent N-type grains 201. The width of the first grain boundary 102 is smaller than the width of the second grain boundary 202. This reduces the recombination of holes at the grain boundary, enhances the electron transport efficiency, improves the photoelectric conversion efficiency of the solar cell. At the same time, it can make the overall stress of the silicon wafer more balanced, reduce the possibility of the silicon wafer bending, and ultimately improve the manufacturing yield of solar cells.

[0061] In some embodiments, the silicon substrate has a light-facing surface and a backlight-facing surface that are oppositely arranged, and both the first region and the second region are disposed on the backlight-facing surface.

[0062] The silicon substrate has two main surfaces, a light-facing surface and a backlight-facing surface. The light-facing surface directly faces sunlight and is directly exposed to light, while the backlight-facing surface is the other side, and the two surfaces are oppositely arranged.

[0063] Both the first region and the second region are disposed on the backlight surface, that is, both the P-type polysilicon layer and the N-type polysilicon layer are disposed on the backlight surface. Generally, the first region and the second region are arranged alternately. Specifically, a plurality of first regions and a plurality of second regions are arranged alternately along a first direction, and both the first region and the second region extend along a second direction, and the second direction intersects with the first direction. The first region and the second region may be arranged alternately along the lateral direction of the silicon substrate and both extend along the longitudinal direction, that is, the first direction may be the lateral direction of the back contact battery, and the second direction may be the longitudinal direction of the back contact battery, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction may also be other directions. For example, the two may be the diagonal directions of the silicon substrate respectively, and specific details are not limited herein.

[0064] In this embodiment, the P-type polysilicon layer and the N-type polysilicon layer are disposed on the backlight surface. The polysilicon layer on the backlight surface can effectively collect and transport carriers, and at the same time reduce the reflection loss of photons on the backlight surface, which can optimize the collection and transport of carriers and improve the photoelectric conversion efficiency of the solar cell.

[0065] In some embodiments, the width of the first grain boundary 102 is less than 10 nm.

[0066] Multiple samples with different widths of the first grain boundary 102 are tested. The experimental results show that when the width of the first grain boundary 102 is less than 10 nm, the carrier lifetime is significantly improved. For example, when the width of the first grain boundary 102 is 7 nm, the carrier lifetime is 200 μs; while when the width of the first grain boundary 102 is 12 nm, the carrier lifetime is only 100 μs. Through statistical analysis of the experimental data, it can be determined that when the width of the first grain boundary 102 is less than 10 nm, the recombination of carriers at the grain boundary can be effectively reduced, thereby improving the carrier lifetime.

[0067] Furthermore, when the width of the first grain boundary 102 is in the range of 7-8 nm, the transport and recombination rate of carriers can be further optimized, the recombination of carriers at the grain boundary can be significantly reduced, and the carrier lifetime can be improved.

[0068] In some embodiments, the width of the second grain boundary 202 is greater than 10 nm.

[0069] In an N-type semiconductor, due to the doping of pentavalent impurities (such as phosphorus), there are differences in the size and electronic structure between the impurity atoms and silicon atoms. When the width of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will be stretched or compressed, and the cumulative effect of this distortion is more obvious in the grain boundary region, thereby generating greater stress.

[0070] Multiple samples with different widths of the second grain boundary 202 were tested. The experimental results show that when the width of the second grain boundary 202 is greater than 10 nm, a good balance with the stress in the P region can be achieved, and the stress concentration phenomenon inside the silicon wafer will be alleviated. This is beneficial to improving the stability of the silicon wafer during subsequent processing, such as in lithography, etching and other processes, reducing pattern deformation and dimensional deviation caused by stress. At the same time, it also helps to improve the long-term stability and reliability of the solar cell, reducing material fatigue and performance degradation problems caused by stress.

[0071] Furthermore, the width of the second grain boundary 202 is in the range of 10 - 22 nm. If the width of the second grain boundary is too large and exceeds the stress balance range that the silicon wafer can withstand, it may also lead to stress imbalance inside the silicon wafer, increasing the risk of silicon wafer breakage and reducing the manufacturing yield of the solar cell. Setting the width of the second grain boundary 202 in the range of 10 - 22 nm can better achieve stress balance, reduce material fatigue and performance degradation problems caused by stress, and improve the overall performance of the battery.

[0072] In some embodiments, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202.

[0073] Grain boundaries not only have width but also depth. The grain boundary depth refers to the vertical distance that the grain boundary extends inside the material, usually measured from the surface and extending into the material. The depth of the grain boundary can be measured by observing the cross-section of the sample using a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0074] The grain boundary depth affects the transport path of carriers in the material. Deeper grain boundaries may form more complex transport channels, affecting the flow efficiency of carriers. The grain boundary depth is also closely related to the defect distribution at the grain boundary. Deeper grain boundaries may contain more defects, increasing the probability of carrier recombination.

[0075] The depth of the first grain boundary 102 is less than the depth of the second grain boundary 202. Holes are the main carriers in the P-type grain 101, and holes are prone to recombination with electrons at the grain boundary. The shallower depth of the first grain boundary 102 can reduce the residence time of holes at the grain boundary and lower the recombination rate. While electrons are the main carriers in the N-type grain 201, and electrons require a longer transport path at the grain boundary. The greater depth of the second grain boundary 202 can enhance the transport efficiency of electrons and reduce losses during the transport process.

[0076] A grain boundary is the interfacial region between different grains, with irregular atomic arrangements, a large number of lattice defects such as dislocations and vacancies, and may also be enriched with impurity atoms. When the grain boundary becomes deeper, it means that the range of this region with defects and impurities expands in the direction perpendicular to the grain surface.

[0077] When electrons are transported in an N-type semiconductor, they need to move freely in the lattice. After the grain boundaries become deeper, electrons will encounter more of these defects and impurities during the movement process. The defects and impurities will form energy traps, and electrons may be trapped by the traps, deviate from their original movement paths, and even be bound in the traps. This leads to a decrease in the electron mobility. The electrons that could originally move rapidly in a directional manner to form a current now need to spend more time and energy to overcome these obstacles, thereby reducing the electron transport efficiency.

[0078] In the second region, the number of free electrons far exceeds the number of holes, and electrons are the majority carriers (majority carriers). Even if the deepening of the second grain boundary 202 hinders the transport of a part of the electrons, compared with the huge electron population, the affected electrons are only a small part, so the impact on the overall efficiency is not significant.

[0079] In the first region, holes are the majority carriers, while electrons are the minority carriers. However, here we are discussing the holes that participate in conduction and energy conversion during the interaction process with the second region. The number of these holes is relatively small and they are minority carriers.

[0080] When the first grain boundary 102 becomes deeper, the defects and impurities at the first grain boundary 102 increase, and holes are more likely to be trapped and recombined by these traps during the transport process. Since the number of holes itself is small, the loss of each hole has a relatively large impact on the overall carrier transport. In a solar cell, the smooth transport of holes is crucial for converting light energy into electrical energy. The deepening of the first grain boundary 102 leads to a significant reduction in the hole transport efficiency, resulting in a significant decrease in the number of holes reaching the electrode, thus seriously affecting the current output and photoelectric conversion efficiency of the battery, so the impact on the overall efficiency is very large.

[0081] In this embodiment, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202, which can reduce recombination and thus improve the photoelectric conversion efficiency of the cell.

[0082] In some embodiments, the depth of the first grain boundary 102 is less than 15 nm.

[0083] The shallower depth of the first grain boundary 102 can reduce the defect density at the grain boundary. The shallow grain boundary can limit the formation and expansion of defects, reduce the number of hole recombination centers, thereby reducing the recombination rate of holes at the grain boundary, and thus increasing the hole lifetime.

[0084] Multiple samples with different depths of the first grain boundary 102 were tested. The experimental results show that when the depth of the first grain boundary 102 is less than 15 nm, the hole lifetime is significantly improved. For example, when the depth of the first grain boundary 102 is 10 nm, the hole lifetime is 250 μs; while when the depth of the first grain boundary 102 is 18 nm, the hole lifetime is only 120 μs. By statistically analyzing the experimental data, it can be determined that when the depth of the first grain boundary 102 is less than 15 nm, the hole lifetime is longer.

[0085] Furthermore, when the depth of the first grain boundary 102 is in the range of 8 - 14 nm, the hole lifetime reaches the optimal value, thereby improving the overall performance of the device.

[0086] In some embodiments, the depth of the second grain boundary 202 is greater than 10 nm.

[0087] In an N-type semiconductor, due to the doping of pentavalent impurities (such as phosphorus), there are differences in the size and electronic structure between the impurity atoms and silicon atoms. When the depth of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will be stretched or compressed, and the cumulative effect of this distortion is more obvious in the grain boundary region, thus generating greater stress.

[0088] Multiple samples with different depths of the second grain boundary 202 were tested. The experimental results show that when the depth of the second grain boundary 202 is greater than 10 nm, a good balance with the stress in the P region can be achieved, and the stress concentration phenomenon inside the silicon wafer will be alleviated. This is beneficial to improving the stability of the silicon wafer during subsequent processing. For example, in processes such as lithography and etching, it can reduce pattern deformation and dimensional deviation caused by stress. At the same time, it also helps to improve the long-term stability and reliability of the solar cell, and reduce material fatigue and performance degradation problems caused by stress.

[0089] Furthermore, the depth of the second grain boundary 202 is in the range of 15 - 24 nm. If the depth of the second grain boundary is too large and exceeds the stress balance range that the silicon wafer can withstand, it may also cause stress imbalance inside the silicon wafer, increase the risk of silicon wafer breakage, and reduce the manufacturing yield of the solar cell. Setting the depth of the second grain boundary 202 in the range of 15 - 24 nm can better achieve stress balance, reduce material fatigue and performance degradation problems caused by stress, and improve the overall performance of the battery.

[0090] In some embodiments, the number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region.

[0091] The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. The unit area is a preset specific region, and the side length, area, and shape of this specific region are all fixed. The specific shape of this specific region can be square, circular, or other shapes, which are not limited here.

[0092] When the specific region is set within the first region, the specific region can be set at any position within the first region, and the number of P-type grains 101 falling within this specific region is a; when the specific region is set within the second region, the specific region can be set at any position within the second region, and the number of N-type grains 201 falling within this specific region is b, and a > b.

[0093] The number of P-type grains 101 per unit area is greater than the number of N-type grains 201 per unit area, which means that the average area of P-type grains 101 is smaller than the average area of N-type grains 201. This is because within the same area, if the number of a certain type of grain is smaller, then the area occupied by each grain is relatively larger. For example, if there are more P-type grains 101 in a unit area, then the average area occupied by each P-type grain 101 will be smaller than the average area of the fewer N-type grains 201.

[0094] It can be understood that although the average area of P-type grains 101 is smaller than the average area of N-type grains 201, this does not exclude the existence of one or more P-type grains 101 in the first region whose area is larger than the area of any N-type grain 201 in the second region. These smaller P-type grains 101 may be due to local conditions during the material growth process, non-uniformity of doping distribution, or other factors. The average area is a statistical value that reflects the overall trend, rather than the specific situation of each individual. In actual materials, the grain sizes may have a certain distribution range, some P-type grains 101 may be smaller, while some N-type grains 201 may be larger.

[0095] On the one hand, when the solar cell is illuminated, the silicon substrate absorbs photon energy to generate electron-hole pairs. In this structure with polysilicon layers of different doping types, the P-type polysilicon layer is rich in holes, and the N-type polysilicon layer is rich in electrons. The main function of the P-type polysilicon layer is to transport holes. More P-type grains 101 can provide more transport channels, through which holes can move more efficiently towards the corresponding electrodes of the cell. Since the hole migration within each grain is relatively smooth, the network structure formed by numerous grains can reduce the hindrance during hole transport, lower the probability of hole recombination, and improve the hole collection efficiency. Due to the generation of more photo-generated carriers in the P-type region, under the action of the P-N junction, these carriers will diffuse towards the N-type region. At this time, although the number of grains per unit area in the N-type region is relatively small, it can form a good match with the carriers generated in the P-type region. The N-type region has sufficient space and ability to receive the electrons diffused from the P-type region. The synergy with the N-type region avoids the increase in recombination caused by excessive carrier concentration, ensuring the effective separation and transport of carriers.

[0096] On the other hand, the relatively large number of P-type grains 101 in the P-type polysilicon layer means that there are more grain boundaries. These interfaces can serve as effective regions for light absorption. When light irradiates the solar cell, more P-type grains 101 can interact with the light, increasing the probability of light absorption. After the light is absorbed, more electron-hole pairs, that is, photo-generated carriers, will be excited, thus improving the generation efficiency of photo-generated carriers. The numerous P-type grains 101 form a complex microstructure, and the light will undergo multiple scatterings among these grains. The scattered light has a longer propagation path inside the cell and has more opportunities to be absorbed, further increasing the amount of light absorbed and thus increasing the generation of photo-generated carriers.

[0097] Furthermore, due to the differences in their doping types and microstructures, the P-type polysilicon layer and the N-type polysilicon layer have different absorption and response characteristics to light of different wavelengths. The different numbers of grains per unit area in the first region and the second region enable the solar cell to achieve effective light absorption and carrier generation in a wider spectral range. For example, the P-type polysilicon layer may have an advantage in light absorption at certain specific wavelengths, while the N-type polysilicon layer performs better in light absorption at other wavelengths. By reasonably setting the number of grains per unit area, the response of the cell to the entire solar spectrum can be optimized, improving the power generation ability of the cell under different illumination conditions.

[0098] In this embodiment, a first region and a second region are respectively provided on a silicon substrate. A P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201. The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. The characteristics of P-type and N-type semiconductors and the function of the P-N junction are fully utilized to improve the generation efficiency of photo-generated carriers, optimize the separation and transmission of carriers, etc., and finally improve the photoelectric conversion efficiency of the solar cell.

[0099] In some embodiments, the total perimeter of the P-type grains 101 per unit area is greater than the total perimeter of the N-type grains 201 per unit area.

[0100] The perimeter refers to the total length of the boundary line of a geometric figure. For a grain, the perimeter refers to the total length of the grain boundary. The total perimeter refers to the sum of the perimeters of all individual grains per unit area.

[0101] The total perimeter of the grains per unit area is mainly affected by two factors: the number of grains, the more grains per unit area, the usually larger the total perimeter; the ruggedness of the grain boundary, the more rugged the grain boundary (i.e., the more complex the shape), the larger the perimeter of a single grain, and thus the larger the total perimeter.

[0102] Specific examples are given to illustrate the influence of the number of grains and the ruggedness of the grain boundary on the total perimeter of the grains per unit area:

[0103] First example: Assume that the unit area is 1 square centimeter, and 20 first grains are provided per unit area. Each grain has a smooth and flat boundary, and the perimeter of a single grain is 0.1 centimeter. Then the total perimeter is: 20×0.1 = 2 centimeters.

[0104] 10 second grains are provided per unit area. Each grain has a very rugged boundary, and the perimeter of a single grain is 0.2 centimeter. Then the total perimeter is: 10×0.2 = 2 centimeters.

[0105] The number of second grains is less, but the boundary is rugged, and the total perimeter is 2 centimeters. The number of first grains is more, but the boundary is smooth, and the total perimeter is also 2 centimeters. In this example, although the number of second grains is less than that of the first grains, due to the rugged boundary of the second grains, the perimeter of a single grain is larger, and finally the total perimeters of the two are equal.

[0106] Second example: Assume that the unit area is 1 square centimeter, and 20 first grains are provided per unit area. Each grain has a smooth and flat boundary, and the perimeter of a single grain is 0.1 centimeter. Then the total perimeter is: 20×0.1 = 2 centimeters.

[0107] There are 10 second grains set within the unit area. The boundary of each grain is very rugged, and the perimeter of a single grain is 0.3 cm. Then the total perimeter is: 10 × 0.3 = 3 cm.

[0108] The number of second grains is small, but the boundary is rugged, and the total perimeter is 3 cm. The number of first grains is large, but the boundary is smooth, and the total perimeter is 2 cm, which is greater than the total perimeter of the second grains within the unit area. In this example, the total perimeter of the second grains is greater than that of the first grains. Although the number of second grains is small, the ruggedness of their boundaries significantly increases the perimeter of a single grain, resulting in a larger total perimeter.

[0109] Third example: Assume the unit area is 1 square centimeter. There are 20 first grains set within the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 cm. Then the total perimeter is: 20 × 0.1 = 2 cm.

[0110] There are 10 second grains set within the unit area. The boundary of each grain is rugged, and the perimeter of a single grain is 0.15 cm. Then the total perimeter is: 10 × 0.15 = 1.5 cm.

[0111] The number of second grains is small, but the boundary is rugged, and the total perimeter is 1.5 cm. The number of first grains is large, but the boundary is smooth, and the total perimeter is 2 cm. The number of second grains is less than that of the first grains, and the ruggedness of the boundaries of the second grains is greater than that of the first grains. However, the impact of the ruggedness of the second grains on the total perimeter increment is less than the impact of the number of the first grains on the total perimeter increment, making the total perimeter of the second grains less than that of the first grains. That is, the total perimeter of the first grains is greater than that of the second grains.

[0112] Fourth example: Assume the unit area is 1 square centimeter. There are 20 first grains set within the unit area. The ruggedness of the boundary of each grain is similar to that of the second grains, and the perimeter of a single grain is also 0.2 cm. Then the total perimeter is: 20 × 0.2 = 4 cm.

[0113] There are 10 second grains set within the unit area. The perimeter of a single grain is 0.2 cm. Then the total perimeter is: 10 × 0.2 = 2 cm.

[0114] The number of second grains is less than that of the first grains, and the ruggedness of the boundaries of the second grains is similar to that of the first grains, and the perimeter of a single grain is the same, making the total perimeter of the second grains less than that of the first grains. It can be understood that when the ruggedness of the second grains is less than that of the first grains, it also holds that the total perimeter of the second grains is less than that of the first grains. That is, the total perimeter of the first grains is greater than that of the second grains.

[0115] In this embodiment, the total perimeter of the P-type grains 101 per unit area is greater than the total perimeter of the second grains per unit area, which may be similar to the third example or similar to the fourth example. The larger total perimeter indicates that the P-type grains 101 have more boundaries. That is to say, the N-type grains 201 have fewer boundaries, which can reduce the recombination of carriers at the grain boundaries, is conducive to improving the transport efficiency of carriers, and improving the photoelectric conversion efficiency of the solar cell.

[0116] As Figure 5 and Figure 6 shown, in some embodiments, the number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region.

[0117] The protrusion is relative to a reference plane, and the part of some P-type grains 101 or N-type grains 201 that is higher than the reference plane in height. For the P-type polysilicon layer, the reference plane usually refers to the plane where most of the P-type polysilicon layer is located in the first region. For the N-type polysilicon layer, the reference plane usually refers to the plane where most of the N-type polysilicon layer is located in the second region.

[0118] In the first region, P-type grains 101 protrude from the reference plane of the first region at multiple positions. Specifically, one P-type grain 101 can protrude from the reference plane of the first region at each of multiple positions, multiple adjacent P-type grains 101 can protrude from the reference plane of the first region at each of multiple positions, or one P-type grain 101 can protrude from the reference plane of the first region at some of the multiple positions, and multiple adjacent P-type grains 101 can protrude from the reference plane of the first region at the other part of the multiple positions.

[0119] Similarly, in the second region, N-type grains 201 protrude from the reference plane of the second region at multiple positions. Specifically, one N-type grain 201 can protrude from the reference plane of the second region at each of multiple positions, multiple adjacent N-type grains 201 can protrude from the reference plane of the second region at each of multiple positions, or one N-type grain 201 can protrude from the reference plane of the second region at some of the multiple positions, and multiple adjacent N-type grains 201 can protrude from the reference plane of the second region at the other part of the multiple positions.

[0120] The number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region. The unit area is to preset a specific region, and the side length, area, and shape of this specific region are all fixed. The specific shape of this specific region can be square, circular, or other shapes, which are not limited here.

[0121] When the specific area is set within the first area, the specific area can be set at any position within the first area, and the number of protruding P-type grains 101 within the specific area is a; when the specific area is set within the second area, the specific area can be set at any position within the second area, and the number of protruding N-type grains 201 within the specific area is b, where a < b.

[0122] The P-type polysilicon layer is mainly responsible for the transport of holes, while the N-type polysilicon layer is mainly responsible for the transport of electrons. The protruding grains will increase the effective surface area, thus affecting the transport and recombination of carriers. The less protrusion of the P-type grains 101 in the first area can reduce surface defects and carrier recombination, and improve the hole transport efficiency. The protruding grains can increase the scattering and absorption of light, and reduce the light reflection loss. The more protrusion of the N-type grains 201 in the second area can make more effective use of the incident light and improve the photoelectric conversion efficiency.

[0123] In this embodiment, the first area and the second area are respectively set on the silicon substrate. A P-type polysilicon layer is set within the first area, and the P-type polysilicon layer includes a number of P-type grains 101; an N-type polysilicon layer is set within the second area, and the N-type polysilicon layer includes a number of N-type grains 201. The number of protruding P-type grains 101 per unit area in the first area is less than the number of protruding N-type grains 201 per unit area in the second area, which can ensure a higher hole transport efficiency in the first area and a higher electron collection efficiency in the second area. By increasing the light absorption and reducing the carrier recombination, the photoelectric conversion efficiency of the solar cell is significantly improved.

[0124] In some embodiments, the protruding height of the P-type grains 101 is less than the protruding height of the N-type grains 201.

[0125] The fact that the protruding height of the P-type grains 101 is less than the protruding height of the N-type grains 201 is a description of the average state, that is, the average protruding height of the P-type grains 101 per unit area is less than the average protruding height of the N-type grains 201 per unit area. There may be individual P-type grains 101 with a protruding height greater than that of the N-type grains 201, but the influence on the average trend is weak and will not be discussed separately.

[0126] It can be understood that the protruding height of the P-type grains 101 refers to the distance between the highest point of the protrusion of the P-type grains 101 and the reference plane of the first area. The protruding height of the N-type grains 201 refers to the distance between the highest point of the protrusion of the N-type grains 201 and the reference plane of the second area.

[0127] On the one hand, the N-type crystal 201 has a relatively high protrusion height, which can play a better role in light scattering. When light irradiates the battery surface, the relatively high N-type crystal 201 causes the light to scatter multiple times on its surface, extending the propagation path of the light inside the battery. This increases the chance of the light being absorbed by the P-type semiconductor, as the P-type semiconductor is mainly responsible for absorbing photons and generating electron-hole pairs. The P-type crystal 101 is relatively low and does not overly obstruct the propagation of light, ensuring that the light can effectively reach the P-type region for photoelectric conversion. The relatively high N-type crystal 201 can change the incident angle of the light, enabling more light to enter the battery interior rather than being reflected, thereby improving the light utilization rate.

[0128] On the other hand, after electrons and holes are generated under light illumination, they need to be effectively separated and collected. The relatively high N-type crystal 201 can provide a larger surface area, which is beneficial for the rapid collection of electrons. As the majority carriers in the N-type semiconductor, electrons can reach the electrode more quickly through the N-type crystal 201. The P-type crystal 101 is relatively low, reducing the recombination probability of holes during transmission. Because when holes are transmitted in the P-type semiconductor, if they pass through too many interfaces and obstacles, they are prone to recombine with electrons and be lost. The relatively low P-type crystal 101 enables the holes to be transmitted to the electrode more smoothly, thereby improving the carrier collection efficiency.

[0129] In this embodiment, the protrusion height of the P-type crystal grains 101 is less than that of the N-type crystal grains 201, which can optimize the carrier transmission and collection efficiency.

[0130] In some embodiments, the protrusion height of the P-type crystal grains 101 is 1 - 10 nm.

[0131] The specific height value can precisely control the carrier transmission path and recombination rate, further optimizing the battery performance. For example, the P-type crystal grains 101 with a height of 1 - 10 nm can reduce surface recombination and increase the carrier lifetime.

[0132] In some embodiments, the protrusion height of the N-type crystal grains 201 is 1 - 15 nm.

[0133] The specific height value can precisely control the electron collection efficiency, further optimizing the battery performance. For example, the N-type crystal grains 201 with a height of 1 - 15 nm can enhance electron collection and increase the short-circuit current of the battery.

[0134] In some embodiments, the thickness of a single P-type crystal grain 101 and / or a single N-type crystal grain 201 is non-uniform.

[0135] Specifically, it may be that at least one P-type grain 101 has a non-uniform thickness while the thicknesses of all N-type grains 201 are uniform, or at least one N-type grain 201 has a non-uniform thickness while the thicknesses of all P-type grains 101 are uniform, or at least one P-type grain 101 has a non-uniform thickness and at least one N-type grain 201 has a non-uniform thickness.

[0136] The non-uniform thickness of a single grain means that within the area occupied by each grain, there are differences in thickness at different positions. Specifically, the thickness of a grain refers to the vertical distance between the top surface of the grain and the reference plane (i.e., the plane where most of the P-type polysilicon layer or N-type polysilicon layer is located).

[0137] Within a certain area of a single grain, the thickness may be thicker in one area and thinner in another area. This thickness non-uniformity can be a continuous gradual change or a sudden stepped change.

[0138] Grains with non-uniform thickness can optimize the carrier transport path and recombination rate. Thicker areas can enhance the carrier collection efficiency, while thinner areas can reduce carrier recombination, thereby improving the overall cell performance. At the same time, grains with non-uniform thickness can increase light scattering and absorption and reduce light reflection loss. Thicker areas can make more effective use of incident light and improve the photoelectric conversion efficiency.

[0139] In this embodiment, the non-uniform thickness of a single P-type grain 101 and / or a single N-type grain 201 is beneficial to improving the carrier collection efficiency and reducing carrier recombination.

[0140] As Figures 1 to 4 shown, in some embodiments, the undulation degree of the P-type grain 101 is greater than that of the N-type grain 201.

[0141] The surface morphologies of the P-type grain 101 and the N-type grain 201 are different, and the undulation degree of the P-type grain 101 is greater than that of the N-type grain 201.

[0142] The undulation degree refers to the degree of height fluctuation of the material surface relative to a certain reference plane, reflecting the complexity and irregularity of the material surface morphology. Specifically, the undulation degree can be quantified by measuring the height differences of each point on the surface relative to the reference plane. The reference plane is a preset reference plane, which can be an idealized, completely flat reference plane or a plane close to most of the material surface. The undulation degree is measured relative to the reference plane, and the choice of the reference plane directly affects the calculation result of the undulation degree. If the reference plane is chosen as the plane close to most of the material surface, then the measurement of the undulation degree will mainly reflect the height fluctuation of the surface relative to this plane, and this method is more intuitive and can be judged by observing the surface morphology.

[0143] By measuring the height of each point on the surface relative to the reference plane, the undulation can be calculated. The undulation of the P-type grain 101 is greater than that of the N-type grain 201, which means that the surface morphology of the P-type grain 101 is more complex than that of the N-type grain 201, with more protrusions 30 and / or depressions 40.

[0144] The fact that the undulation of the P-type grain 101 is greater than that of the N-type grain 201 means that there are more protrusions 30 and / or depressions 40 on the surface of the P-type grain 101 than on the surface of the N-type grain 201 ( Figures 1 to 4 in which the protrusions 30 are white positions and the depressions 40 are black positions). Specifically, it can be that there are more protrusions 30 on the surface of the P-type grain 101 than on the surface of the N-type grain 201, and the number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; it can be that the number of protrusions 30 on the surface of the P-type grain 101 is greater than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is a), and the number of depressions 40 on the surface of the P-type grain 101 is less than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is b), and a > b; it can be that there are more protrusions 30 on the surface of the P-type grain 101 than on the surface of the N-type grain 201, and the number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; it can be that the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is c), and the number of protrusions 30 on the surface of the P-type grain 101 is less than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is d), and c > d; it can also be that the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201, and the number of protrusions 30 on the surface of the P-type grain 101 is greater than the number of protrusions 30 on the surface of the N-type grain 201.

[0145] It can be understood that the fact that the undulation of the P-type grain 101 is greater than that of the N-type grain 201 is a description of the average state, that is, the average undulation of the P-type grain 101 is greater than the average undulation of the N-type grain 201. Since the growth of the grains is affected by many factors, there may be some P-type grains 101 with undulations less than those of some N-type grains 201, but this does not affect the overall trend of the average undulation of the grains.

[0146] The undulation degree of the material surface is not only related to the number of depressions 40 and / or protrusions 30 on the material surface, but also positively correlated with the depth of the depressions 40 and the depth of the protrusions 30. The deeper the depth of the depressions 40 and the higher the height of the protrusions 30, the greater the undulation degree of the material surface. However, on the grain surface, due to the relatively small grain size itself, the sizes of the depressions 40 and / or protrusions 30 on the grains are even smaller, and the influence of the number of depressions 40 and / or protrusions 30 on the undulation degree is much greater than the influence of the depth of the depressions 40 and the depth of the protrusions 30 on the undulation degree. Therefore, in this embodiment, the influence of the depth of the depressions 40 and the depth of the protrusions 30 on the undulation degree is ignored and not discussed in detail.

[0147] It can be understood that the surface of the P-type grains 101 has more protrusions 30 and / or depressions 40 than the surface of the N-type grains 201. The larger undulation degree may increase the surface area of the grain surface, thereby affecting light absorption and the generation and transport of carriers. A larger undulation degree means more light scattering and reflection. The surface of the P-type grains 101 has a larger undulation degree, and light will be reflected and scattered multiple times on the grain surface, increasing the path length of photons in the P-type region and the residence time of photons in the P-type region, thereby improving the light absorption rate. While the undulation degree of the N-type grains 201 is smaller, that is, the surface of the N-type grains 201 is relatively flat. The smaller undulation degree helps to reduce surface defects and improve the transport efficiency of carriers. The combined effect helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0148] In this embodiment, by respectively setting a first region and a second region on the silicon substrate, a P-type polysilicon layer is arranged in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is arranged in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201, and the undulation degree of the P-type grains 101 is greater than that of the N-type grains 201. The absorption efficiency of photons in the first region is increased, and the transport efficiency of carriers in the second region is improved, thereby improving the overall photoelectric conversion efficiency of the solar cell.

[0149] In some embodiments, the number of depressions 40 on the P-type grains 101 is greater than the number of depressions 40 on the N-type grains 201.

[0150] The depression 40 refers to a tiny concave region on the grain surface. The fact that the number of depressions 40 on the P-type grains 101 is greater than the number of depressions 40 on the N-type grains 201 is a description of the average state, that is, the average number of depressions 40 on the P-type grains 101 is greater than the average number of depressions 40 on the N-type grains 201. There may be individual P-type grains 101 with the number of depressions 40 less than that of the N-type grains 201, but the influence on the average trend is weak and not discussed separately.

[0151] The position of the depression 40 affects the scattering and absorption of light. More depressions 40 increase the light scattering ability on the surface of the P-type grains 101, enabling the incident light to be more effectively captured and absorbed within the P-type region. This helps to improve the photoelectric conversion efficiency of the P-type region, thereby enhancing the performance of the entire solar cell.

[0152] In this embodiment, the number of depressions 40 on the P-type grains 101 is greater than the number of depressions 40 on the N-type grains 201. The presence of the depressions 40 causes the light to undergo multiple reflections and scatterings on the grain surface, increasing the path length of the photons within the P-type region, thereby improving the light absorption efficiency.

[0153] In some embodiments, the number of protrusions 30 on the P-type grains 101 is greater than the number of protrusions 30 on the N-type grains 201.

[0154] The protrusion 30 refers to a tiny upward convex region on the grain surface. Similar to the depression 40, the fact that the number of protrusions 30 on the P-type grains 101 is greater than the number of protrusions 30 on the N-type grains 201 is a description of the average state, that is, the average number of protrusions 30 of the P-type grains 101 is greater than the average number of protrusions 30 of the N-type grains 201. There may be individual P-type grains 101 with the number of protrusions 30 less than that of the N-type grains 201, but the impact on the average trend is weak and will not be discussed separately.

[0155] The position of the protrusion 30 also affects the scattering and absorption of light. A larger number of protrusions 30 further enhances the light scattering effect on the surface of the P-type grains 101, increasing the residence time of the photons within the P-type region and improving the light absorption efficiency. This helps to enhance the overall performance of the solar cell.

[0156] In this embodiment, the number of protrusions 30 on the P-type grains 101 is greater than the number of protrusions 30 on the N-type grains 201. The presence of the protrusions 30 causes the light to undergo multiple reflections and scatterings on the grain surface, increasing the path length of the photons within the P-type region, thereby improving the light absorption efficiency.

[0157] In some embodiments, the difference between the highest position and the lowest position on the P-type grains 101 is 1 - 15 nm.

[0158] Testing multiple different samples, the experimental results show that when the difference between the highest position and the lowest position on the P-type grains 101 is 1 - 15 nm, the light absorption efficiency increases rapidly.

[0159] In some embodiments, the difference between the highest position and the lowest position on the N-type grains 201 is 1 - 20 nm.

[0160] Multiple different samples were tested, and the experimental results showed that when the difference between the highest and lowest positions on the N-type grain 201 was 1 - 20 nm, the light absorption efficiency increased rapidly.

[0161] In some embodiments, a plurality of P-type grains 101 cover the surface of the entire first region.

[0162] A plurality of P-type grains 101 cover the entire first region and are arranged on the plane of the first region in a non-overlapping manner to ensure that the entire first region is completely covered. It does not exclude the existence of gaps between adjacent grains (grain boundaries formed due to the repulsive force between adjacent grains).

[0163] The fully covered P-type grains 101 ensure that there is no unutilized area within the first region, maximizing the light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0164] In this embodiment, a plurality of P-type grains 101 cover the surface of the entire first region, and the fully covered P-type grains 101 enable each part within the first region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0165] In some embodiments, a plurality of N-type grains 201 cover the surface of the entire second region.

[0166] A plurality of N-type grains 201 cover the entire first region and are arranged on the plane of the second region in a non-overlapping manner to ensure that the entire second region is completely covered. It does not exclude the existence of gaps between adjacent grains (grain boundaries formed due to the repulsive force between adjacent grains).

[0167] The fully covered N-type grains 201 ensure that there is no unutilized area within the second region, maximizing the light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0168] In this embodiment, a plurality of N-type grains 201 cover the surface of the entire second region, and the fully covered N-type grains 201 enable each part within the second region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0169] In some embodiments, at least one of the first region and the second region is a textured surface.

[0170] The textured surface structure is a surface treatment technology that increases the scattering and absorption of light by forming tiny uneven structures on the material surface. The textured surface is usually formed by methods such as chemical etching or mechanical polishing. Chemical etching uses specific etching agents to form tiny uneven structures on the material surface, while mechanical polishing forms similar uneven structures through mechanical force on the material surface.

[0171] Specifically, the first region and the second region are both velvet, that is, the P-type polysilicon layer and the N-type polysilicon layer are both velvet layers. It can be that the first region is a velvet surface and the second region is a polished surface, that is, the P-type polysilicon layer is a velvet layer and the N-type polysilicon layer is a polished surface layer. It can also be that the first region is a polished surface and the second region is a velvet surface, that is, the P-type polysilicon layer is a polished surface layer and the N-type polysilicon layer is a velvet layer. It can also be that the first region and the second region are both polished surfaces, that is, the P-type polysilicon layer and the N-type polysilicon layer are both polished surface layers.

[0172] The velvet structure can increase the scattering and reflection of light, extend the path of light in the material, and thus improve the light absorption efficiency. At least one of the first area and the second area is set as a velvet surface, which can improve the photoelectric conversion efficiency of the solar cell.

[0173] In some embodiments, both the first region and the second region are suede.

[0174] Specifically, both the P-type polysilicon layer and the N-type polysilicon layer are velvet layers. The double velvet structure can increase light scattering and absorption in the P-type polysilicon layer and the N-type polysilicon layer at the same time, optimize light absorption efficiency, and further improve the photoelectric conversion efficiency of the solar cell.

[0175] In some embodiments, both the first region and the second region are acid faceted.

[0176] Acid faceting is a type of velvet, which is a microstructure formed on the surface of a silicon wafer through acid etching technology. The etching depth and surface morphology can be controlled by adjusting the acid concentration, temperature and time to meet different application requirements.

[0177] The acid engraving forms an irregular concave-convex structure, which causes the light to be reflected and scattered multiple times on the surface, extending the path length of photons in the silicon wafer, thereby improving the light absorption efficiency. The irregular structure can effectively reduce the reflection loss of light, allowing more light energy to enter the interior of the silicon wafer.

[0178] Acid etching also increases the surface area of ​​the silicon wafer, provides more carrier transmission channels, improves charge separation and collection efficiency, and the microstructure of the acid-etched surface can capture carriers and reduce their recombination losses on the surface, thereby improving the photoelectric conversion efficiency.

[0179] In this embodiment, both the first region and the second region are subjected to acid faceting treatment, which can ensure uniform light absorption and carrier transport performance on the entire battery surface and avoid local performance differences.

[0180] In some embodiments, both the first region and the second region are polished surfaces.

[0181] The polished surface is a surface treatment technology that mechanically or chemically treats the material surface to be very smooth. Polishing usually uses polishing agents and polishing pads to mechanically treat the material surface to be very smooth. Chemical polishing uses specific chemical reagents to form a smooth surface on the material surface.

[0182] In this embodiment, both the first region and the second region are polished surfaces, that is, both the P-type polysilicon layer and the N-type polysilicon layer are polished layers. The polished surface can reduce surface defects and impurities and improve the carrier transport efficiency. Setting both the first region and the second region as polished surfaces can improve the carrier transport efficiency of the solar cell, reduce carrier recombination, and thus improve the photoelectric conversion efficiency.

[0183] In some embodiments, the roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer.

[0184] Roughness is a parameter that measures the flatness of the material surface. The higher the roughness, the lower the flatness of the material surface, and the lower the roughness, the higher the flatness of the material surface.

[0185] P-type polysilicon is usually formed by doping acceptor impurities such as boron (B). Boron atoms have a small size and cause less damage to the lattice structure during the doping process, making it easier to form a smooth surface. Moreover, P-type polysilicon is more likely to form a uniform grain structure during deposition and annealing. N-type polysilicon is usually formed by doping donor impurities such as phosphorus (P) or arsenic (As). Phosphorus and arsenic atoms have a large size and are likely to cause lattice distortion during the doping process. Due to the influence of doping atoms, the grain growth of N-type polysilicon may be uneven, resulting in an increase in surface roughness. The roughness of the P-type polysilicon layer being less than that of the N-type polysilicon layer is easier to achieve during processing and has a lower processing difficulty.

[0186] In terms of performance, the surface of the P-type polysilicon layer with a smaller roughness is smoother, reducing surface defects and trap states at grain boundaries, thereby reducing the recombination probability of carriers (electrons and holes) at the surface and grain boundaries. A lower carrier recombination rate can increase the carrier lifetime and efficiency of the device. At the same time, the interface quality between the P-type polysilicon layer and the N-type polysilicon layer is crucial for device performance. The roughness of the P-type polysilicon layer being less than that of the N-type polysilicon layer can form a more uniform and stable interface, reducing the interface state density and thus improving the electrical characteristics of the device.

[0187] Specifically, the root mean square roughness (RMS) of the material surface can be detected by an atomic force microscope (AFM). AFM uses a tiny probe (tip) to interact with the sample surface. When the probe approaches the sample surface, it is subjected to various forces, such as van der Waals forces and electrostatic forces. By detecting the changes in the forces between the probe and the sample surface, AFM can accurately measure the height changes of the probe during scanning on the sample surface. During the scanning process, the probe moves point by point along the sample surface, recording the height values of each point relative to the reference plane. By performing statistical analysis on these height values, the root mean square roughness can be calculated.

[0188] The larger the value of RMS, the higher the surface roughness of the material; the smaller the value of RMS, the smaller the surface roughness of the material.

[0189] For example, the RMS value of the surface of the detected P-type polysilicon layer sample is 1.736 nm, and the RMS value of the surface of the detected N-type polysilicon layer sample is 6.928 nm. Since 1.736 nm < 6.928 nm, it indicates that the roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer.

[0190] In this embodiment, based on the differences in the processing characteristics and physical characteristics between P-type and N-type polysilicon, the roughness of the P-type polysilicon layer being less than that of the N-type polysilicon layer can significantly reduce carrier recombination, improve carrier mobility, optimize interface characteristics, reduce leakage current, and improve the consistency and yield of the device.

[0191] In some embodiments, the surface of the N-type grain 201 has dense small holes.

[0192] The small holes refer to the tiny holes on the grain surface. The small holes on the surface of the N-type grain 201 are blind holes, and the small holes are densely distributed on the surface of the N-type grain 201. The small holes and the depressions 40 are two different surface structure features:

[0193] The size of the small holes is usually small, with a diameter possibly ranging from nanometers to micrometers (e.g., 0.1 micrometer to 1 micrometer), and the distribution of the small holes is very dense, with a large number of holes per unit area (e.g., hundreds of small holes per square micrometer). Compared with the small holes, the size of the depressions 40 is usually larger, with a diameter possibly ranging from micrometers to millimeters (e.g., 1 micrometer to 100 micrometers), and the distribution of the depressions 40 is relatively sparse, with a small number of depressions 40 per unit area (e.g., dozens of depressions 40 per square micrometer).

[0194] The depth of the small holes is relatively shallow, usually equivalent to or slightly smaller than the diameter (e.g., 0.1 micrometer to 1 micrometer), and the depth uniformity of the small holes is relatively high, with the overall surface being relatively flat. While the depth of the depressions 40 is relatively large, possibly much larger than its diameter (e.g., 1 micrometer to 10 micrometers), and the depth of the depressions 40 is uneven, possibly showing an obvious undulating state.

[0195] The small holes are usually regular or irregular circles or ellipses. The presence of the small holes makes the surface present a porous structure, similar to a sponge or honeycomb. The depression 40 is usually irregular in shape and may appear as a strip, a circle or an irregular polygon. The presence of the depression 40 makes the surface present an uneven state, similar to a gully or a pothole.

[0196] The presence of the small holes causes light to be reflected and scattered multiple times on the surface of the crystal grains, increasing the path length of photons in the N-type region, increasing the light scattering ability of the N-type grain surface, increasing the residence time of photons in the N-type region, improving the light absorption efficiency, and contributing to improving the overall performance of the solar cell.

[0197] In this embodiment, the surface of the N-type grain 201 has dense small holes, increasing the surface area and enhancing light scattering, and improving the light absorption efficiency.

[0198] Furthermore, the aperture of the small holes is 0.1 - 2 nm.

[0199] This embodiment also provides a battery module, including the solar cell in the above embodiment.

[0200] The beneficial effects of the battery module are similar to those of the solar cell and will not be elaborated here.

[0201] The battery module may include a plurality of back-contact solar cells. The plurality of back-contact solar cells in the battery module may be connected in series in sequence to form a battery string. Each battery string may be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between each solar cell can be realized by welding solder strips, and the connection between each battery string can be realized by a bus bar.

[0202] The battery module may further include a metal frame, a back sheet, a photovoltaic glass and a glue film (not shown in the figures). The glue film can be filled between the light-facing surface of the solar cell and the photovoltaic glass, the backlight surface and the back sheet, and adjacent solar cells, etc. As a filler, it can be a transparent colloid with good light transmission performance and aging resistance. For example, the glue film can adopt an EVA glue film or a POE glue film, which can be specifically selected according to the actual situation and is not limited here.

[0203] The photovoltaic glass can cover the glue film on the light-facing surface of the solar cell. The photovoltaic glass can be ultra-white glass, which has a high light transmittance, high transparency, and excellent physical, mechanical and optical properties. For example, the light transmittance of the ultra-white glass can reach more than 92%, and it can protect the solar cell with as little impact on the efficiency of the solar cell as possible. At the same time, the glue film can bond the photovoltaic glass and the solar cell together, and the presence of the glue film can seal and insulate the solar cell and prevent water and moisture.

[0204] The backsheet can be attached to the adhesive film on the backlight side of the solar cell. The backsheet can protect and support the solar cell, and has reliable insulation, water resistance and aging resistance. There are multiple choices for the backsheet, which can usually be tempered glass, plexiglass, aluminum alloy TPT composite film, etc., and its specific settings can be determined according to specific circumstances and are not limited here. The whole composed of the backsheet, solar cell, adhesive film and photovoltaic glass can be set on the metal frame. The metal frame serves as the main external support structure of the entire battery module and can stably support and install the battery module. For example, the battery module can be installed at the required installation position through the metal frame.

[0205] This embodiment also provides a photovoltaic system, including the battery module in the above embodiment.

[0206] The beneficial effects of the photovoltaic system are similar to those of the battery module and will not be elaborated here.

[0207] The photovoltaic system can be applied in photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be applied to devices or apparatuses that use solar energy for power generation, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be applied in all fields that require solar power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system can include a photovoltaic array, a combiner box and an inverter. The photovoltaic array can be an array combination of multiple battery modules. For example, multiple battery modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the combiner box, and the combiner box can collect the current generated by the photovoltaic array. After the collected current flows through the inverter and is converted into alternating current required by the commercial power grid, it is connected to the commercial power grid to achieve solar power supply.

[0208] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, the silicon substrate comprising a first region and a second region, a P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region; The P-type polysilicon layer includes a plurality of P-type crystal grains, and a first crystal boundary is formed between adjacent P-type crystal grains. The N-type polysilicon layer includes a plurality of N-type crystal grains, and a second crystal boundary is formed between adjacent N-type crystal grains. The width of the first crystal boundary is smaller than the width of the second crystal boundary.

2. The solar cell according to claim 1, characterized in that The silicon substrate has a light-facing surface and a backlight surface that are arranged opposite to each other, and the first area and the second area are both located on the backlight surface.

3. The solar cell according to claim 1, characterized in that The width of the first grain boundary is less than 10 nm.

4. The solar cell according to claim 3, characterized in that: The width of the first grain boundary is 7-8 nm.

5. The solar cell according to claim 1, characterized in that The width of the second grain boundary is greater than 10 nm.

6. The solar cell according to claim 5, characterized in that The width of the second grain boundary is 10 to 22 nm.

7. The solar cell according to claim 1, characterized in that The depth of the first grain boundary is smaller than the depth of the second grain boundary.

8. The solar cell according to claim 7, characterized in that The depth of the first grain boundary is less than 15 nm.

9. The solar cell according to claim 8, characterized in that The depth of the first grain boundary is 8-14 nm.

10. The solar cell according to claim 7, characterized in that: The depth of the second grain boundary is greater than 10 nm.

11. The solar cell according to claim 10, characterized in that The depth of the second grain boundary is 15-24 nm.

12. The solar cell according to claim 1, characterized in that: The first region and / or the second region is suede.

13. The solar cell according to claim 1, characterized in that: The first region and / or the second region is a polished surface.

14. A battery assembly, characterized in that: Comprising the solar cell described in any one of claims 1 to 13.

15. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 14.

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