Resistive random access memory and preparation method thereof

Abstract

The invention provides a resistive random access memory and a preparation method thereof, and belongs to the field of memory device manufacturing. The method comprises the following steps: forming a first electrode layer on the surface of a semiconductor substrate; a physical vapor deposition method is utilized, an oxide resistive layer with a preset cross section width is formed on the surface of the first electrode layer, the oxide resistive layer comprises a hafnium oxide layer with a first preset cross section width and a tantalum oxide layer with a second preset cross section width, the tantalum oxide layer grows on the surface of the hafnium oxide layer, and the tantalum oxide layer grows on the surface of the tantalum oxide layer; the second preset section width is greater than the first preset section width; and forming a second electrode layer on the surface of the tantalum oxide layer to obtain the resistive random access memory.

Description

Technical Field

[0001] The present invention relates to the field of manufacturing of storage devices, and particularly to a resistive random access memory and a method for preparing the same. Background Art

[0002] The resistive random access memory (RRAM) with the characteristics of high-density three-dimensional integration is one of the promising candidates for the next-generation non-volatile storage technology. However, the randomness of the formation and rupture of conductive filaments in the resistive layer of RRAM leads to poor performance uniformity and reliability of RRAM. The conductive filaments in the resistive layer play an irreplaceable role in the resistive switching process, and in continuous write-erase operations, the random growth and rupture of the conductive filaments in the resistive layer are the main reasons for the instability of the storage window during the resistive switching process. Therefore, controlling the growth and rupture of the conductive filaments in the resistive layer is an effective method to solve these problems. Summary of the Invention

[0003] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present invention provides a resistive random access memory and a method for preparing the same.

[0004] According to an embodiment of one aspect of the present invention, a method for preparing a resistive random access memory is provided, including: forming a first electrode layer on the surface of a semiconductor substrate; using physical vapor deposition to form an oxide resistive layer with a preset cross-sectional width on the surface of the first electrode layer, wherein the oxide resistive layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width, the tantalum oxide layer grows on the surface of the hafnium oxide layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width; forming a second electrode layer on the surface of the tantalum oxide layer to obtain the resistive random access memory.

[0005] According to an embodiment of the present invention, the cross-sectional width of the hafnium oxide layer is 5 - 50 nm, and the cross-sectional width of the tantalum oxide layer is 100 - 500 m.

[0006] According to an embodiment of the present invention, forming a first electrode layer on the surface of a semiconductor substrate includes: preprocessing the semiconductor substrate to obtain a preprocessed semiconductor substrate; using physical vapor deposition to deposit a nitride on the preprocessed semiconductor substrate to form the first electrode layer.

[0007] According to an embodiment of the present invention, the first electrode layer is a tantalum nitride layer, the thickness of the first electrode layer is 20 - 40 nm, and the cross-sectional width of the first electrode layer is 5 - 5 nm.

[0008] According to an embodiment of the present invention, using physical vapor deposition to form an oxide resistive layer on the surface of the first electrode layer includes: using physical vapor deposition to deposit a hafnium oxide layer on the surface of the first electrode layer; forming a tantalum oxide layer on the surface of the hafnium oxide layer to obtain the oxide resistive layer.

[0009] According to an embodiment of the present invention, the thickness of the hafnium oxide layer is 3 - 15 nm, and the thickness of the tantalum oxide layer is 10 - 15 nm.

[0010] According to an embodiment of the present invention, a tantalum oxide layer is formed on the surface of the hafnium oxide layer to obtain an oxide resistive switching layer, including: after applying a photoresist with a first preset cross-sectional width on the surface of the hafnium oxide layer, etching a part of the hafnium oxide layer and a part of the first electrode layer, and retaining the hafnium oxide layer and the first electrode layer with the first preset cross-sectional width; removing the photoresist on the surface of the hafnium oxide layer with the first preset cross-sectional width, and depositing an insulating layer on the surface of the hafnium oxide layer and around the hafnium oxide layer and the first electrode layer by chemical vapor deposition; chemically mechanically polishing a part of the insulating layer to expose the hafnium oxide layer, and depositing a tantalum oxide layer on the surface of the hafnium oxide layer and the remaining insulating layer by physical vapor deposition to form an oxide resistive switching layer.

[0011] According to an embodiment of the present invention, a second electrode layer is formed on the surface of the tantalum oxide layer to obtain a resistive random access memory, including: depositing a second electrode layer on the surface of the tantalum oxide layer, after applying a photoresist with a second preset cross-sectional width on the surface of the second electrode layer, etching from the surface of a part of the second electrode layer to a part of the tantalum oxide layer until the surface of the remaining insulating layer is exposed, and retaining the second electrode layer with the second preset cross-sectional width to the tantalum oxide layer to form a resistive random access memory.

[0012] According to an embodiment of the present invention, the thickness of the second electrode layer is 20 - 40 nm, and the second electrode layer is a titanium nitride layer.

[0013] According to an embodiment of another aspect of the present invention, a resistive random access memory prepared by the above method is provided.

[0014] According to an embodiment of the present invention, an oxide resistive switching layer is formed by sequentially depositing a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-section on the first electrode layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width, so that the growth and breakage of conductive filaments in the resistive switching layer can be controlled during the resistive switching process of the prepared resistive random access memory, to solve the technical problems of poor performance uniformity and poor reliability of the resistive random access memory caused by the random growth and breakage of conductive filaments in the resistive switching layer in the prior art, and further achieve controlling the growth and breakage of conductive filaments in the resistive switching layer and improving the performance uniformity of the resistive random access memory and the reliability of the storage window during the resistive switching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features and advantages of the present invention will become more apparent. In the drawings:

[0016] Figure 1Schematically shows a flowchart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention;

[0017] Figure 2 Schematically shows a schematic diagram of the principle of a resistive random access memory according to an embodiment of the present invention;

[0018] Figure 3 Schematically shows a schematic diagram of a method for manufacturing a resistive random access memory according to an embodiment of the present invention;

[0019] FIG. 4(a) schematically shows a schematic diagram of the operating voltage uniformity of a resistive random access memory according to an embodiment of the present invention;

[0020] FIG. 4(b) schematically shows a schematic diagram of the device resistance uniformity of a resistive random access memory according to an embodiment of the present invention;

[0021] FIG. 4(c) schematically shows a schematic diagram of the endurance of a resistive random access memory according to an embodiment of the present invention. Detailed implementation manners

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, many specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present invention. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0023] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The term "including" used herein indicates the presence of features, steps, operations, but does not exclude the presence or addition of one or more other features.

[0024] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0025] In the related art, the growth of the resistive switching layer is restricted by growing nanocolumns with a diameter of dozens of nanometers or the RRAM is grown into a conical shape. However, the shape of the RRAM grown by this process cannot be integrated with the CMOS process, and the materials of the RRAM grown based on this process are not suitable for mass production.

[0026] Based on this, the present invention provides a method for growing a resistive random access memory, including: forming a first electrode layer on the surface of a semiconductor substrate; using physical vapor deposition to form an oxide resistive switching layer with a preset cross-sectional width on the surface of the first electrode layer, wherein the oxide resistive switching layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width, the tantalum oxide layer grows on the surface of the hafnium oxide layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width; forming a second electrode layer on the surface of the tantalum oxide layer to obtain the resistive random access memory.

[0027] Figure 1 Schematically shows a flowchart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention.

[0028] As Figure 1 shown, the method may include: operation S101 to operation S103.

[0029] In operation S101, a first electrode layer is formed on the surface of a semiconductor substrate.

[0030] In operation S102, using physical vapor deposition, an oxide resistive switching layer with a preset cross-sectional width is formed on the surface of the first electrode layer, wherein the oxide resistive switching layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width, the tantalum oxide layer grows on the surface of the hafnium oxide layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width.

[0031] In operation S103, a second electrode layer is formed on the surface of the tantalum oxide layer to obtain the resistive random access memory.

[0032] According to an embodiment of the present invention, the semiconductor substrate may be Si or a semiconductor material that can be used as a substrate.

[0033] According to an embodiment of the present invention, the semiconductor substrate can be pretreated, for example, removing contaminants, surface residual moisture, and volatile substances on the surface of the semiconductor substrate, so that the surface of the semiconductor substrate becomes clean and flat.

[0034] According to an embodiment of the present invention, a nitride layer can be deposited on the surface of the pretreated semiconductor substrate by physical vapor deposition to form the first electrode layer. Physical vapor deposition may include magnetron sputtering and ion beam sputtering.

[0035] According to an embodiment of the present invention, the nitride layer may be a tantalum nitride layer, and the thickness of the first electrode layer may be 20 - 40 nm. For example, it may be 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm.

[0036] According to an embodiment of the present invention, the oxide resistive change layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width. The physical vapor deposition method may be used to first deposit a hafnium oxide layer with a preset thickness on the surface of the first electrode layer, such that the hafnium oxide layer completely covers the surface of the first electrode layer. The thickness of the hafnium oxide layer may be 3 - 15 nm. For example, it may be 3 nm, 6 nm, 9 nm, 12 nm, and 15 nm.

[0037] According to an embodiment of the present invention, a tantalum oxide layer may be formed on the surface of the deposited hafnium oxide layer. Specifically, a photoresist may be applied on the surface of the hafnium oxide layer, and then photolithography is performed on the photoresist to form a photoresist with a first preset cross-sectional width, exposing part of the hafnium oxide layer. Etching treatment is performed on the exposed part of the hafnium oxide layer until part of the hafnium oxide layer, part of the first electrode layer under the hafnium oxide layer, and the substrate are etched away.

[0038] According to an embodiment of the present invention, the photoresist on the surface of the hafnium oxide layer may be removed until the hafnium oxide layer with a first preset cross-sectional width is exposed. The cross-sectional width of the first electrode layer is 5 - 50 nm. For example, it may be 5 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, and 50 nm.

[0039] According to an embodiment of the present invention, an insulating layer may be grown on the surface and around the hafnium oxide layer by chemical vapor deposition, such that the deposition layer formed by the hafnium oxide layer and the first electrode layer is wrapped in the insulating layer.

[0040] According to an embodiment of the present invention, the insulating layer may be a silicon nitride layer or a silicon carbide layer. Chemical mechanical polishing is performed on the insulating layer on the hafnium oxide layer until the hafnium oxide layer is exposed.

[0041] According to an embodiment of the present invention, a tantalum oxide layer is further deposited on the surface of the hafnium oxide layer and the remaining insulating layer by physical vapor deposition method, and a second electrode layer is deposited on the tantalum oxide layer.

[0042] According to an embodiment of the present invention, the thickness of the tantalum oxide layer may be 10 - 15 nm. For example, it may be 10 nm, 12 nm, and 15 nm; the second electrode layer may be a titanium nitride layer, and the thickness of the second electrode layer may be 20 - 40 nm. For example, it may be 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm.

[0043] According to an embodiment of the present invention, a glue coating process can be performed on the surface of the second electrode layer, and then a photolithography process is carried out on the photoresist to form a photoresist with a second preset cross-sectional width. The second electrode layer without the photoresist is etched until the surface of the insulating layer is exposed, forming a tantalum oxide layer and a second electrode layer with a second preset cross-sectional width, thereby obtaining a resistive random access memory (RRAM).

[0044] According to an embodiment of the present invention, the second preset cross-sectional width can be 100 - 500 nm. For example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm. The width of the second preset cross-section is greater than the width of the first preset cross-section.

[0045] According to an embodiment of the present invention, the hafnium oxide layer with the first preset cross-sectional width and the tantalum oxide layer with the second preset cross-sectional width form an oxide resistive change layer, so as to control the growth width of the resistive change layer when preparing the resistive random access memory, and avoid the instability of the performance of the resistive random access memory caused by the random growth of the resistive change layer.

[0046] Figure 2 The principle schematic diagram of the resistive random access memory according to an embodiment of the present invention is schematically shown.

[0047] As Figure 2 shown, the resistive random access memory prepared by the present invention can have an upper-wide and lower-narrow structure. The first preset cross-sectional width of the hafnium oxide ( ) layer is less than the second preset cross-sectional width of the tantalum oxide ( ) layer. When a set operation is performed, a voltage is applied to the upper electrode (i.e., the second electrode layer) of the resistive random access memory. Since the cross-sectional width of the hafnium oxide ( ) layer is relatively narrow compared to the cross-sectional width of the tantalum oxide ( ) layer, the oxygen vacancies generated in the tantalum oxide ( ) layer will only be confined in the hafnium oxide ( ) layer, restricting the generation position of the oxygen vacancy conductive filaments. A stable single filament is formed in the hafnium oxide ( ) layer, and the resistance value changes from a high resistance value to a low resistance value. When a reset operation is performed, a voltage is applied to the lower electrode (i.e., the first electrode layer) of the resistive random access memory to break the conductive filament, and the resistance value changes from a low resistance value to a high resistance value.

[0048] According to an embodiment of the present invention, an oxide resistive switching layer is formed by sequentially depositing a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width on a first electrode layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width, so that the prepared resistive switching memory can control the growth and breakage of conductive filaments in the resistive switching layer during the resistive switching process, so as to solve the technical problems in the prior art of poor performance uniformity and poor reliability of the resistive switching memory caused by the instability of the storage window during the resistive switching process due to the random growth and breakage of the conductive filaments in the resistive switching layer, thereby achieving the goal of controlling the growth and breakage of the conductive filaments in the resistive switching layer and improving the performance uniformity of the resistive switching memory and the reliability of the storage window during the resistive switching process.

[0049] Figure 3 The schematic diagram schematically shows a method for preparing a resistive random access memory according to an embodiment of the present invention.

[0050] like Figure 3 As shown, two layers of materials, namely, a first electrode layer 2 and a hafnium oxide layer 31, can be deposited on a semiconductor substrate 1 by physical vapor deposition, as shown in FIG. Figure 3 (a) Figure; a photoresist is coated on the hafnium oxide layer and a portion of the photoresist is etched to obtain a photoresist 4 with a first preset cross-sectional width, and a portion of the hafnium oxide layer 31 is exposed, such as Figure 3 (b) Figure; etching a portion of the hafnium oxide layer 31 until the portion of the hafnium oxide layer and the first electrode layer and the semiconductor substrate thereunder are etched away, such as Figure 3 (c) Figure; the first preset cross-sectional width of the photoresist 4 is removed to expose the first preset cross-sectional width of the hafnium oxide layer 31, such as Figure 3 In (d) Figure; on the hafnium oxide surface 31 and its surroundings using chemical vapor deposition growing insulating layer 5, such as Figure 3 and using chemical mechanical polishing to mechanically polish a portion of the insulating layer 5 until the hafnium oxide layer 31 is exposed, such as Figure 3 (f) Figure; using physical vapor deposition method on the surface of the hafnium oxide layer and the remaining insulating layer is deposited tantalum oxide layer 32 and the second electrode layer 6, such as Figure 3 and after the photoresist is coated on the second electrode layer, a portion of the photoresist is removed to form a second photoresist 7 of a preset width, exposing a portion of the second electrode layer 6, such as Figure 3 (h) Figure; the second electrode layer is etched to remove the photoresist to expose the portion until the insulating layer 5 is exposed, such as Figure 3 In the middle (i) figure; the photoresist with a second preset cross-sectional width is then removed to expose the second electrode layer 6. At this time, the second electrode layer 6 and the tantalum oxide layer 32 are both of the second preset cross-sectional width, and the hafnium oxide layer 31 and the tantalum oxide layer 32 form an oxide resistive switching layer 3. At this point, the resistive switching memory is prepared. Figure 3Figure (j).

[0051] FIG. 4(a) schematically shows a diagram of the operation voltage uniformity of a resistive random access memory according to an embodiment of the present invention.

[0052] As shown in FIG. 4(a), by performing set and reset operations on a plurality of resistive random access memories, it can be seen that the distributions of the set voltages and reset voltages of each resistive random access memory are very concentrated. From this, it can be seen that the resistive random access memory has good operation voltage uniformity.

[0053] FIG. 4(b) schematically shows a diagram of the device resistance uniformity of a resistive random access memory according to an embodiment of the present invention.

[0054] As shown in FIG. 4(b), after performing set operations on a plurality of resistive random access memories, the low resistance states (LRS) of each resistive random access memory are obtained. After performing reset operations on a plurality of resistive random access memories, the high resistance states (HRS) of each resistive random access memory are read to determine whether the set or reset is successful. It can be seen that the distributions of the low resistance states after the set operations of each resistive random access memory are very concentrated, and the distributions of the high resistance states after the reset operations are also very concentrated, that is, the resistance uniformity of the resistive random access memory after the operations is good.

[0055] FIG. 4(c) schematically shows a diagram of the durability of a resistive random access memory according to an embodiment of the present invention.

[0056] As shown in FIG. 4(c), by performing continuous multiple set / reset operations on a plurality of resistive random access memories, each set / reset is considered as one cycle operation. It can be seen that after the number of cycles reaches , the resistance values of the resistive random access memories after the cycle operations are still very stable, indicating that the conductive filaments in the resistive layer can grow and break along fixed paths.

[0057] According to an embodiment of the present invention, the present invention also provides a resistive random access memory prepared by the above preparation method. The resistive random access memory includes a first electrode layer; an oxide resistive layer is deposited on the surface of the first electrode layer. The oxide resistive layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width. The tantalum oxide layer is deposited on the surface of the hafnium oxide layer, and the hafnium oxide layer is deposited on the surface of the first electrode layer. The second preset cross-sectional width is greater than the first preset cross-sectional width; a second electrode layer is deposited on the surface of the tantalum oxide layer.

[0058] According to an embodiment of the present invention, in the resistive random access memory prepared by the above method, an oxide resistive switching layer formed by a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-section, and the second preset cross-sectional width is greater than the first preset cross-sectional width, so that the growth and breakage of conductive filaments in the resistive switching layer can be controlled during the resistive switching process of the prepared resistive random access memory, to solve the technical problems of poor performance uniformity and poor reliability of the resistive random access memory caused by the random growth and breakage of conductive filaments in the resistive switching layer in the prior art, thereby achieving the control of the growth and breakage of conductive filaments in the resistive switching layer and improving the performance uniformity of the resistive random access memory and the reliability of the storage window during the resistive switching process.

[0059] In the above specific embodiments, the object, technical solution and beneficial effects of the present invention have been further described in detail. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for preparing a resistive random access memory, comprising: forming a first electrode layer on a surface of a semiconductor substrate; Using a physical vapor deposition method, an oxide resistive switching layer with a preset cross-sectional width is formed on the surface of the first electrode layer, wherein the oxide resistive switching layer includes a hafnium oxide layer with a first preset cross-sectional width and a tantalum oxide layer with a second preset cross-sectional width, the tantalum oxide layer is grown on the surface of the hafnium oxide layer, and the second preset cross-sectional width is greater than the first preset cross-sectional width; A second electrode layer is formed on the surface of the tantalum oxide layer to obtain a resistive random access memory.

2. The method according to claim 1, wherein: The cross-sectional width of the hafnium oxide layer is 5-50 nm, and the cross-sectional width of the tantalum oxide layer is 100-500 nm.

3. The method according to claim 1, wherein: The step of forming a first electrode layer on the surface of the semiconductor substrate comprises: Preprocessing the semiconductor substrate to obtain a preprocessed semiconductor substrate; The physical vapor deposition method is used to deposit nitride on the pretreated semiconductor substrate to form a first electrode layer.

4. The method according to claim 3, wherein: The first electrode layer is a tantalum nitride layer, the thickness of the first electrode layer is 20-40 nm, and the cross-sectional width of the first electrode layer is 5-50 nm.

5. The method according to claim 1, wherein: The method of forming an oxide resistive switching layer on the surface of the first electrode layer by using a physical vapor deposition method includes: Depositing the hafnium oxide layer on the surface of the first electrode layer using the physical vapor deposition method; The tantalum oxide layer is formed on the surface of the hafnium oxide layer to obtain the oxide resistive switching layer.

6. The method according to claim 5, wherein: The thickness of the hafnium oxide layer is 3-15 nm, and the thickness of the tantalum oxide layer is 10-15 nm.

7. The method according to claim 6, wherein: The tantalum oxide layer is formed on the surface of the hafnium oxide layer to obtain the oxide resistive switching layer, comprising: After applying glue with the first preset cross-sectional width to the surface of the hafnium oxide layer, etching a portion of the hafnium oxide layer and a portion of the first electrode layer to retain the hafnium oxide layer and the first electrode layer with the first preset cross-sectional width; Performing a degumming treatment on the surface of the hafnium oxide layer of the first preset cross-sectional width, and depositing an insulating layer on the surface of the hafnium oxide layer, around the hafnium oxide layer and the first electrode layer by using a chemical vapor deposition method; A portion of the insulating layer is chemically mechanically polished to expose the hafnium oxide layer, and the tantalum oxide layer is deposited on the surface of the hafnium oxide layer and the remaining insulating layer using the physical vapor deposition method to form an oxide resistive switching layer.

8. The method according to claim 7, wherein: The step of forming a second electrode layer on the surface of the tantalum oxide layer to obtain a resistive random access memory comprises: Depositing the second electrode layer on the surface of the tantalum oxide layer; After applying glue with the second preset cross-sectional width on the surface of the second electrode layer, etching is performed from part of the second electrode layer surface to part of the tantalum oxide layer until the remaining insulating layer surface is exposed, retaining the second electrode layer with the second preset cross-sectional width to the tantalum oxide layer to form the resistive random access memory.

9. The method according to claim 1, wherein: The thickness of the second electrode layer is 20-40 nm, and the second electrode layer is a titanium nitride layer.

10. A resistive random access memory prepared by the method according to any one of claims 1 to 9.

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