Manufacturing method for power semiconductor device and power semiconductor device

Abstract

The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), the method comprising: forming a plurality of growth templates on a carrier substrate (2), the growth templates comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor material in each of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of the first type, in particular n + / p- / n- / n + structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor material in each of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n + / n- / p- / n + structures. The present disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to a novel method of integrating at least two different types of wide bandgap semiconductor structures into a single power semiconductor device. Background Art

[0002] Wide bandgap (WBG) semiconductor materials, such as silicon carbide (SiC), have advantageous properties, including high critical electric fields and electron mobility or high-frequency switching. Thus, they result in a much larger Baliga figure of merit (BFOM) compared to commonly used semiconductor materials, such as silicon, making them a good option for power semiconductor devices, such as power MISFETs. These advantages enable several applications for energy efficiency and power transportation. However, the relatively high cost and processing complexity involved in manufacturing power semiconductor devices including WBG materials limit their use in many fields. Summary of the Invention

[0003] Embodiments of the present disclosure relate to a method of manufacturing a power semiconductor device and a power semiconductor device, the method comprising the steps of forming a plurality of hollow growth templates on a carrier substrate and selectively growing first and second sequences of differently doped WBG semiconductor materials therein, and the power semiconductor device comprising a carrier substrate, a dielectric layer, and a plurality of first and second semiconductor structures formed therein.

[0004] According to a first aspect of the present disclosure, there is provided a method of manufacturing a power semiconductor device. The method comprises:

[0005] - forming a plurality of growth templates on a carrier substrate, the growth templates comprising at least a first plurality of hollow growth templates and a second plurality of hollow growth templates;

[0006] - selectively growing a first sequence of differently doped WBG semiconductor materials in each of the first plurality of hollow growth templates, thereby forming a plurality of first semiconductor structures of a corresponding first type, particularly an n+ / p- / n- / n+ structure; and

[0007] - selectively growing a second sequence of differently doped WBG semiconductor materials in each of the second plurality of hollow growth templates, thereby forming a plurality of second semiconductor structures of a corresponding second type, particularly an n+ / n- / p- / n+ structure.

[0008] The above processing steps enable the growth of multiple sets of different types of WBG semiconductor structures on a common carrier structure. This enables, on the one hand, the efficient production of multiple WBG semiconductor structures of the same type (e.g., for carrying high currents and / or high voltages within a branch of a circuit), and on the other hand, the implementation of different structures within a single integrated power device (e.g., for different branches of a circuit). For example, if separate first and second semiconductor structures are connected in parallel, they can carry a relatively high current. Additionally, if the multiple first semiconductor structures of a first type and the multiple second semiconductor structures of a second type are connected in sequence, they can form common circuit components such as the lower and upper halves of a half-bridge. Furthermore, by using WBG semiconductor materials selectively grown in a growth template, high critical electric fields and electron mobilities can be achieved, thereby improving, for example, energy efficiency and enabling high-frequency switching.

[0009] In at least one embodiment, regions of a vertically oriented growth template are formed, where each growth template in the vertically oriented growth template extends in a direction perpendicular to the main surface of the carrier substrate. This enables the fabrication of vertical power components (such as vertical MISFETs).

[0010] In at least one embodiment, the step of forming multiple hollow growth templates may include: depositing and structuring a sacrificial material, particularly amorphous silicon, on a carrier substrate; covering the structured sacrificial material with a dielectric material layer; and selectively removing the sacrificial material surrounded by the dielectric material to form the first and second multiple growth templates. This enables the use of conventional semiconductor processing steps to produce multiple very narrow vertical growth templates.

[0011] In at least one embodiment, the upper ends of the initially multiple growth templates are sealed, and the method further includes the steps of: only opening the upper ends of a first subset of the multiple growth templates before growing a first sequence of differently doped WBG semiconductor materials; resealing the upper ends of the first subset after growing the first sequence of differently doped WBG semiconductor materials; and only opening the upper ends of a second subset of the multiple growth templates before growing a second sequence of differently doped WBG semiconductor materials. In this way, at least multiple portions of the growth templates can be formed together, while different types of semiconductor structures can be grown at a later stage using conventional semiconductor processing equipment.

[0012] In at least one embodiment, the first and second sequences of differently doped WBG semiconductor materials are selectively grown by chemical vapor deposition (CVD) using different doping profiles, thereby allowing the use of conventional processing chambers and alleviating the need for later implantation of dopants into previously grown epitaxial layers.

[0013] In at least one embodiment, the method further comprises: forming a plurality of first gate structures that surround at least a portion of each of the plurality of first semiconductor structures; and / or forming a plurality of second gate structures that surround at least a portion of each of the plurality of second semiconductor structures. In this way, the first and / or second semiconductor structures can be switched, for example, for implementing a half-bridge of an inverter circuit. Furthermore, by completely surrounding the respective semiconductor structures, a particularly fast switching response can be achieved.

[0014] In at least one embodiment, the method further comprises: forming at least one dielectric layer, wherein a first gate contact is embedded in the at least one dielectric layer and a second gate contact is formed at or near an upper surface of the at least one dielectric layer. This enables, in particular, the respective gate contacts to be arranged close to the respective drift layers of the first and second semiconductor structures and vertically offset relative to each other.

[0015] In at least one embodiment, the method further comprises: forming a first top-side contact, in particular the positive DC terminal of a half-bridge structure, which is electrically connected at least to a subgroup of the plurality of first semiconductor structures; forming a second top-side contact, in particular the negative DC terminal of a half-bridge structure, which is electrically connected at least to a subgroup of the plurality of second semiconductor structures; and / or forming a bottom contact, in particular the AC terminal of a half-bridge structure, which is electrically connected at least to a subgroup of the plurality of first semiconductor structures and a subgroup of the plurality of second semiconductor structures. This connection arrangement respectively enables a partial or full parallel connection of the first and second semiconductor structures.

[0016] According to a second aspect of the present disclosure, there is provided a power semiconductor device. The device comprises:

[0017] - a carrier substrate that includes at least one bottom contact, in particular the AC terminal of a half-bridge structure;

[0018] - at least one dielectric layer that is formed on the carrier substrate;

[0019] - a plurality of first semiconductor structures of a first type, in particular n+ / p- / n- / n+ structures, which are formed within the at least one dielectric layer, each of the semiconductor structures of the first semiconductor structures being electrically connected to the bottom contact and including sub-layers of differently doped WBG semiconductor materials in a first sequence;

[0020] - a plurality of second semiconductor structures of a second type, in particular n+ / n- / p- / n+ structures, which are formed within the at least one dielectric layer, each of the second semiconductor structures being electrically connected to the bottom contact and including sub-layers of differently doped WBG semiconductor materials in a second sequence;

[0021] - A first top-side contact arranged on the upper surface of the at least one dielectric layer, in particular the positive DC terminal of a half-bridge structure, which is electrically connected to at least a subgroup of the plurality of first semiconductor structures; and

[0022] - A second top-side contact arranged on the upper surface of the at least one dielectric layer, in particular the negative DC terminal of a half-bridge structure, which is electrically connected to at least a subgroup of the plurality of second semiconductor structures.

[0023] The power semiconductor device according to the second embodiment is useful for monolithic integration of power semiconductor devices including a plurality of serially and / or parallely connected semiconductor structures made of WBG semiconductor material. It can be manufactured using the manufacturing method according to the first aspect and provides similar advantages and features as indicated above.

[0024] In at least one embodiment, the first and second semiconductor structures are selectively grown nanowire structures having a diameter of 10 nm to 10 μm and / or having a length of 1 μm to 100 μm. The at least one dielectric layer can have a thickness of 1 μm to 100 μm. Such semiconductor structures achieve a high power density and thus enable a space-efficient integration of the power semiconductor device. They are suitable for the voltages and currents occurring in typical power applications (such as inverters for electric vehicles and / or photovoltaic power generation).

[0025] In at least one embodiment, the carrier substrate includes a layer made of silicon or polycrystalline silicon carbide, the at least one dielectric layer includes a dioxide, in particular silicon dioxide, or includes alumina, and / or the WBG semiconductor material includes silicon carbide, in particular one of 4H-SiC, 6H-SiC or 3C-SiC. Among other things, the above device structure and corresponding processing steps enable the combination of active semiconductor structures made of WBG semiconductor material on a carrier substrate made of a relatively inexpensive semiconductor material (such as silicon or polycrystalline silicon carbide).

[0026] In at least one embodiment, the device includes a half-bridge circuit or a full-bridge circuit. Such circuits are often used in different power applications, such as inverters, rectifiers and converters.

[0027] Although the present disclosure provides multiple aspects, each feature described with respect to the first aspect is also disclosed herein with respect to the second aspect, and vice versa, even if the corresponding feature is not explicitly mentioned in the context of a particular aspect. Description of the Drawings

[0028] The accompanying drawings are included to provide a further understanding. In the drawings, elements having the same structure and / or function may be referred to by the same reference numerals. It will be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0029] Figure 1 is a schematic cross-section through a power semiconductor device that includes two different types of semiconductor structures.

[0030] Figure 2 Processing steps of a method for manufacturing a power semiconductor device are schematically shown.

[0031] Figures 3a to 3r Shows the various stages of manufacturing a power semiconductor device including a half-bridge circuit.

[0032] Figure 4a and Figure 4b show a perspective view of the power semiconductor device and a top-side contact of the power semiconductor device, respectively. Detailed Description

[0033] Figure 1 Shows a schematic cross-section through a power semiconductor device 1 according to the present disclosure.

[0034] Figure 1 The power semiconductor device 1 shown in includes a carrier substrate 2. The carrier substrate 2 may include, for example, multiple parts of a silicon wafer and / or one or more epitaxial growth layers (epilayer or epitaxial layer) or amorphous silicon carbide (SiC). As Figure 2 shown in, a bottom contact 3 is formed on the lower main surface of the carrier substrate 2. The bottom contact 3 may form a common terminal for all semiconductor structures formed on the carrier substrate 2.

[0035] On the opposite top surface of the carrier substrate 2, a dielectric layer 4 is formed. The dielectric layer 4 may be formed of an electrically insulating material such as a dioxide (e.g., silicon dioxide (SiO 2 )) or aluminum oxide (Al 2 O 3 ). Within the dielectric layer 4, a number of vertical semiconductor structures 5 and 6 are formed. In particular, in the Figure 1 embodiment shown in, a regular pattern of alternating first semiconductor structures 5 and second semiconductor structures 6 is formed.

[0036] The first semiconductor structure 5 and the second semiconductor structure 6 differ in their doping profiles and / or functionality. For example, as will be described in further detail below, the first semiconductor structure 5 may form a switching component of the lower branch of a half-bridge circuit, while the second semiconductor structure 6 may form a switching component of the upper branch of the same half-bridge circuit.

[0037] In Figure 1 the illustrated embodiment, a plurality of different top-side contacts 7 and 8 are formed on the upper surface of the dielectric layer 4 for connecting the first semiconductor structure 5 and the second semiconductor structure 6. In particular, several first top-side contacts 7 for connecting the first semiconductor structure 5 and several second top-side contacts 8 for connecting the second semiconductor structure 6 are formed. Note the fact that in Figure 1 the illustrated cross-section, only a single semiconductor structure 5 or 6 is shown connected to the respective top-side contacts 7 and 8. However, in practice, additional semiconductor structures of the same type may be present behind or in front of the row of semiconductor structures shown in Figure 1 the cross-section. In this case, the corresponding top-side contacts 7 and 8 will connect multiple or all of the first semiconductor structures 5 or second semiconductor structures 6 of the same type. Specifically, two different top-side contacts 7, 8 may form the positive and negative DC contacts of a half-bridge circuit, where the bottom contact 3 forms the AC contact.

[0038] Figure 2 A method for manufacturing a power semiconductor device (such as, Figure 1 the power semiconductor device 1) is schematically shown.

[0039] In a first step S1, a plurality of hollow growth templates are formed. This can be achieved, for example, by selectively etching the dielectric layer and / or depositing a sacrificial material, which is later covered with a dielectric material, as detailed below. As Figure 2 further indicated in, step S1 includes forming a first growth template in step S1a and forming a second growth template in step S1b. In practice, these two steps can be performed partially or fully simultaneously. However, in other embodiments, the first and second growth templates can be formed separately from each other.

[0040] In a second step S2, a first semiconductor structure is formed in the first hollow growth template formed in step S1a. For example, a first type of semiconductor structure, such as an n+ / p- / n- / n+ structure, can be formed by selective area epitaxy. This can be achieved in particular by selectively growing (i.e., depositing) differently doped WBG semiconductor material only inside the first hollow growth template, while growth in other regions covered by the material of the growth template is suppressed. The above notation for the layers iterates the respective sub-layers and the grown WBG semiconductor material in the order in which they are grown, i.e., from the substrate 2 upwards. That is, first the n+ material is deposited, followed by the p- material, the n- material, and finally the n+ material.

[0041] In a third step S3, a second semiconductor structure 6 is formed in the second hollow growth template formed in step S1b. The second semiconductor structure 6 will be different from the first semiconductor structure 5 grown in step S2 in terms of its physical setup, doping profile, and / or functionality. For example, they may have an inverted doping profile or sublayer sequence. For example, an n+ / n- / p- / n+ WBG semiconductor structure may be grown in the second hollow growth template.

[0042] It should be noted that although the formation of two sets of growth templates and the formation of two types of semiconductor structures have been described above, more than two types of hollow growth templates and more than two types of semiconductor structures can be formed in a similar manner.

[0043] Figure 2 The schematic diagrams focus on the formation of different first semiconductor structures 5 and second semiconductor structures 6 respectively. The formation of an actual power semiconductor device may include several additional processing steps, such as forming top and bottom contacts and gate electrodes. Such steps will be described in more detail below with respect to the fabrication of a half-bridge structure including multiple vertical MISFETs.

[0044] Figures 3a to 3r Illustrates the various stages of manufacturing a power semiconductor device including a half-bridge circuit.

[0045] In particular, Figure 3a Shows a cross-section through a carrier substrate 9 covered by an epitaxial layer 10. The growth substrate 9 and the epitaxial layer 10 formed on its top surface together form the carrier substrate 2.

[0046] In the described embodiment, the epitaxial layer 10 can be used as a growth seed for semiconductor structures selectively grown at a later stage. In this case, the epitaxial layer 10 filters out growth defects. In other embodiments, the epitaxial layer 10 itself can form part of the finished semiconductor device. For example, the epitaxial layer 10 can act as a drift layer. In still other embodiments, the epitaxial layer 10 can be completely omitted.

[0047] On the top surface of the carrier substrate 2, a sacrificial material (e.g., polysilicon) has been deposited to form a sacrificial layer 11.

[0048] Figure 3b Shows the situation after structuring the sacrificial layer 11. For example, using a corresponding photoresist pattern and conventional etching, several sacrificial, vertically oriented nanowires 12 can be formed by removing multiple portions of the sacrificial layer 11. The sacrificial nanowires 12 form a positive template for semiconductor structures to be formed later.

[0049] Figure 3cShows the situation after covering the sacrificial nanowire 12 with the first dielectric layer 13. For example, SiO can be deposited on all exposed surfaces of the carrier substrate 2 and the sacrificial nanowire 12 2 or Al 2 O 3 , to coat the remaining sacrificial material on all sides.

[0050] Figure 3d Shows the situation after applying the photoresist layer 14 for planarization. Initially, the photoresist layer 14 covers the entire first dielectric layer 13, such that the sacrificial nanowire 12 is buried in the photoresist material.

[0051] Figure 3e Shows the situation after removing the upper part of the photoresist layer 14 to partially expose the upper ends 17 of all the sacrificial nanowires 12. This can be achieved, for example, by dry etching, plasma etching, or other known semiconductor processing methods. Note the fact that the sacrificial nanowire 12 is still covered and sealed by the first dielectric layer 13.

[0052] Figure 3f Shows the situation after applying and structuring the second dielectric layer 15 to cover the upper ends of a subset of the nanowires 12. In particular, in the example shown in FIG. 3F, every other row of nanowires 12 is covered by the remaining material of the second dielectric layer 15 (such as, SiO 2 or Al 2 O 3 ). On the other hand, openings 16 are formed in the second dielectric layer 15 to expose the upper ends 17 of every other nanowire 12. In the described embodiment, the materials of the first dielectric layer 13 and the second dielectric layer 15 are different, and thus selective etching can be performed using appropriate formulations. Alternatively, the second dielectric layer 15 can be selectively deposited only in the regions corresponding to the covered subset of the nanowires 12.

[0053] Figure 3g Shows the situation after removing (e.g., by etching) the uppermost part of the first dielectric layer 13 to expose the sacrificial material at the upper ends 17 of the first subgroup of the sacrificial nanowires 12. Different etchants can be used in this step to selectively etch the material of the first dielectric layer 13. However, partial removal of the much thicker second dielectric layer 15 is also acceptable.

[0054] Figure 3h Shows the situation after removing (e.g., by etching) the sacrificial material of the first subgroup of the nanowires 17 to form a plurality of first hollow growth templates 18. For example, potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) can be used in a wet etching step to remove the exposed Si material, thereby forming the nanowires 17. Alternatively, XeF can be used for the Si material 2Gas-phase etching. The nanowires 17 formed of carbon (C) can be removed, for example, by O 2 plasma etching.

[0055] Figure 3i The situation after removing the remaining portions of the second dielectric layer 15 and the photoresist layer 14 is shown. It can be seen that the first, open, hollow growth templates 18 alternate with the remaining sacrificial nanowires 12, the upper ends 17 of which are still covered by the first dielectric layer 13, i.e., are enclosed. Thus, when a WBG semiconductor material is applied in the processing chamber, selective growth occurs only in the first hollow growth templates 18.

[0056] Figure 3j The situation after selectively growing a first sequence of differently doped WBG semiconductor materials in each of the first plurality of growth templates 18 to form the first semiconductor structure 5 is shown.

[0057] For example, to form a SiC AccuFET or a power MOSFET, 4H-SiC can be used due to the advantages in 4H-SiC growth technology and its attractive electronic properties (such as a larger bandgap and higher carrier mobility) over other available wafer-level SiC polytypes (such as 6H-SiC or 3C-SiC). However, this material can also be used for the selective growth of semiconductor structures. Note the fact that the crystalline material of the epitaxial layer 10 can act as a growth seed for the selectively grown WBG material, and the diameter of the hollow growth template 18 can be chosen small enough to implement a defect filter.

[0058] In the example provided, the entire semiconductor structure 5 can have a diameter in the range of 10 nm to 10 μm and a length of 1 μm to 100 μm (i.e., along the vertical or normal direction with respect to the top surface of the carrier substrate 2). Due to their small size, the semiconductor structures 5 are also referred to as nanowire structures in part in the present disclosure. The doping concentration and the diameter determine the resistance and current-carrying capacity of each nanowire, while its length determines its blocking voltage.

[0059] In the specific example shown, chemical vapor deposition (CVD) is used to successively deposit the first n+-doped WBG sublayer 19 of the power MOSFET, followed by the p-doped WBG sublayer 20, followed by the n-doped WBG sublayer 21, and followed by the n+-doped WBG sublayer 22. However, other types of semiconductor devices (such as, AccuFET) can be formed in a similar manner. In the finished device, the p-WBG sublayer 20 serves as the channel or depletion region, and the n-WBG sublayer 21 serves as the drift layer of the power MOSFET structure. Also note the fact that essentially the same type of semiconductor structure 5 grows in parallel in all open, first hollow growth templates 18, while no WBG material is deposited in the closed, still-filled sacrificial nanowires 12.

[0060] Figure 3k Shown is the situation after covering the entire top surface of the device being fabricated with a thin metal layer 23. This can be performed, for example, by atomic layer deposition (ALD) or other suitable processing methods. The material from the metal layer 23 will later be used to form the gate lines and gate spacers of the previously grown first semiconductor structure 5.

[0061] Figure 3l Shown is the situation after removing multiple portions of the metal layer 23 in the region of the remaining sacrificial nanowires 12. For example, for this purpose, a suitable combination of a photoresist mask and selective etching can be employed. As a result, the first gate line 24 is formed only in the region of the first growth template 18. The gate line 24 will later connect all the gate spacers of the first semiconductor structure 5, but is electrically isolated from the second semiconductor structure to be formed later.

[0062] Figure 3m Shown is the situation after performing gate metal etching to form the first gate structure in the form of the bottom gate spacer 26. The gate spacer 26 surrounds each of the first semiconductor structures 5 in a cylindrical manner. During this processing step, the metal material of the metal layer 23 is retained only in the vertical direction near the p-WBG sublayer 20, such that the gate spacer 26 can be used as a control gate that symmetrically surrounds the channel region of the finished MISFET structure on all sides.

[0063] Figure 3n Shown is the situation after depositing a third dielectric layer 27 on the top surface of the device being fabricated. The dielectric layer 27 covers both the first semiconductor structure 5 and the remaining sacrificial nanowires 12.

[0064] Figure 3oThis shows the situation after performing planarization on the device, exposing and opening the previously closed upper end portion 17, and removing the remaining sacrificial material for a second subset of the initially grown sacrificial nanowires 12. This can be performed in a manner similar to that Figures 3e to 3h explained above for the first subset of the sacrificial nanowires 12. For example, an additional photoresist mask can be applied and planarized in a subsequent lithography step. Alternatively, a spin-on glass (SOG) layer can be formed. A plurality of second openings 29 are formed in the third dielectric layer 27 to expose the upper end portions 17 of the sacrificial nanowires 17, after which the upper end portions 17 are opened and the remaining sacrificial material is removed to form a second hollow growth template 28. At the same time, the already fabricated first semiconductor structure 5 and the associated bottom gate spacer 26 are still covered by the remaining portion of the third dielectric layer 27.

[0065] Figure 3p This shows the situation after selectively growing a second type of second semiconductor structure 6 in the second hollow growth template 28, as previously Figure 3j explained. However, as Figure 3p shown in, the sequence of differently doped WBG semiconductor materials of the second semiconductor structure 6 is different. In the provided example, the sequence of the WBG sublayers 19 to 22 is reversed. That is, the n+WBG sublayer 22 is initially deposited, followed by the deposition of the n-WBG sublayer 21, the p-WBG sublayer 20, and finally the n+WBG sublayer 19.

[0066] In addition, as Figure 3p also shown in, after growing the second semiconductor structure 6, an additional metal layer is deposited in the opening 16 surrounding the second hollow growth template 28. The deposited metal material is etched to form a second gate line ( Figure 3p not visible in) and a corresponding second gate structure in the form of a top gate spacer 30 that surrounds the p-WBG sublayer 20 that forms the depletion layer of the resulting MISFET structure.

[0067] Figure 3q This shows the situation after depositing and planarizing an additional dielectric material to form a fourth dielectric layer 31. The thickness of the finished dielectric layer 31 roughly corresponds to the lengths of the first semiconductor structure 5 and the second semiconductor structure 6. Thus, at this stage, the upper end portions of the first semiconductor structure 4 and the second semiconductor structure 6 are exposed at the surface of the fourth dielectric layer 31.

[0068] Figure 3rThis shows the situation after forming metal contacts to electrically contact the respective ends of the grown semiconductor structures 5 and 6. In particular, alternating first top-side contacts 7 and second top-side contacts 8 are formed to contact the upper n+WBG sublayer 22 of the first semiconductor structure 5 and the upper n+WBG sublayer 19 of the second semiconductor structure 6, respectively. Additionally, at the bottom side of the substrate 9, a metal layer is deposited to form a common bottom contact 3 for all semiconductor structures 5 and 6.

[0069] Figure 4a A perspective view of a finished power semiconductor device 40 implementing a half-bridge circuit is shown, which may have been manufactured using the method explained above with respect to Figures 3a to 3r In the view of Figure 4a , some parts of the semiconductor device 40 have been removed to show the internal structure of the finished device.

[0070] As can be seen in Figure 4a , the semiconductor device 40 includes a two-dimensional array of nanostructures or nanowires formed of a WBG material. As can be seen in the partial cross-section in the front row as shown in Figure 4a , the internal structures of the nanostructures embedded in the dielectric layer 4 are different in terms of their respective doping profiles, as explained above. Thus, a first group of first semiconductor structures 5 of a first type and a second group of second semiconductor structures 6 of a second type are formed in the dielectric layer 4.

[0071] All first semiconductor structures 5 of the first type are connected in parallel using a positive DC (DC+) terminal 32 and an AC terminal 34. Correspondingly, all second semiconductor structures 6 of the second type are connected in parallel using a negative DC (DC-) terminal 33 and an AC terminal 34. It can be seen that the respective bottom gate spacers 26 and the top gate spacers 30 completely surround the respective semiconductor structures 5 and 6, respectively. Additionally, it can be seen that the individual bottom gate spacers 26 are connected in parallel by the metal material forming the first gate line 24, and the top gate spacers 30 are connected in parallel by the second gate line 25. Externally, the gate lines 24 and / or 25 are connected to one or more gate runners 35 or gate contacts arranged on the upper surface of the dielectric layer 4.

[0072] Figure 4b A top-side contact structure formed on the upper surface of the dielectric layer 4 is shown. The high-side gate contact 36 and the low-side gate contact 37 are connected to the buried first gate line 24 of the bottom gate spacer 26 and the second gate line 25 of the top gate spacer 30, respectively. Additionally, the positive busbar 38 is connected to all DC+ terminals 32 formed in every other row of the finished array. Correspondingly, the negative busbar 39 is connected to all DC- terminals 33 in the remaining rows of the array.

[0073] The semiconductor devices 1 and 40 and the corresponding manufacturing methods described above have several advantages over existing power semiconductor structures and manufacturing methods. Among other things, the favorable properties of WBG semiconductor materials (e.g., high critical electric field and electron mobility and / or the possibility of very high frequency switching) compared to commonly used silicon result in a much larger Baliga figure of merit (BFOM). This makes such materials a good choice for power switching applications and enables several applications for energy transfer and power transportation.

[0074] The specific manufacturing method detailed above allows for the cost-effective manufacture of highly integrated SiC power semiconductor devices. Among other things, neither implantation nor activation is required during the manufacture of semiconductor devices 1 and 40. In addition, it enables the use of relatively inexpensive substrates such as Si or polycrystalline SiC. The manufacturing method has a low thermal budget, allowing for the integration of advanced high-K gate dielectrics. Furthermore, the selective formation of two different sets of hollow growth masks 18 and 28 enables the integrated formation of a half-bridge or full-bridge in a single design.

[0075] Together, this concept of an integrated SiC half-bridge device allows SiC technology to enter lower voltage classes, e.g., voltage classes below 1.2 kV.

[0076] In the Figure 1 to Figure 4B, the illustrated embodiments represent exemplary embodiments of improved power semiconductor devices 1 and 40 and their manufacturing methods. Thus, they do not constitute a complete list of all embodiments of the improved devices and manufacturing methods. For example, actual devices and manufacturing methods may differ from the illustrated embodiments in terms of the materials used, specific processing steps, and circuit configurations.

[0077] Reference numerals

[0078] 1 Power semiconductor device

[0079] 2 Carrier substrate

[0080] 3 Bottom contact

[0081] 4 Dielectric layer

[0082] 5 (First) semiconductor structure

[0083] 6 (Second) semiconductor structure

[0084] 7 (First) top contact

[0085] 8 (Second) top contact

[0086] 9 Substrate

[0087] 10 Epitaxial layer

[0088] 11 Sacrificial layer

[0089] 12 Sacrificial nanowire

[0090] 13 (First) dielectric layer

[0091] 14 Photoresist layer

[0092] 15 (Second) dielectric layer

[0093] 16 Opening

[0094] 17 Upper end portion

[0095] 18 (First) hollow growth template

[0096] 19 n+ WBG sublayer

[0097] 20 p-WBG sublayer

[0098] 21 n-WBG sublayer

[0099] 22 n+ WBG sublayer

[0100] 23 Metal layer

[0101] 24 (First) gate line

[0102] 25 (Second) gate line

[0103] 26 (Bottom) gate spacer

[0104] 27 (Third) dielectric layer

[0105] 28 (Second) hollow growth template

[0106] 29 (Second) opening

[0107] 30 (Top) gate spacer

[0108] 31 (Fourth) dielectric layer

[0109] 32 DC+ terminal

[0110] 33 DC- terminal

[0111] 34 AC terminal

[0112] 35 Gate runner

[0113] 36 (High-side) gate contact

[0114] 37 (Low-side) gate contact

[0115] 38 Positive bus bar

[0116] 39 Negative bus bar

[0117] 40 Power semiconductor device (with a half-bridge circuit)

Claims

1. A method for manufacturing a power semiconductor device (1, 40), the method comprising: - forming (S1) a plurality of growth templates on a carrier substrate (2), the growth templates comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); - selectively growing (S2) a first sequence of differently doped wide bandgap (WBG) semiconductor materials in each of the first hollow growth templates (18) to thereby form a plurality of first semiconductor structures (5) of a corresponding first type, in particular n+ / p- / n- / n+ structures; and - selectively growing (S3) a second sequence of differently doped WBG semiconductor materials in each of the second hollow growth templates (28) to thereby form a plurality of second semiconductor structures (6) of a corresponding second type, in particular n+ / n- / p- / n+ structures.

2. The method according to claim 1, wherein, in the step of forming (S1) the plurality of growth templates (18, 28), an array of vertically oriented growth templates is formed, wherein each of the vertically oriented growth templates extends in a direction perpendicular to the main surface of the carrier substrate (2).

3. The method according to claim 1 or 2, wherein, the step of forming (S1) the plurality of growth templates (18, 28) comprises: - depositing and structuring a sacrificial material, in particular amorphous silicon, on the carrier substrate (2); - covering the structured sacrificial material with a dielectric material layer (13); and - selectively removing the sacrificial material surrounded by the dielectric material to form the first and second pluralities of hollow growth templates (18, 28).

4. The method according to any one of claims 1 to 3, wherein, initially the upper ends (17) of the plurality of growth templates are sealed, and the method further comprises: - opening only the upper ends (17) of a first subset of the plurality of growth templates before growing the first sequence of differently doped WBG semiconductor materials; - resealing the upper ends (17) of the first subset after growing the first sequence of differently doped WBG semiconductor materials; and - opening only the upper ends (17) of a second subset of the plurality of growth templates before growing the second sequence of differently doped WBG semiconductor materials.

5. The method according to any one of claims 1 to 4, wherein, the first and second sequences of differently doped WBG semiconductor materials are selectively grown by chemical vapor deposition (CVD) using different doping profiles.

6. The method according to any one of claims 1 to 5, wherein, the first hollow growth template (18) and / or the second hollow growth template (28) extends into the crystalline material of the carrier substrate (2), and in the step of selectively growing (S2, S3), the crystalline material serves as a seed region for the WBG semiconductor material.

7. The method according to any one of claims 1 to 6, further comprising: - Forming a plurality of first gate structures that surround at least a portion of each of the plurality of first semiconductor structures (5); and / or - Forming a plurality of second gate structures that surround at least a portion of each of the plurality of second semiconductor structures (6).

8. The method according to claim 7, further comprising: - Forming at least one dielectric layer (4, 27, 31), wherein - The first gate structures are buried in the at least one dielectric layer (4, 27, 31); and - The second gate structures are formed on the upper surface of the at least one dielectric layer (4, 27, 31) or formed near the at least one dielectric layer (4, 27, 31).

9. The method according to any one of claims 1 to 8, further comprising: - Forming a first top-side contact (7), in particular a positive DC terminal (32) of a half-bridge structure, the first top-side contact being electrically connected at least to a subgroup of the plurality of first semiconductor structures (5); - Forming a second top-side contact (8), in particular a negative DC terminal (33) of a half-bridge structure, the second top-side contact being electrically connected at least to a subgroup of the plurality of second semiconductor structures (6); and / or - Forming a bottom contact (3), in particular an AC terminal (34) of a half-bridge structure, the bottom contact being electrically connected at least to a subgroup of the plurality of first semiconductor structures (5) and a subgroup of the plurality of second semiconductor structures (6).

10. A power semiconductor device (1, 40), comprising: - A carrier substrate (2) including at least one bottom contact (3), in particular an AC terminal (34) of a half-bridge structure; - At least one dielectric layer (4, 27, 31) formed on the carrier substrate (2); - A plurality of first semiconductor structures (5) of a first type, in particular an n+ / p- / n- / n+ structure, the plurality of first semiconductor structures of the first type being formed within the at least one dielectric layer (4, 27, 31), each of the first semiconductor structures (5) being electrically connected to the bottom contact (3) and including sub-layers (19, 20, 21, 22) of differently doped wide-bandgap WBG semiconductor material in a first sequence; - A plurality of second semiconductor structures (6) of a second type, in particular an n+ / n- / p- / n+ structure, the plurality of second semiconductor structures of the second type being formed within the at least one dielectric layer (4, 27, 31), each of the second semiconductor structures (6) being electrically connected to the bottom contact (3) and including sub-layers (22, 21, 20, 19) of the WBG semiconductor material in a second sequence; - A first top-side contact (7) disposed on the upper surface of the at least one dielectric layer (4, 27, 31), in particular a positive DC terminal (32) of a half-bridge structure, the first top-side contact (7) being electrically connected at least to a subgroup of the plurality of first semiconductor structures (5); and - A second top-side contact (8), in particular the negative DC terminal (33) of a half-bridge structure, disposed on the upper surface of the at least one dielectric layer (4, 27, 31), the second top-side contact (8) being electrically connected to at least a subgroup of the plurality of second semiconductor structures (6).

11. The device (1, 40) according to claim 10, wherein: - The at least one dielectric layer (4, 27, 31) includes an array of vertically oriented growth templates (18, 28), the vertically oriented growth templates extending in a direction perpendicular to the main surface of the carrier substrate (2); - The first semiconductor structure (5) is a nanowire structure selectively grown in a first subset of the array of vertically oriented growth templates (18); and - The second semiconductor structure (6) is a nanowire structure selectively grown in a second subset of the array of vertically oriented growth templates (28).

12. The device (1, 40) according to claim 11, wherein, - The nanowire structure has a diameter of 10 nm to 10 μm; - The nanowire structure has a length of 1 μm to 100 μm; and / or - The at least one dielectric layer (4, 31) has a thickness of 1 μm to 100 μm.

13. The device (1, 40) according to any one of claims 10 to 12, wherein, - The carrier substrate (2) includes a layer made of silicon Si and / or polycrystalline silicon carbide poly-SiC; - The at least one dielectric layer (4, 27, 31) includes a dioxide, in particular silicon dioxide SiO2, or includes aluminum oxide Al2O3; and / or - The WBG semiconductor material includes one of silicon carbide SiC, in particular 4H-SiC, 6H-SiC or 3C-SiC.

14. The device (1, 40) according to any one of claims 10 to 13, further comprising: - A plurality of buried first gate structures, disposed within the at least one dielectric layer (4, 27, 31) and surrounding a first depletion layer of a corresponding one of the first semiconductor structures (5) to form a first metal-insulator-semiconductor field-effect transistor MISFET, in particular a first MOSFET or AccuFET; and / or - A plurality of second gate structures, disposed at the upper surface of the at least one dielectric layer (4, 27, 31) or disposed near the at least one dielectric layer (4, 27, 31) and surrounding a second depletion layer of a corresponding one of the second semiconductor structures (6) to form a second MISFET, in particular a second MOSFET or AccuFET.

15. The device (1, 40) according to claim 14, comprising: - A half - bridge circuit, wherein the buried first gate structure is connected in parallel to a first gate contact (36) to selectively switch a first branch of the half - bridge circuit, in particular the high - side of the half - bridge circuit, and the second gate structure is connected in parallel to a second gate contact (37) to selectively switch a second branch of the half - bridge circuit, in particular the low - side of the half - bridge circuit; or - A full - bridge circuit, wherein the buried gate structures corresponding to a first subset of the first semiconductor structure (5) are connected in parallel to a first gate contact to selectively switch a first branch of the full - bridge circuit, the buried gate structures corresponding to a second subset of the first semiconductor structure (5) are connected in parallel to a second gate contact to selectively switch a second branch of the full - bridge circuit, the second gate structures corresponding to a first subset of the second semiconductor structure (6) are connected in parallel to a third gate contact to selectively switch a third branch of the full - bridge circuit, and the additional gate structures corresponding to a second subset of the second semiconductor structure (6) are connected in parallel to a fourth gate contact to selectively switch a fourth branch of the full - bridge circuit.

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