Low-temperature co-flow epitaxial deposition process

Abstract

The present disclosure provides a method for selectively depositing an epitaxial layer. In some embodiments, a selective epitaxial deposition process includes providing a co-flow of a chlorosilane precursor with at least one of an antimony-containing precursor and a phosphorus-containing precursor. The method utilizes co-flow of multiple chlorosilane precursors to enable silicon to be combined with at least one of phosphorus and antimony in the same matrix using a low temperature selective process. Epitaxial layers deposited using the described epitaxial deposition techniques contain not only phosphorus and / or antimony but also highly active phosphorus and / or antimony concentrations.

Description

Technical Field

[0001] Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, the present disclosure relates to the selective deposition of epitaxial silicon films. Background Art

[0002] Typical selective epitaxy processes involve deposition and etching reactions. The deposition reaction causes an epitaxial layer to form on the single-crystal surface of a substrate, while polycrystalline and / or amorphous layers form on non-single-crystal surfaces, e.g., a patterned dielectric layer deposited on top of the substrate. The etching reaction removes the epitaxial layer and the polycrystalline and / or amorphous layers at different rates, providing a net selective process that can result in the deposition of epitaxial material and limited or no deposition of polycrystalline material.

[0003] As device critical dimensions continue to shrink, selective epitaxial deposition methods (such as the illustrative method above) involve lower processing temperatures (e.g., about 600 degrees Celsius or lower). Unfortunately, at such temperatures, typical etching gases do not provide a suitable selectivity window between the epitaxial layer and the polycrystalline and / or amorphous layers. Additionally, current cyclic deposition / etch processes are complex processes that are difficult to maintain and have low yields.

[0004] For the above reasons, there is a need for selective epitaxy processes that can be performed at lower temperatures. Summary of the Invention

[0005] Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, the present disclosure relates to the selective deposition of epitaxial silicon films.

[0006] In at least one aspect, a method of forming a semiconductor component is provided. The method includes forming a multi-material layer on a substrate located in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming source and drain regions on the crystalline first layers of the substrate. The formed source and drain regions have an n-type dopant precursor concentration greater than about 1x10 21 atoms / cm 3 . Forming the source and drain regions further includes flowing a first chlorosilane precursor gas selected from dichlorosilane and trichlorosilane; co-flowing a higher-order chlorosilane precursor gas having the formula Cl y Si x H (2X+2-y) , where y is 3 or more and x is one or more and the higher-order chlorosilane precursor gas is different from the first chlorosilane precursor gas; co-flowing an n-type dopant precursor gas with the first chlorosilane precursor gas and the higher-order chlorosilane precursor gas; and heating the substrate to a temperature of about 550 °C or lower.

[0007] The embodiments may include one or more of the following. This higher-order chlorosilane precursor gas contains trichlorosilane (Cl 3 SiH), hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), pentachlorodisilane (Cl 5 Si 2 H), octachlorotrisilane (Cl 8 Si 3 ) or a combination of the above items. The flow rate of this higher-order chlorosilane precursor gas is 3:1 or greater than the flow rate of this first chlorosilane precursor gas. The flow rate of this higher-order chlorosilane precursor gas is 10:1 or greater than the flow rate of this first chlorosilane precursor gas. Forming the source region and the drain region further includes maintaining the temperature in the processing region within a range of about 450 degrees Celsius to about 500 degrees Celsius, and maintaining the pressure in the processing region within a range of about 10 Torr to about 600 Torr. This n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination of the above. This n-type dopant precursor is an antimony-containing precursor, and the concentration of this n-type dopant precursor is the antimony concentration in the source region and the drain region, and this antimony concentration is greater than about 2×10 21 atoms / cm 3 . This antimony-containing precursor is one or a combination of stibine, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, stibine trihydride, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony. The growth rate of the source region and the drain region on these crystalline first layers is greater than about 50 times the growth rate on these amorphous second layers. These amorphous second layers further include dielectric spacers disposed on their outsides. During the selective formation of the source region and the drain region, a plurality of gaps are formed adjacent to these amorphous second layers. The method further includes flowing this first chlorosilane precursor at a flow rate in the range of about 100 to about 1000 sccm; flowing this higher-order chlorosilane at a flow rate in the range of about 1000 to about 10000 sccm; and flowing this n-type dopant precursor at a flow rate in the range of about 300 to about 1000 sccm. The method further includes flowing hydrogen at a flow rate in the range of about 1 to about 40 SLM.

[0008] In another aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate located in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming a source region and a drain region on the crystalline first layers of the substrate. The formed source region and drain region contain greater than about 2×10 21 Atom / cm 3 The forming of the source region and the drain region further includes flowing dichlorosilane; co-flowing trichlorosilane; co-flowing a phosphorus-containing precursor gas with the dichlorosilane and the trichlorosilane; and heating the substrate to a temperature of about 550° C. or less, wherein the ratio of the flow rates of TCS to DCS is in a range of about 3:1 to about 7:1.

[0009] Embodiments may include one or more of the following. The phosphorus-containing precursor gas is selected from phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tri-tert-butylphosphine, or a combination thereof. The method further includes flowing dichlorosilane at a flow rate in a range of about 700 sccm to about 1000 sccm; flowing trichlorosilane at a flow rate in a range of about 2000 sccm to about 7000 sccm; and flowing phosphine at a flow rate in a range of about 0.1 sccm to 300 sccm. The method further includes flowing an antimony-containing precursor gas at a flow rate in a range of about 10 sccm to about 100 sccm.

[0010] In another aspect, a method of forming a semiconductor device is provided. The method includes forming a multi-material layer on a substrate located in a processing region. The multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern. The method further includes selectively forming a source region and a drain region on the crystalline first layers of the substrate. The formed source region and drain region contain greater than about 1×10 21 Atom / cm 3 The forming of the source region and the drain region further includes flowing pentachlorodisilane; co-flowing trichlorosilane; co-flowing an antimony-containing precursor gas with pentachlorodisilane and trichlorosilane; and heating the substrate to a temperature of about 550° C. or less, wherein the ratio of the flow rate of trichlorosilane to pentachlorodisilane is in a range of about 9:1 to about 16:1.

[0011] The embodiments may include one or more of the following. The antimony-containing precursor gas is selected from stibine, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, stibine, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony. The method further includes flowing pentachlorodisilane at a flow rate in the range of about 100 sccm to about 1000 sccm; flowing trichlorosilane at a flow rate in the range of about 7000 sccm to about 10000 sccm; and flowing the antimony-containing precursor at a flow rate in the range of about 0.1 sccm to 100 sccm.

[0012] In another aspect, instructions are stored on a non-transitory computer-readable medium that, when executed by a processor, cause the program to perform the operations of the above-described apparatus and / or method. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To enable a detailed understanding of the above-described features of the present disclosure, the present disclosure briefly summarized above may be described in more detail by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope, since the present disclosure may admit other equally effective embodiments.

[0014] Figure 1 A flowchart showing a method of forming an epitaxial layer according to one or more aspects of the present disclosure.

[0015] Figure 2 A schematic isometric view showing a horizontal gate all-around structure according to one or more aspects of the present disclosure.

[0016] Figures 3A to 3C Shows according to one or more aspects of the present disclosure Figure 2 A schematic cross-sectional view of the hGAA structure of.

[0017] Figure 4 A flowchart showing another method of forming an epitaxial layer according to one or more aspects of the present disclosure.

[0018] For ease of understanding, whenever possible, the same reference numerals are used to denote the same common elements in the drawings. It is contemplated that the elements and features of one embodiment may be advantageously combined in other embodiments without further elaboration. DETAILED DESCRIPTION

[0019] Aspects of the present disclosure generally relate to the field of semiconductor devices and methods for manufacturing semiconductor devices. More specifically, the present disclosure relates to the selective deposition of epitaxial silicon films. A method is provided for epitaxial deposition of n-channel metal oxide semiconductor (NMOS) source / drain regions formed in a device, such as within a horizontal gate all around (hGAA) device structure. The method is performed at a temperature of 550 degrees Celsius or lower. The method includes using a chlorosilane precursor, a higher-order chlorosilane precursor, and an n-type dopant precursor selected from an antimony-containing precursor, a phosphorus-containing precursor, an arsenic-containing precursor, or a combination of the foregoing.

[0020] Current epitaxial deposition processes have difficulty achieving co-flow selective Si:P or Si:Sb epitaxial deposition at low temperatures (e.g., 550 degrees Celsius or lower) because HCl is not active at these low temperatures. As a result, current epitaxial deposition processes are performed using a cyclic deposition / etch process, which is complex and time-consuming, resulting in yield issues. Aspects of the present disclosure provide a selective epitaxial deposition process that provides co-flow of a chlorosilane precursor with at least one of an antimony-containing precursor and a phosphorus-containing precursor. Aspects of the present disclosure utilize co-flow of multiple chlorosilane precursors to enable the combination of silicon with at least one of phosphorus and antimony in the same matrix using a low-temperature selective process. The epitaxial layer deposited using the described epitaxial deposition technique not only contains phosphorus and / or antimony, but also has a high active phosphorus and / or antimony concentration.

[0021] The combination of chlorosilane precursors of the present disclosure is used to continuously etch the epitaxial layer during epitaxial layer formation and to improve the selectivity of the epitaxial layer when deposited onto a device (e.g., a superlattice structure). The epitaxial layer is formed only on the crystalline portions of the superlattice structure and not on oxide or amorphous surfaces. The antimony-containing precursor reduces the temperature at which the epitaxial layer is deposited and increases the growth rate of the epitaxial layer on the crystalline portions of the superlattice structure. The phosphorus-containing precursor dopes the epitaxial layer with phosphorus and enables better adhesion to the crystalline portions of the superlattice structure.

[0022] It has also been shown that the growth rate of the epitaxial layer relative to the exposed crystalline surface of the superlattice structure varies with the addition of different concentrations of antimony in the epitaxial layer. In some aspects described, the concentration of antimony in the epitaxial layer is greater than about 1.0×10 21 atoms / cm 3 and the growth is primarily in the <110> direction. The antimony concentration has been shown to cause primary crystalline growth in the <110> direction. The crystalline growth primarily in the <110> direction reduces the mirror surface of the epitaxial layer on the superlattice structure.

[0023] Figure 1 FIG. 100 is a flow chart of a method for forming an epitaxial layer in accordance with one or more aspects of the present disclosure. At operation 110, a substrate (e.g., substrate 202) is positioned within a processing chamber. The processing chamber can be an RP Epi chamber available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other chambers, including chambers available from other manufacturers, can be used to practice aspects of the present disclosure.

[0024] The term "substrate" is intended to broadly encompass any article or material having a surface on which a layer of material can be deposited. The substrate can include a bulk material such as silicon (e.g., single crystal silicon that can include dopants), or can include one or more layers overlying the bulk material. The substrate can be a planar substrate or a patterned substrate. A patterned substrate is a substrate that can include electronic features formed in or on a processing surface of the substrate. The substrate can include a single crystal surface and / or a non-single crystal secondary surface, such as a polycrystalline or amorphous surface. The single crystal surface can include a bare crystalline substrate or a deposited single crystal layer, typically made of a material such as silicon, germanium, silicon germanium, or silicon carbide. The polycrystalline or amorphous surface can include a dielectric material such as an oxide or nitride, particularly silicon oxide or silicon nitride, and an amorphous silicon surface. The substrate can have various dimensions, such as 200 mm, 300 mm, 450 mm, or other diameters, and can also be a rectangular or square panel. Unless otherwise specified, the examples are performed on substrates having a 200 mm diameter, 300 mm diameter, or 450 mm diameter.

[0025] In at least one aspect, the substrate includes a first surface and a second surface different from the first surface. At least one of the first surface and the second surface is single crystal, while the other surface is non-single crystal. Positioning the substrate within the processing chamber can include adjusting one or more reactor conditions, such as temperature, pressure, and / or carrier gas (e.g., Ar, N 2 , H 2 or He) flow rate, to conditions suitable for epitaxial film formation.

[0026] In operation 120, the substrate is heated to a temperature of 550 degrees Celsius or lower. In at least one aspect, the temperature in the processing chamber can be adjusted such that the reaction zone formed at or near the exposed surface of the substrate, or the surface of the substrate itself, is about 550 degrees Celsius or lower, or 500 degrees Celsius or lower, or 450 degrees Celsius or lower. In one example, the substrate is heated to a temperature in the range of about 400 degrees Celsius to about 550 degrees Celsius, or in the range of about 450 degrees Celsius to about 550 degrees Celsius, or in the range of about 450 degrees Celsius to about 500 degrees Celsius, or in the range of about 400 degrees Celsius to about 500 degrees Celsius. Without being bound by theory, but in some embodiments of forming Si:P, depositing Si:P at a temperature below 450 degrees Celsius has a very slow growth rate, and depositing at a temperature above 550 degrees Celsius may affect the thermal budget of other materials formed on the substrate. The thermal budget of the final device can be minimized by heating the substrate to the lowest temperature sufficient to thermally decompose the process reagents and epitaxially deposit a layer on the substrate. The pressure in the processing chamber can be adjusted such that the reaction zone pressure is in the range of about 1 to about 760 Torr, or in the range of about 1 Torr to about 600 Torr, or in the range of about 100 Torr to about 300 Torr, or in the range of about 200 Torr to about 300 Torr. In some embodiments, a carrier gas (e.g., nitrogen) can flow into the processing chamber at a flow rate of about 1 to 40 SLM (standard liters per minute). Nitrogen remains inert during the low-temperature deposition process. Thus, nitrogen is not incorporated into the deposited layer during the low-temperature process. Additionally, a nitrogen carrier gas does not form a hydrogen-terminated surface like a hydrogen carrier gas. However, it should be understood that in some embodiments, a different carrier gas / diluent gas can be employed, e.g., an inert carrier gas such as argon or helium, different flow rates can be used, or such a gas can be omitted.

[0027] In operation 130, a first chlorosilane precursor gas is introduced into the processing chamber. The first chlorosilane precursor gas includes a precursor having both silicon and chlorine. In at least one embodiment, the first chlorosilane gas includes dichlorosilane (SiCl 2 H 2 )(DCS), trichlorosilane (SiCl 3(H)(TCS) or a combination of the above items. In one example, when using dichlorosilane, the dichlorosilane flows into the processing chamber at a flow rate in the range of about 100 sccm to about 1000 sccm, or in the range of about 700 sccm to about 1000 sccm, or in the range of about 800 sccm to 950 sccm, or in the range of about 850 sccm to 900 sccm. In another example, when using trichlorosilane, the trichlorosilane flows into the processing chamber at a flow rate in the range of about 1000 sccm to about 10000 sccm, or in the range of about 7000 sccm to about 10000 sccm, or in the range of about 7500 sccm to about 9000 sccm, or in the range of about 8000 sccm to about 8500 sccm.

[0028] At operation 140, a second chlorosilane precursor gas is introduced into the processing chamber. The second chlorosilane precursor gas is different from the first chlorosilane precursor gas. In at least one embodiment, the second chlorosilane precursor gas is a higher-order chlorosilane gas. The higher-order chlorosilane gas may have the formula Cl y Si x H (2x+2-y) , where y is 3 or more, or 5 or more, and x is 1 or more, or 2 or more, or 3 or more. In one example, y is from 5 to 8, and x is from 2 to 3. In at least one embodiment, the second chlorosilane precursor gas comprises trichlorosilane, hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), pentachlorodisilane (Cl 5 Si 2 H), octachlorotrisilane (Cl 8 Si 3 ), or a combination of the above items, consisting of, or consisting essentially of. In another embodiment, the second chlorosilane gas comprises pentachlorodisilane (Cl 5 Si 2 H), hexachlorodisilane (Si 2 Cl 6 ), octachlorotrisilane (Cl 8 Si 3) or a combination of the above items, consisting of, or consisting essentially of. In one example, in the case of using pentachlorodisilane (PCDS), pentachlorodisilane is caused to flow into the processing chamber at a flow rate in the range of about 100 sccm to about 1000 sccm, or in the range of about 300 sccm to about 600 sccm, or in the range of about 400 sccm to about 550 sccm, or in the range of about 450 sccm to about 500 sccm. In another example, in the case of using trichlorosilane, trichlorosilane is flowed into the processing chamber at a flow rate in the range of about 1000 sccm to about 10000 sccm, or in the range of about 7000 sccm to about 10000 sccm, or in the range of about 7500 sccm to about 9000 sccm, or in the range of about 8000 sccm to about 8500 sccm.

[0029] At operation 150, an n-type dopant precursor is introduced into the processing chamber. In at least one aspect, the n-type dopant precursor comprises, consists of, or consists essentially of a phosphorus-containing precursor, an antimony precursor, an arsenic-containing precursor, or a combination thereof. In at least one embodiment, the antimony-containing precursor comprises one or a combination of antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenyl antimony, antimony trihydride, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethyl antimony, and trimethyl antimony. In at least one specific embodiment, triethyl antimony is used. The flow rate of the antimony-containing precursor may be in the range of about 0.1 sccm to 300 sccm, or in the range of about 10 sccm to about 100 sccm. In at least one embodiment, the phosphorus-containing precursor comprises a combination of one or more of phosphine and alkyl phosphines. Suitable alkyl phosphines include trimethyl phosphine ((CH 3 ) 3 P), dimethylphosphine ((CH 3 ) 2 PH), triethylphosphine ((CH 3 CH 2 ) 3 P), tri-tert-butylphosphine and diethylphosphine ((CH 3 CH 2 ) 2 PH). In at least one specific embodiment, phosphine is used. The flow rate of the phosphorus-containing precursor may be in the range of about 0.1 sccm to 1000 sccm, 0.1 sccm to 300 sccm, or in the range of about 100 sccm to about 300 sccm, or in the range of about 300 sccm to about 1000 sccm. In at least one embodiment, the arsenic-containing precursor includes arsine (AsH 3 ), halogenated arsenic compounds, trimethylarsenic and silylarsine [(H 3 Si)3-x AsR x (where x = 0, 1, 2, and R x is hydrogen or deuterium) or a combination of one or more of the above items. The flow rate of the arsenic-containing precursor can be in the range of about 0.1 sccm to 1000 sccm, 0.1 sccm to 300 sccm, or in the range of about 100 sccm to about 300 sccm, or in the range of about 300 sccm to about 1000 sccm.

[0030] It is contemplated that operations 130, 140, and 150 can be performed simultaneously, substantially simultaneously, or in any desired order. In at least one aspect, each of the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorus-containing precursor flows into the processing chamber simultaneously. Without being bound by theory, it is believed that co-flowing each of the first chlorosilane precursor gas, the second chlorosilane precursor gas, the antimony-containing precursor, and the phosphorus-containing precursor improves the conductivity of the antimony-doped source / drain regions and enables a deposition temperature below 550 degrees Celsius. In one embodiment, at least two of the precursor gases are mixed before being delivered to the processing region. In another embodiment, at least two of the precursor gases are delivered separately to the processing region and mixed within the processing region.

[0031] In at least one embodiment, the flow rate of the second chlorosilane precursor gas is 3:1 or greater than the flow rate of the first chlorosilane precursor gas, for example, in the range of about 3:1 to about 7:1. In one example, the flow rate of the second chlorosilane precursor gas is 10:1 or greater than the flow rate of the first chlorosilane precursor gas. In another aspect, the flow rate of the first chlorosilane precursor gas is 7:1 or greater than the flow rate of the second chlorosilane precursor gas, for example, in the range of about 7:1 to about 20:1, or in the range of about 9:1 to about 16:1. In one example, the flow rate of the first chlorosilane precursor gas is 10:1 or greater than the flow rate of the second chlorosilane precursor gas.

[0032] In one aspect, the first chlorosilane precursor gas is dichlorosilane, the second chlorosilane precursor gas is trichlorosilane, and the n-type dopant gas is phosphine. The mixture of DCS and TCS includes a mixture of TCS and DCS having a flow rate ratio of 2:1 or greater (e.g., in the range of about 3:1 to about 7:1). In some embodiments, it has been shown that TCS grows a phosphorous-doped epitaxial layer only when DCS is present and no phosphorous-doped epitaxial layer is formed, or forms a phosphorous-doped epitaxial layer at a significantly reduced rate when not co-flowing with DCS. DCS has been shown to increase the growth rate of the phosphorous-doped source / drain regions. The chlorosilane precursors enable the growth of a phosphorous-doped epitaxial layer. As the phosphorous-doped epitaxial layer grows, an etch-back operation is not performed. Chlorine in the chlorosilane precursor gas has been shown to improve the crystalline growth of the epitaxial layer without an additional etch-back process. In one example, dichlorosilane is introduced into the processing chamber at a flow rate in the range of about 700 sccm to about 1000 sccm, or in the range of about 800 sccm to about 950 sccm, or in the range of about 850 sccm to about 900 sccm. Trichlorosilane is introduced into the processing chamber at a flow rate in the range of about 1000 sccm to about 10000 sccm, or in the range of about 2000 sccm to about 7000 sccm, or in the range of about 3000 sccm to about 6000 sccm, or in the range of about 3000 sccm to about 4000 sccm. Phosphine is introduced into the processing chamber at a flow rate in the range of about 0.1 sccm to 300 sccm, or in the range of about 100 sccm to about 300 sccm.

[0033] In another aspect, the first chlorosilane precursor gas is trichlorosilane (TCS), the second chlorosilane precursor gas is pentachlorodisilane (PCDS), and the n-type dopant gas includes triethylantimony and optionally phosphine. The mixture of TCS and PCDS includes a mixture of TCS to PCDS in the range of about 7:1 to about 20:1, or about 9:1 to about 16:1. In some embodiments, it has been shown that TCS grows an antimony-doped epitaxial layer only in the presence of PCDS and when no antimony-doped epitaxial layer is formed, or forms an antimony-doped epitaxial layer at a significantly reduced rate when PCDS does not co-flow with it. PCDS has been shown to increase the growth rate of the antimony-doped source / drain regions. The chlorosilane precursor gases enable the growth of an antimony-doped epitaxial layer. As the antimony-doped epitaxial layer grows, no etch-back operation is performed. Chlorine in the silicon chloride precursor has been shown to improve the crystalline growth of the epitaxial layer without an additional etch-back process. In one example, PCDS is introduced into the processing chamber at a flow rate in the range of about 100 sccm to about 1000 sccm, or in the range of about 300 sccm to about 600 sccm, or in the range of about 400 sccm to about 550 sccm, or in the range of about 450 sccm to about 500 sccm. Trichlorosilane is introduced into the processing chamber at a flow rate in the range of about 1000 sccm to about 10000 sccm, or in the range of about 7000 sccm to about 10000 sccm, or in the range of about 7500 sccm to about 9000 sccm, or in the range of about 8000 sccm to about 8500 sccm. Triethylantimony is introduced into the processing chamber at a flow rate in the range of about 0.1 sccm to 100 sccm, or in the range of about 100 sccm to about 300 sccm. Phosphine is introduced into the processing chamber at a flow rate in the range of about 0.1 sccm to 300 sccm, or in the range of about 100 sccm to about 300 sccm.

[0034] In operation 160, an n-type doped silicon layer is selectively formed on the first surface. A mixture of the first chlorosilane precursor gas, the second chlorosilane precursor gas, and one or more n-type dopants thermally react to selectively form an n-type doped silicon layer on the first surface. In one aspect, the n-type doped silicon layer is a phosphorus-doped silicon layer having a phosphorus concentration of 2×10 21 atoms / cm 3 or greater, such as 3.5×10 21 atoms / cm 3 , 3.9×10 21 atoms / m 3 , or 4×10 21 atoms g / cm 3 or greater. In another aspect, the n-type doped silicon layer is an antimony-doped silicon layer having an antimony concentration of 1×10 21 atoms / cm3 or greater, such as 1.5×10 21 atoms / cm 3 、2×10 21 atoms g / cm 3 or 3×10 21 atoms / cm 3 or a greater antimony-doped silicon layer. In some embodiments, the n-type doped silicon layer is then exposed to a heat treatment process, such as a spike annealing process. The spike annealing process can be carried out at a temperature of about 900 °C to about 1200 °C for a time of about 1 second to about 30 seconds.

[0035] Figure 2 FIG. shows a schematic isometric view of a horizontal gate all-around (hGAA) structure 200 according to one or more aspects of the present disclosure. Portions of the hGAA structure 200 can be formed according to method 100. The hGAA structure 200 includes a multi-material layer 205 having alternating first layers 206 and second layers 208, in which spacers 210 are formed. The hGAA structure 200 utilizes the multi-material layer 205 as a nanowire (e.g., a channel) between the source region 214a and the drain region 214b and the gate structure 212. The composition and formation of the source / drain regions 214a, 214b on the hGAA structure 200 are described. As Figure 2 shown in the cross-sectional view of the multi-material layer 205 in, the nanowire spacers 210 formed at the bottom (e.g., or the end) of each second layer 208 help manage the interface between the second layer 208 and the source / drain 214a, 214b to reduce parasitic capacitance and maintain minimal device leakage.

[0036] The hGAA structure 200 includes a multi-material layer 205 disposed on the top surface 203 of the substrate 202, such as on top of an optional material layer 204 disposed on the substrate 202. In embodiments where the optional material layer 204 is absent, the multi-material layer 205 is formed directly on the substrate 202.

[0037] In one example, the optional material layer 204 is an insulating material. Suitable examples of insulating materials can include silicon oxide materials, silicon nitride materials, silicon oxynitride materials, or any suitable insulating material. Alternatively, the optional material layer 204 can be any suitable material, including conductive materials or non-conductive materials as needed. The multi-material layer 205 includes at least a pair of layers, each pair containing a first layer 206 and a second layer 208. Although Figure 2The example shown in [figure] shows four pairs and a first layer 206 cap, but each pair includes a first layer 206 and a second layer 208 (alternating pairs, each pair containing a first layer 206 and a second layer 208). An additional first layer 206 is provided on top of the multi-material layer 205. The number of pairs can vary based on different process requirements, with additional or no additional first layer 206 or second layer 208. In at least one example, the thickness of each individual first layer 206 can be in the range of about to about , such as about and the thickness of each individual second layer 208 can be in the range of about to about , such as about The multi-material layer 205 can have a total thickness in the range of about to about , or about to about .

[0038] In at least one embodiment, the first layer 206 is a crystalline material layer, such as a single crystalline silicon layer, a polysilicon layer, or a monocrystalline silicon layer. The first layer 206 is formed using an epitaxial deposition process. Alternatively, the first layer 206 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, and the like. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, and the like. In yet another example, the first layer 206 is a III-V material, such as a GaAs layer.

[0039] The second layer 208 is an amorphous material layer. In at least one aspect, the second layer 208 is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layers. Alternatively, the second layer 208 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. In yet another example, the second layer 208 is a III-V material, such as a GaAs layer. In yet another example, the first layer 206 is a silicon layer, and the second layer 208 is a metal material having a high-k material coating on its outer surface. Suitable examples of high-k materials include hafnium dioxide (HfO 2 ), zirconium dioxide (ZrO 2 ), hafnium silicate (HfSiO 4 ), hafnium aluminum oxide (HfAlO), zirconium silicate (ZrSiO 4 ), tantalum pentoxide (TaO 2)), aluminum oxide, aluminum-doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT), etc. In a specific example, the coating is hafnium dioxide (HfO 2 ) layer. In at least one embodiment, the second layer 208 is a material similar to the gate structure 212 to form a surrounding gate around the first layer 206.

[0040] Spacers 210 are formed near the ends of the second layer 208 and can be considered part of the second layer 208. The spacers 210 are dielectric spacers or air gaps. The spacers 210 can be formed by using an etch precursor to etch away portions of each of the second layer 208 to form grooves at the ends of each of the second layer 208. The spacers 210 are formed in the grooves adjacent to each of the second layer 208. A liner layer (not shown) can be additionally deposited in the grooves before depositing the spacers 210. The spacers 210 are formed of a dielectric material and separate each of the nanowires or nanosheets formed as the first layer 206. In at least one embodiment, the spacers 210 are selected to be a silicon-containing material, such as a low-k material, that can reduce the parasitic capacitance between the gate and the source / drain structures in the hGAA nanowire structure. The silicon-containing material or low-k material can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbon oxide, silicon carbonitride, a doped silicon layer, or other suitable materials, such as Black material available from Applied Materials.

[0041] In at least one example, the spacers 210 are a low-k material (e.g., with a dielectric constant less than 4) or a material containing silicon oxide / silicon nitride / silicon carbide. In another example, the spacers 210 are air gaps.

[0042] The gate structure 212 is disposed above and around the multi-material layer 205. According to one embodiment, the gate structure 212 includes a gate electrode layer and may additionally include a gate dielectric layer, gate spacers, and a shielding layer. The gate electrode layer of the gate structure 212 includes a polysilicon layer or a metal layer covered with a polysilicon layer. The gate electrode layer can include metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), or molybdenum nitride (MoN x ))), metal carbides (such as tantalum carbide (TaC) or hafnium carbide (HfC)), metal carbonitrides (such as TaCN), metal oxides (such as molybdenum oxide (MoO x ))), metal oxynitrides (such as molybdenum oxynitride (MoO x N y))), metal silicides (such as nickel silicide), or combinations of the above. The gate electrode layer is disposed on top of the multi-material layer 205 and surrounds this multi-material layer.

[0043] A gate dielectric layer may optionally be disposed under the gate electrode layer and under the multi-material layer 205. The optional gate dielectric layer may include silicon oxide (SiO x ), which may be formed by thermal oxidation of one or more of the first layer 206 and / or the second layer 208, or formed by any suitable deposition process. Suitable materials for forming the gate dielectric layer include silicon oxide, silicon nitride, oxynitride, metal oxides, such as hafnium oxide (HfO 2 ), hafnium zirconium oxide (HfZrO x ), hafnium silicon oxide (HfSiO x ), hafnium titanium oxide (HfTiO x ), hafnium aluminum oxide (HfAlO x ), and combinations and multi-layers of the above. Gate spacers are formed on the sidewalls of the gate electrode layer. Each gate spacer includes a nitride portion and / or an oxide portion. A shielding layer is formed on top of the gate electrode layer and may include silicon nitride.

[0044] Using Figure 4 method 400 to form the hGAA structure 200. The described hGAA structure 200 is an n-channel metal oxide semiconductor (NMOS) device. Thus, the dopants within the hGAA structure 200 are n-type dopants, such as phosphorus, antimony, or combinations of the above. In at least one embodiment, the n-type dopant includes phosphorus (P). In at least another embodiment, the n-type dopant includes antimony (Sb). In yet another embodiment, the n-type dopant includes both phosphorus (P) and antimony (Sb).

[0045] During operation 410, a multi-material layer 205 and a gate structure 212 are formed on the substrate 202 and the optional material layer 204 as described with respect to Figure 2 . After operation 410, the hGAA structure 200 is similar to the structure shown in Figure 2 A. The combination of the multi-material layer 205 and the gate structure 212 may be described as a film stack. During operation 410, multiple deposition operations are used to form the multi-material layer 205 to form multiple alternating first layers 206 and second layers 208. A portion of the second layer 208 is etched back, and spacers 210 are formed.

[0046] A gate structure 212 is formed around the multi-material layer 205. In at least one embodiment, the gate electrode layer of the gate structure 212 is a material similar to the material of each second layer 208 within the multi-material layer 205. The gate structure 212 and the second layer 208 form a wrap-around gate around each first layer 206. The first layer 206 serves as a nanowire or nanosheet disposed within the wrap-around gate. After forming the source / drain regions, the first layer 206 serves as a channel between the source / drain regions.

[0047] After forming the film stack during operation 410, as Figure 2 shown in B, n-type doped source / drain regions 214a, 214b are formed during operation 420. The n-type doped source / drain regions 214a, 214b formed during operation 420 can be formed according to method 100. During operation 420, a deposition gas mixture is introduced into the process chamber to deposit the n-type doped source / drain regions 214a, 214b. The n-type doped source / drain regions 214a, 214b are deposited on the substrate 202 and each first layer 206 within the multi-material layer 205, as Figure 2 shown in B. In at least one embodiment, the n-type doped source / drain regions 214a, 214b have a thickness in the range of about 1 nm to about 10 nm. The n-type doped source / drain regions 214a, 214b are deposited by an epitaxial deposition process such as the selective epitaxial deposition process described in method 100. In at least one embodiment, the n-type doped source / drain regions 214a, 214b are selectively deposited on the first layer 206 and the exposed portions of the substrate 202 made of a crystalline material (such as Si), and the n-type doped source / drain regions 214b are not deposited on the gate structure 212 or the spacers 210, which are made of a dielectric material.

[0048] In at least one embodiment, the deposition gas mixture includes the described first chlorosilane precursor, second chlorosilane precursor, and n-type dopant.

[0049] The amount of excess point defects in the n-type doped source / drain regions 214a, 214b can be controlled by changing the processing conditions, such as the partial pressure of the precursor, the ratio of the precursors, the processing temperature, and / or the layer thickness. The amount of excess point defects in the n-type doped source / drain regions 214a, 214b can control the diffusion of Sb atoms into the first layer 206 of the multi-material layer 205. During the deposition of the n-type doped source / drain regions 214a, 214b, Sb atoms can diffuse into the first layer 206 of the multi-material layer 205. A P dopant is added to the n-type doped source / drain regions 214a, 214b using a P-containing precursor. The P-containing precursor flows simultaneously to both the chlorosilane-containing precursor and the Sb-containing precursor.

[0050] A precursor gas containing a first chlorosilane, a precursor gas containing a second chlorosilane, and each of the precursors containing an n-type are simultaneously co-introduced into a processing chamber. Co-introducing each of the precursor gas containing a first chlorosilane, the precursor gas containing a second chlorosilane, and the precursor gas containing an n-type increases the conductivity of the source / drain regions 214a, 214b doped with antimony and / or phosphorus, and enables the deposition temperature to be lower than 550 degrees Celsius. In some embodiments, the phosphorus precursor is a general n-type dopant precursor. In one example described, for TCS / DCS / PH3, the ratio of the first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (such as phosphorus) introduced into the process chamber is from about 3:1:0.1 to about 7:1:0.3. In another example described, for TCS / PCDS / TeSb, the ratio of the first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (such as antimony) introduced into the processing chamber is from about 7:1:0.1 to about 20:1:1, or from about 9:1:0.1 to 16:1:0.1. In yet another example described, for TCS / PCDS / TeSb / PH3, the ratio of the first chlorosilane precursor gas to the second chlorosilane precursor gas to the n-type dopant precursor gas (such as antimony) introduced into the processing chamber is from about 3:1:0.1:0.1 to about 7:1:0.3:0.3.

[0051] In one example, the n-type doped source / drain regions 214a, 214b have a phosphorus concentration of 2.0×10 21 atoms / cm 3 or greater, such as 3.5×10 21 atoms / cm 3 、3.9×10 21 atoms / cm 3 , or 4.0×10 21 atoms / cm 3 or greater. In another example, the n-type doped source / drain regions 214a, 214b have an antimony concentration of 1.0×10 21 atoms / cm 3 or greater, such as 1.5×10 21 atoms / cm 3 、2.0×10 21 atoms / cm 3 , or 3.0×10 21 atoms / cm 3 or greater. In yet another example, the n-type doped source / drain regions 214a, 214b have an antimony concentration of 1.0×10 21 atoms / cm 3 or greater, such as 1.5×10 21 atoms / cm 3 、2.0×1021 atoms / cm 3 , or 3.0×10 21 atoms / cm 3 or greater. The concentration of phosphorus dopants within the deposited n-type doped source / drain regions 214a, 214b is about 2.0×10 21 atoms / cm 3 to about 4.0×10 21 atoms / cm 3 . The low temperature deposition of the n-type doped source / drain regions 214a, 214b further reduces the migration of antimony into the multi-material layer 205 and other portions of the substrate, since the diffusion of antimony may lead to the degradation of device performance.

[0052] The concentration of antimony dopants within the n-type doped source / drain regions 214a, 214b changes the growth rate of the n-type doped source / drain regions 214a, 214b. It has been found that in cases with a lower concentration of antimony dopants or in embodiments without the co-flow of antimony dopants, the deposition rate of the n-type doped source / drain regions 214a, 214b at temperatures below 550 degrees Celsius is greatly reduced. In some embodiments, it has been found that the antimony concentration within the n-type doped source / drain regions 214a, 214b increases the deposition rate by more than twice the growth rate as compared to a process without any antimony-containing precursors. In some embodiments, in the case of not co-flowing the antimony-containing precursor and the chlorosilane precursor simultaneously, at temperatures below 550 degrees Celsius, on both the crystalline and non-crystalline positions of the substrate, the growth rate of the n-type doped source / drain regions 214a, 214b approaches zero. The antimony in the antimony-containing precursor is used to reduce the surface activation energy of the first layer 206, thereby forming the n-type doped source / drain regions 214a, 214b. The growth rate of the n-type doped source / drain regions 214a, 214b is highly selective to the crystalline structure, such that the growth rate of the n-type doped source / source regions 214a, 214b on the first layer 206 is greater than that of the n-type doped source regions / drain regions 214a, 214b on the spacer 210 and the gate structure 212 by about 100 times, such as greater than about 150 times the growth rate. In some embodiments, the growth rate of the n-type doped source / drain regions 214a, 214b is about 10 angstroms per minute to about 20 angstroms per minute.

[0053] In some embodiments, the deposition of the n-type doped source / drain regions 214a, 214b with antimony is carried out in a first processing chamber, and the doping of the n-type doped source / drain regions 214b with phosphorus is carried out in a second processing chamber. In other embodiments, the formation of the n-type doped source / drain regions 214a, 214b with antimony and the doping of the n-type doped source / drain regions 214a, 214b with phosphorus are carried out in one chamber.

[0054] After operation 420, operation 430 of heat-treating the hGAA structure 200 is performed. In at least one embodiment, the heat treatment of the hGAA structure is a spike annealing process. The spike annealing process is carried out at a temperature of about 900 °C to about 1200 °C for a time of about 1 second to about 30 seconds. Due to the large size of Sb atoms, Sb atoms do not diffuse at the same rate as P dopants. Therefore, the short time period of spike annealing suppresses the diffusion of Sb atoms while allowing some P dopants to diffuse in the first layer 206 to form a doped region 320 in the first layer 206 of the multi-material layer 205, as Figure 3C shown.

[0055] When the temperatures of operation 420 and operation 430 are maintained below about 550 °C, dopant diffusion and warping of the multi-material layer 205 are reduced.

[0056] After forming the n-type doped source / drain regions 214a, 214b, an overlying layer (not shown) may be deposited on the hGAA structure 200 as appropriate. The overlying layer is a silicon-containing layer and is deposited on top of each of the n-type doped source / drain regions 214a, 214b and the spacers 210 such that the overlying layer fills the gaps 211.

[0057] Examples:

[0058] The following non-limiting examples are provided to further illustrate the described embodiments. However, these examples are not intended to be comprehensive nor to limit the scope of the described embodiments.

[0059] The examples are carried out on a wafer having an exposed crystalline silicon layer with a patterned silicon nitride layer deposited on the exposed crystalline silicon layer. The patterned silicon nitride layer exposes trenches formed in the crystalline silicon.

[0060]

[0061] In the summary of the invention, the detailed description, the claims and the drawings, reference is made to specific features (including method operations) of the present disclosure. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, in the case where a particular feature is disclosed in the context of a particular aspect, embodiment or example or a particular claim of the present disclosure, this feature may also be combined with and / or used in the context of other particular aspects and embodiments of the present disclosure to the extent possible, and is generally used in the present disclosure.

[0062] The term "comprising" and its grammatical equivalents are used to indicate the presence, optionally, of other components, ingredients, operations, etc. For example, an article "comprising" (or "comprises") components A, B, and C may consist of (i.e., contain only) components A, B, and C, or may contain not only components A, B, and C, but also one or more other components. Further, whenever a composition, element, or group of elements is preceded by the transitional phrase "comprising" and its grammatical equivalents, it should be understood that it is contemplated that the transitional phrases "consisting essentially of", "consisting of", "selected from the group consisting of", or "is" may be placed before the same composition or group of elements prior to the recitation of such composition, element, or elements, and vice versa.

[0063] When referring to a method that includes two or more defined operations, the defined operations may be performed in any order or simultaneously, except where the context excludes this possibility, and the method may include one or more other operations that are performed before any of the defined operations, between two of the defined operations, or after all of the defined operations, except where the context excludes this possibility.

[0064] When introducing elements of the present disclosure or illustrative aspects or embodiments thereof, the articles "a / an", "the", and "said" are intended to mean that there is one or more elements.

[0065] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its basic scope, and its scope is determined by the appended claims.

Claims

1. A method of forming a semiconductor device, the method comprising: forming a multi-material layer on a substrate located in a processing region, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern; and Selectively form source and drain regions on the first crystalline layer of the substrate, wherein the formed source and drain regions contain an n-type dopant precursor concentration greater than about 1×10 21 atoms / cm 3 , and the forming of the source and drain regions further comprises: flowing a first chlorosilane precursor gas selected from dichlorosilane and trichlorosilane; Co-flow a higher-order chlorosilane precursor gas having the formula Cl y Si x H (2X+2-y) where y is 3 or more, and x is or more, and the higher-order chlorosilane precursor gas is different from the first chlorosilane precursor gas; co-flowing an n-type dopant precursor gas with the first chlorosilane precursor gas and the higher-order chlorosilane precursor gas; and heating the substrate to a temperature of about 550 °C or lower.

2. The method according to claim 1, wherein the higher-order chlorosilane precursor gas comprises trichlorosilane (Cl 3 SiH), hexachlorodisilane (Si 2 Cl 6 ), tetrachlorosilane (SiCl 4 ), pentachlorodisilane (Cl 5 Si 2 H), octachlorotrisilane (Cl 8 Si 3 ) or a combination of the above items.

3. The method of claim 1, wherein the flow rate of the higher-order chlorosilane precursor gas is 3:1 or greater than the flow rate of the first chlorosilane precursor gas.

4. The method of claim 3, wherein the flow rate of the higher-order chlorosilane precursor gas is 10:1 or greater than the flow rate of the first chlorosilane precursor gas.

5. The method of claim 3, wherein forming the source region and the drain region further comprises: maintaining the temperature within the processing region in the range of about 450 degrees Celsius to about 500 degrees Celsius, and maintaining the pressure within the processing region in the range of about 10 Torr to about 600 Torr.

6. The method of claim 1, wherein the n-type dopant precursor is a phosphorus-containing precursor, an antimony precursor, or a combination of the above.

7. The method according to claim 1, wherein the n-type dopant precursor is an antimony-containing precursor, and the concentration of the n-type dopant precursor is the antimony concentration in the source region and the drain region, and the antimony concentration is greater than about 2×10 21 atoms / cm 3 .

8. The method of claim 7, wherein the antimony-containing precursor is one or a combination of hydrogen antimonide, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, stibine, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony, and trimethylantimony.

9. The method of claim 1, wherein the growth rate of the source region and the drain region on the crystalline first layer is greater than about 50 times the growth rate on the non-crystalline second layer.

10. The method of claim 9, wherein the non-crystalline second layer further includes a dielectric spacer disposed on its outer side.

11. The method of claim 10, wherein during the selective formation of the source region and the drain region, a plurality of gaps are formed adjacent to the non-crystalline second layer.

12. The method of claim 3, the method further comprises: flowing the first chlorosilane precursor at a flow rate in the range of about 100 to about 1000 sccm; flowing the higher-order chlorosilane at a flow rate in the range of about 1000 to about 10000 sccm; and flowing the n-type dopant precursor at a flow rate in the range of about 300 to about 1000 sccm.

13. The method of claim 12, the method further comprises: flowing hydrogen at a flow rate in the range of about 1 to about 40 SLM.

14. A method of forming a semiconductor device, the method comprising: forming a multi-material layer on a substrate located in a processing region, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern; and Source and drain regions are selectively formed on the first crystalline layer of the substrate, wherein the formed source and drain regions contain an n-type dopant precursor concentration greater than about 2×10 21 atoms / cm 3 , and forming the source and drain regions further includes: flowing dichlorosilane; co-flowing trichlorosilane; co-flowing a phosphorus-containing precursor gas with the dichlorosilane and the trichlorosilane; and The substrate is heated to a temperature of about 550° C. or less, wherein a ratio of flow rates of TCS to DCS is in a range of about 3:1 to about 7:

1.

15. The method of claim 14, wherein the phosphorus-containing precursor gas is selected from phosphine, trimethylphosphine, dimethylphosphine, triethylphosphine, diethylphosphine, tri-tert-butylphosphine, or a combination thereof.

16. The method of claim 14, further comprising: include: flowing the dichlorosilane at a flow rate in a range of about 700 sccm to about 1000 sccm; flowing the trichlorosilane at a flow rate in a range of about 2000 sccm to about 7000 sccm; and Phosphine is flowed at a flow rate in a range of about 0.1 sccm to 300 sccm.

17. The method of claim 16, further comprising: include: The antimony-containing precursor gas is flowed at a flow rate in a range of about 10 seem to about 100 seem.

18. A method for forming a semiconductor device, the method include: forming a multi-material layer on a substrate located in a processing region, wherein the multi-material layer includes a plurality of crystalline first layers and a plurality of non-crystalline second layers arranged in an alternating pattern; as well as Selectively form source and drain regions on the first crystalline layer of the substrate, wherein the formed source and drain regions contain an n-type dopant precursor concentration greater than about 1×10 21 atoms / cm 3 , and the forming of the source and drain regions further comprises: causing pentachlorodisilane to flow; allowing trichlorosilane to co-flow; co-flowing an antimony-containing precursor gas with the pentachlorodisilane and the trichlorosilane; and The substrate is heated to a temperature of about 550° C. or less, wherein a ratio of flow rates of trichlorosilane to pentachlorodisilane is in a range of about 9:1 to about 16:

1.

19. The method of claim 18, wherein the antimony-containing precursor gas is selected from one or a combination of hydrogen antimonide, antimony trichloride, antimony tetrachloride, antimony pentachloride, triphenylantimony, antimony trihydride, antimony trioxide, antimony pentoxide, antimony trifluoride, antimony tribromide, antimony triiodide, antimony pentafluoride, triethylantimony and trimethylantimony.

20. The method of claim 18, further comprising: include: flowing the pentachlorodisilane at a flow rate in a range of about 100 sccm to about 1000 sccm; flowing the trichlorosilane at a flow rate in a range of about 7,000 sccm to about 10,000 sccm; and The antimony-containing precursor is flowed at a flow rate in a range of about 0.1 seem to 100 seem.

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