Asynchronous signal processing circuit and storage device

Abstract

The application discloses an asynchronous signal processing circuit and a storage device. In the asynchronous signal processing circuit, a signal processing circuit is configured to determine a timing relationship between a first input signal and a second input signal based on an output signal output by an output end of a received RS latch, and in response to a first state of the received first input signal being earlier than a first state of the received second input signal, output a first output signal with the first state and a second output signal with the first state, and make the first state of the first output signal earlier than the first state of the second output signal, and in response to none of the received first input signal being switched to the first state before the first state of the received second input signal ends, output the first output signal not switched to the first state and the second output signal with the first state.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage control, and particularly relates to an asynchronous signal processing circuit and a storage device. BACKGROUND

[0002] In the prior art, a storage device is usually provided with a normal mode and a low-power mode, and the low-power mode is usually used when the storage device does not need to operate at high power, so as to reduce consumption and reduce energy waste. The low-power mode usually includes a half sleep mode.

[0003] The defect of the prior art is that the storage chip of the storage device is usually configured with an asynchronous signal processing circuit, which is used to perform timing judgment on the received low-power mode exit signal and the operation signal issued in the low-power mode, so as to ensure that the storage chip exits the low-power mode and restores the normal mode when the low-power mode is not operating or is operating to a suitable state, so as to avoid errors. However, due to the conventional structure of the two-stage cascade flip-flop of the existing asynchronous signal processing circuit, when the rising edge or the initial high-level position interval of the received low-power mode exit signal and the operation signal issued in the low-power mode is short, the next stage flip-flop cannot obtain sufficient signal setup time, so that the output correct timing judgment signal cannot be effectively obtained, the low-power mode exit signal is lost, the low-power mode exit signal cannot be responded in time, whether the low-power mode exit signal has been responded is also not determined, and the reliability of the storage device is poor. SUMMARY

[0004] The technical problem solved by the present application is that the asynchronous exit operation of the asynchronous signal processing circuit in the chip (such as a storage chip) is prone to errors in extreme cases.

[0005] To solve the above technical problems, the first technical solution adopted by the present application is: an asynchronous signal processing circuit, comprising: an RS latch, the RS latch respectively receives a first input signal and a second input signal, the first input signal and the second input signal are asynchronous signals; a signal processing circuit, the signal processing circuit is used for respectively receiving the output signal of the output end of the RS latch and the second input signal, and determining the timing relationship between the first input signal and the second input signal based on the received output signal of the output end of the RS latch, and in response to the first state of the received first input signal being earlier than the first state of the received second input signal, outputting a first output signal with a first state and a second output signal with a first state, and making the first state of the first output signal earlier than the first state of the second output signal, and in response to none of the received first input signal being switched to the first state before the first state of the received second input signal ends, outputting a first output signal not switched to the first state and a second output signal with a first state.

[0006] Among them, the signal processing circuit comprises: a first circuit, the first circuit is connected with the output end of the RS latch, and the first circuit is used for outputting a first output signal with a first state in response to the inverse signal of the output signal of the output end of the RS latch being a first state, and outputting a first output signal with a second state in response to the inverse signal of the output signal of the output end of the RS latch being a second state; a second circuit, the second circuit is connected with the output end of the RS latch, and the second circuit is used for outputting a second output signal with a first state after the first output signal is a first state in response to the inverse signal of the output signal of the output end of the RS latch being a first state, and performing delay processing on the second input signal to generate and output a second output signal with a first state in response to the inverse signal of the output signal of the output end of the RS latch being a second state.

[0007] Among them, the first circuit comprises: a first NOT gate, the input end of the first NOT gate is connected with the output end of the RS latch, and the output end of the first NOT gate is used for outputting the first output signal.

[0008] Among them, the first state is a high level state, and the second state is a low level state; the second circuit comprises: a first delay device, the input end of the first delay device is connected with the second input end of the RS latch for receiving the second input signal; a selector, the first input end of the selector is used for receiving a third input signal, the third input signal is switched to a high level signal when the first output signal is switched to a high level signal, the second input end of the selector is connected with the output end of the first delay device, the selection end of the selector is connected with the output end of the first NOT gate, the selector is used for connecting the first input end and the output end thereof in response to the selection end receiving a high level, and connecting the second input end and the output end thereof in response to the selection end receiving a low level, and the output end of the selector is used for outputting the second output signal.

[0009] The first circuit further comprises: a second delay device, an input end of the second delay device being connected to an output end of the first NAND gate; a D latch device, an input end of the D latch device being connected to an output end of the second delay device, a control end of the D latch device being configured to receive a fourth input signal, and an output end of the D latch device being configured to output a first output signal; the fourth input signal is switched to a high level signal when the first output signal is a low level signal and the second output signal is a high level signal, and a delay time of the second delay device is greater than a setup time of the fourth input signal switched to the high level signal; a third input end of the RS latch device is configured to receive a fifth input signal, the fifth input signal and the fourth input signal being inverse signals of each other, the third input end of the RS latch device, a first input end of the RS latch device and an output end of the RS latch device being located on the same NAND gate, and the third input end of the RS latch device and a second input end of the RS latch device being located on different NAND gates.

[0010] The delay time of the first delay device is greater than a maximum setup time when a signal output by the output end of the RS latch device is switched from a high level signal to a low level signal.

[0011] The asynchronous signal processing circuit is applied to control the storage chip to exit a semi-sleep mode, and the semi-sleep mode is a mode in which a normal phase and a low-power-consumption phase are cyclically switched; the first input signal is switched to a first state when an instruction to exit the semi-sleep mode is received; and the second input signal is switched to the first state first and then switched to a second state when the storage chip is switched from the normal phase to the low-power-consumption phase.

[0012] The asynchronous signal processing circuit further comprises: a control logic module, the control logic module being configured to, in response to the first output signal being the first state and the second output signal being the first state, control the storage chip to exit the semi-sleep mode; and the control logic module being further configured to, in response to the first output signal being the second state and the second output signal being the first state, control the storage chip to enter the low-power-consumption phase.

[0013] The second input signal is switched to the second state after the storage chip is in the low-power-consumption phase, and the second input signal remains in the second state after the storage chip is switched from the low-power-consumption phase to the normal phase, and the second input signal is switched to the first state first and then switched to the second state when the storage chip is switched from the normal phase to the low-power-consumption phase.

[0014] To solve the above technical problems, a second technical solution is adopted in the present application: a storage device comprising the asynchronous signal processing circuit.

[0015] The application has the beneficial effects that: different from the prior art, in the technical scheme of the application, the RS latch respectively receives the first input signal and the second input signal, the signal processing circuit is used for respectively receiving the signal output by the output end of the RS latch and the second input signal, the signal processing circuit is used for determining the timing relationship between the first input signal and the second input signal based on the received signal output by the output end of the RS latch, and in response to the first state of the received first input signal being earlier than the first state of the received second input signal, the first output signal with the first state and the second output signal with the first state are output, and the first state of the first output signal is earlier than the first state of the second output signal, and in response to none of the received first input signals being switched to the first state before the end of the first state of the received second input signal, the first output signal not switched to the first state and the second output signal with the first state are output. Based on the above-mentioned mode, after the signal processing circuit responds to the first state of the received first input signal being earlier than the first state of the received second input signal, even if the interval between the first input signal and the second input signal received by the RS latch is extremely short, the subsequent RS latch can still be switched to the latch mode when the first input signal and the second input signal are received at the same time, and the output of the RS latch remains unchanged, so that the signal processing circuit can continue to respond to the first state of the received first input signal being earlier than the first state of the received second input signal, and output the earlier first output signal and the later second output signal in turn, and in response to none of the received first input signals being switched to the first state before the end of the first state of the received second input signal, even if the first input signal switched to the first state is received after the end of the first state of the second input signal, the situation can be determined through the output of the first output signal not switched to the first state and the second output signal with the first state, and in summary, the timing judgment result between the received first input signal and the second input signal can be obtained through the timing relationship between the first output signal and the second output signal output by the signal processing circuit, so that the asynchronous signal processing circuit can subsequently determine the sampling condition of the first input signal or the second input signal based on the current timing judgment result in time, and then perform the asynchronous exit operation based on the sampling condition, and in further embodiments, the storage device in which the asynchronous signal processing circuit is located can be conveniently controlled and processed in time, and the reliability of the storage device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and all other drawings obtained by those skilled in the art without creative effort based on these drawings also belong to the protection scope of the present application.

[0017] Figure 1 is a structural schematic diagram of an embodiment of the asynchronous signal processing circuit of the present application;

[0018] Figure 2 is a structural schematic diagram of another embodiment of the asynchronous signal processing circuit of the present application;

[0019] Figure 3 is a waveform schematic diagram of the first example of the present application;

[0020] Figure 4 is a waveform schematic diagram of the second example of the present application;

[0021] Figure 5 is a waveform schematic diagram of an embodiment of the signal output by the RS latch of the present application;

[0022] Figure 6 is a structural schematic diagram of an embodiment of the storage device of the present application.

[0023] Reference signs: RS latch 11, signal processing circuit 12, first circuit 121, first NOT gate 1211, second delay device 1212, D latch 1213, second circuit 122, first delay device 1221, selector 1222, storage device 20, asynchronous signal processing circuit 21. DETAILED DESCRIPTION

[0024] The present application will be further described in details below in combination with the drawings and embodiments. It is particularly pointed out that the following embodiments are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only some embodiments of the present application, but not all embodiments of the present application, and all other embodiments obtained by those skilled in the art without creative effort also belong to the protection scope of the present application.

[0025] In this paper, the phrase "embodiment" means that the specific features, structures or characteristics described in combination with the embodiment can be contained in at least one embodiment of the present application. The appearance of this phrase in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "setting", "connecting", "connecting" should be understood broadly, for example, it can be fixed connection, it can be detachable connection, or integral connection; it can be mechanically connected, or electrically connected; it can be directly connected, or connected through an intermediate medium. For those skilled in the art, the above belongs to the specific meaning of the present application under the specific circumstances.

[0027] In the prior art, the storage device is usually provided with a normal mode and a low power consumption mode, which is usually used when the storage device does not need to operate at high power to reduce consumption and energy waste. The low power consumption mode usually includes a half sleep mode.

[0028] The defect of the prior art is that the storage chip of the storage device is usually configured with an asynchronous signal processing circuit, which is used to make timing judgment on the received low power consumption mode exit signal and the operation signal issued in the low power consumption mode, to ensure that the storage chip exits the low power consumption mode and restores the normal mode when the low power consumption mode is not operating or operating to the appropriate state, to avoid errors. However, due to the conventional structure of the two-stage cascade flip-flop of the existing asynchronous signal processing circuit, it is easy to cause the rear stage flip-flop to fail to obtain sufficient signal setup time due to the short interval time between the rising edge or high level initial position of the received low power consumption mode exit signal and the operation signal issued in the low power consumption mode, so that the output correct timing judgment signal cannot be effectively obtained, the low power consumption mode exit signal is lost, and the storage device cannot respond to the low power consumption mode exit signal in time, resulting in poor reliability of the storage device.

[0029] For example, if the operation signal issued in the low power consumption mode is the signal issued when the normal stage is switched to the low power consumption stage in the low power consumption mode, the storage chip in the storage device can be controlled to exit the low power consumption mode only when it is detected that the received low power consumption mode exit signal is earlier than the operation signal issued in the low power consumption mode. Otherwise, if the received low power consumption mode exit signal is later than the operation signal issued in the low power consumption mode, the storage chip in the storage device is controlled to exit the low power consumption mode, which is easy to cause the storage chip in the storage device to exit the low power consumption mode in the low power consumption stage, and the exited storage chip is still in the low power consumption stage, and the low power consumption mode is generally required to be in the normal mode or higher power consumption mode, which is easy to cause the storage chip to occur errors or faults, and the reliability is poor.

[0030] Therefore, there is a need for a circuit that can accurately and timely detect the timing judgment result of the received two signals to solve the above problems.

[0031] The application provides an asynchronous signal processing circuit, which refers to Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of an embodiment of the asynchronous signal processing circuit, Figure 2 is a structural schematic diagram of another embodiment of the asynchronous signal processing circuit, as shown in Figure 1 and Figure 2 , the asynchronous signal processing circuit comprises an RS latch 11 and a signal processing circuit 12.

[0032] The RS latch 11 receives a first input signal A1 and a second input signal B1 respectively.

[0033] The first input signal and the second input signal are asynchronous signals.

[0034] The first input terminal of the RS latch 11 can be used for receiving the first input signal A1, and the second input terminal can be used for receiving the second input signal B1. Due to the characteristics of the RS latch 11, if one of the signals received by the first input terminal and the second input terminal of the RS latch 11 is a high-level signal and the other is a low-level signal, the output terminal of the RS latch 11 will output a signal of a different level according to the combination of the different input level signals. Then, if the signals received by the first input terminal and the second input terminal of the RS latch 11 are both switched to high level, the signal output by the output terminal of the RS latch 11 will remain unchanged at the output of the previous state.

[0035] However, when the RS latch 11 receives signals in which one is a high-level signal and the other is a low-level signal, the output terminal of the RS latch 11 can quickly output a signal of a corresponding level. Even if the first input signal A1 and the second input signal B1 are rapidly changed to high-level signals due to the extremely short interval of the first state between the first input signal A1 and the second input signal B1, the output of the RS latch 11 will not be affected, but will enter the holding state of the RS latch 11 to maintain the output unchanged.

[0036] The signal processing circuit 12 is configured to receive the output signal of the RS latch 11 and the second input signal B1, and determine the timing relationship between the first input signal A1 and the second input signal B1 based on the received output signal of the RS latch 11, and output the first output signal A2 with the first state and the second output signal B2 with the first state in response to the first state of the received first input signal A1 being earlier than the first state of the received second input signal B1, and make the first state of the first output signal A2 earlier than the first state of the second output signal B2, and output the first output signal A2 without the first state and the second output signal B2 with the first state in response to none of the received first input signal A1 being switched to the first state before the first state of the received second input signal B1 ends.

[0037] In the case that the output of the RS latch 11 remains unchanged, the signal processing circuit 12 can determine the timing relationship between the first state of the first input signal A1 and the first state of the second input signal B1 more accurately.

[0038] In the case that the signal processing circuit 12 accurately detects that the first state of the received first input signal A1 is earlier than the first state of the received second input signal B1, for example, the first state can be a high state, the signal processing circuit 12 can make the first state of the output first output signal A2 earlier than the first state of the output second output signal B2, so as to indicate that the first input signal A1 is determined to be earlier than the first state of the received second input signal B1 based on the RS latch 11 in the form that the first state of the first output signal A2 is earlier than the first state of the second output signal B2.

[0039] For example, if the first state of the first input signal A1 indicates that an instruction to exit the semi-sleep mode is received, and the first state of the second input signal B1 indicates that the storage chip is about to be switched from the normal stage in the semi-sleep mode to the low-power stage, in the case that the first state of the received first input signal A1 is earlier than the first state of the received second input signal B1, if the semi-sleep mode is exited at this time, it can be ensured that the storage chip is exited from the semi-sleep mode in the normal stage of the semi-sleep mode before the storage chip is switched from the normal stage in the semi-sleep mode to the low-power stage, so as to improve the possibility that the storage chip can normally operate after the semi-sleep mode is exited, and at this time, the storage chip can be normally exited by making the first state of the output first output signal A2 earlier than the first state of the output second output signal B2, so as to trigger the storage chip to exit the semi-sleep mode, and improve the reliability of the storage device.

[0040] In the prior art, due to the structure of the two-stage flip-flop in the asynchronous signal processing circuit, when the first state of the first input signal A1 is earlier than the first state of the second input signal B1, and the interval between the first state of the first input signal A1 and the first state of the second input signal B1 is short, the two-stage flip-flop cannot output the current judgment result smoothly, and thus cannot output the result of the corresponding timing judgment for the currently received first input signal A1 and second input signal B1 in time, and the reliability is poor.

[0041] Therefore, based on the technical solution of the present application, the possibility that the asynchronous signal processing circuit can still normally perform timing judgment to output a signal representing the corresponding result can be improved when the first state of the first input signal A1 is earlier than the first state of the second input signal B1, and the time interval between the first state of the first input signal A1 and the first state of the second input signal B1 is short, and the reliability of the storage device is improved.

[0042] In addition, when the received first input signal A1 is not switched to the first state before the end of the first state of the received second input signal B1, for example, when the first state of the received first input signal A1 is later than the first state of the received second input signal B1, the signal output by the RS latch 11 is different from the signal output by the RS latch 11 when the first state of the received first input signal A1 is earlier than the first state of the received second input signal B1.

[0043] Therefore, according to the signal output by the RS latch 11, it can be determined whether the received first input signal A1 is switched to the first state before the end of the first state of the received second input signal B1, or whether the first state of the received first input signal A1 is later than the first state of the received second input signal B1.

[0044] For example, if the first state of the first input signal A1 represents receiving an instruction to exit the semi-sleep mode, and the first state of the second input signal B1 represents that the storage chip is about to be switched from the normal stage to the low-power stage in the semi-sleep mode, if the first state of the first input signal A1 is later than the first state of the second input signal B1 received at this time, if the storage chip exits the semi-sleep mode at this time, it is easy to make the storage chip exit the semi-sleep mode from the low-power stage of the semi-sleep mode, and further make the storage chip unable to normally operate after exiting the semi-sleep mode. At this time, the storage chip cannot exit the semi-sleep mode at this time, and the storage chip is triggered not to exit the semi-sleep mode at this time, waits for the first state of the first input signal A1 received later than the first state of the second input signal B1 to appear subsequently, and then makes the storage chip exit the semi-sleep mode, which further improves the reliability of the storage device.

[0045] Distinguishing from the prior art, in the technical solution of the application, the RS latch respectively receives the first input signal and the second input signal, the signal processing circuit is used for respectively receiving the signal output by the output end of the RS latch and the second input signal, the signal processing circuit is used for determining the timing relationship between the first input signal and the second input signal based on the received signal output by the output end of the RS latch, and in response to the first state of the received first input signal being earlier than the first state of the received second input signal, the first output signal with the first state and the second output signal with the first state are output, and the first state of the first output signal is earlier than the first state of the second output signal, and in response to none of the received first input signals being switched to the first state before the end of the first state of the received second input signal, the first output signal not switched to the first state and the second output signal with the first state are output. Based on the above-mentioned manner, after the signal processing circuit responds to the first state of the received first input signal being earlier than the first state of the received second input signal, even if the interval between the first input signal and the second input signal received by the RS latch is extremely short, the subsequent RS latch can still switch to the latch mode when the first input signal and the second input signal are received at the same time, and the output of the RS latch remains unchanged, therefore, in the case that the first input signal is received first and the second input signal is received after an extremely short interval, the signal processing circuit can continue to respond to the first state of the received first input signal being earlier than the first state of the received second input signal, and output the earlier first output signal and the later second output signal in turn, and in the case that none of the received first input signals is switched to the first state before the end of the first state of the received second input signal, even if the first input signal switched to the first state is received after the end of the first state of the second input signal, the case can also be determined through the output of the first output signal not switched to the first state and the second output signal with the first state. In summary, the timing relationship between the first output signal and the second output signal output by the signal processing circuit can obtain the result of the timing judgment between the received first input signal and the second input signal, so that the asynchronous signal processing circuit can subsequently determine the sampling condition of the first input signal or the second input signal based on the current result of the timing judgment, and then perform the asynchronous exit operation based on the sampling condition. In further embodiments, it is more convenient to timely control and process the storage device where the asynchronous signal processing circuit is located, and the reliability of the storage device is improved.

[0046] For example, if the first state of the received first input signal A1 is earlier than the first state of the received second input signal B1, it means that the sampling of the first input signal A1 is normally implemented, and the first output signal A2 with the first state and the second output signal B2 with the first state are outputted to represent the first case.

[0047] If the first state of the received first input signal A1 is not switched before the end of the first state of the received second input signal B1, it means that the sampling of the first input signal A1 is not normally implemented, and the first output signal A2 not switched to the first state and the second output signal B2 with the first state are outputted to represent the second case.

[0048] Based on the different output signals, it can be determined whether the case belongs to the first case or the second case, and based on the corresponding case, it can be determined whether the sampling of the signals is continued or still needs to wait for the next sampling, so that the storage device is controlled in time based on the sampling case, and the reliability of the storage device is improved.

[0049] In an embodiment, as shown in FIG. 1, the signal processing circuit 12 includes a first circuit 121 and a second circuit 122. Figure 1 and Figure 2 The signal processing circuit 12 includes a first circuit 121 and a second circuit 122.

[0050] The first circuit 121 is connected to the output end of the RS latch 11, and the first circuit 121 is configured to output the first output signal A2 with the first state in response to the inverse signal of the signal outputted by the output end of the RS latch 11 being the first state, and output the first output signal A2 with the second state in response to the inverse signal of the signal outputted by the output end of the RS latch 11 being the second state.

[0051] The second circuit 122 is connected to the output end of the RS latch 11, and the second circuit 122 is configured to output the second output signal B2 with the first state after the first output signal A2 is the first state in response to the inverse signal of the signal outputted by the output end of the RS latch 11 being the first state, and delay the second input signal B1 to generate and output the second output signal B2 with the first state in response to the inverse signal of the signal outputted by the output end of the RS latch 11 being the second state.

[0052] Specifically, in the first case, when the inverse signal of the signal outputted from the output terminal of the RS latch 11 is in the first state, at this time, the first state of the received first input signal A1 is earlier than the first state of the received second input signal B1, the first circuit 121 can output the first output signal A2 in the first state, and the second circuit 122 can output the second output signal B2 in the first state after the first circuit 121 outputs the first output signal A2 in the first state, so as to realize outputting the first output signal A2 in the first state and the second output signal B2 in the first state, and making the first state of the first output signal A2 earlier than the first state of the second output signal B2.

[0053] In the second case, when the inverse signal of the signal outputted from the output terminal of the RS latch 11 is in the second state, at this time, the first state of the received first input signal A1 is later than the first state of the received second input signal B1, the first circuit 121 can output the first output signal A2 in the second state, and the second input signal B1 generates the second output signal B2 in the first state after delay processing, so as to realize outputting the first output signal A2 without the first state and the second output signal B2 with the first state.

[0054] Based on the above manner, different timing relationships between the first state of the first input signal A1 and the first state of the second input signal B1 can be represented through different combinations of the signal outputted by the first circuit 121 and the signal outputted by the second circuit 122, so as to output the result of timing judgment, and improve the reliability of the storage device.

[0055] Optionally, as shown in Figure 1 and Figure 2 the first circuit 121 comprises a first NOT gate 1211.

[0056] The input terminal of the first NOT gate 1211 is connected to the output terminal of the RS latch 11, and the output terminal of the first NOT gate 1211 is used to output the first output signal A2.

[0057] Specifically, the signal outputted by the first NOT gate 1211, i.e. the inverse signal of the signal outputted from the output terminal of the RS latch 11 mentioned in the foregoing embodiment, can generate and output the corresponding first output signal A2 based on the inverse signal of the signal outputted from the output terminal of the RS latch 11, so that the level state of the first output signal A2 can reflect the level state of the first input signal A1.

[0058] Further, as shown in Figure 1 and Figure 2 the first state is a high level state, and the second state is a low level state.

[0059] The second circuit 122 comprises a first delay device 1221 and a selector 1222.

[0060] The input end of the first delay device 1221 is connected with the first input end of the RS latch 11, the first input end of the RS latch 11 is used for receiving the first input signal A1, and the second input end of the RS latch 11 is used for receiving the second input signal B1.

[0061] The first input end of the selector 1222 is used for receiving the third input signal C1, the third input signal C1 is switched to a high level signal when the first output signal A2 is switched to a high level signal, the second input end of the selector 1222 is connected with the output end of the first delay device 1221, the selection end of the selector 1222 is connected with the output end of the first NOT gate 1211, the selector 1222 is used for connecting its first input end and its output end in response to the selection end receiving a high level, and connecting its second input end and its output end in response to the selection end receiving a low level, and the output end of the selector 1222 is used for outputting the second output signal B2.

[0062] Specifically, the delay time of the first delay device 1221 is greater than the maximum setup time of the signal outputted by the output end of the RS latch 11 being switched from a high level signal to a low level signal.

[0063] The third input signal C1 is a high level signal generated after the first output signal A2 is a high level signal, or is a signal switched from a low level signal to a high level signal after the first output signal A2 is a high level signal, so as to ensure that the first state of the second output signal B2 generated based on the third input signal C1 is later than the first state of the first output signal A2.

[0064] In addition, by setting the first delay device 1221 to perform corresponding delay processing, the first state of the second input signal B1 can be ensured to arrive at the selector 1222 after the signal outputted by the output end of the RS latch 11 in the first state is generated and the selector 1222 is controlled, so as to reduce the possibility that the first state of the second output signal B2 is earlier than the first output signal A2 due to the second input signal B1 arriving at the selector 1222 too early, and further improve the reliability of the storage device.

[0065] Furthermore, as shown in Figure 2 The first circuit 121 further includes a second delay device 1212 and a D latch 1213.

[0066] The input end of the second delay device 1212 is connected with the output end of the first NOT gate 1211.

[0067] An input terminal of the D latch 1213 is connected to an output terminal of the second delay device 1212, a control terminal of the D latch 1213 is configured to receive a fourth input signal D1, and an output terminal of the D latch 1213 is configured to output a first output signal A2.

[0068] The fourth input signal D1 is switched to a high level signal when the first output signal A2 is a low level signal and the second output signal B2 is a high level signal, and a delay time of the second delay device 1212 is greater than a setup time of the fourth input signal D1 switched to the high level signal.

[0069] A third input terminal of the RS latch 11 is configured to receive a fifth input signal E1, the fifth input signal E1 and the fourth input signal D1 are inverse signals of each other, the third input terminal of the RS latch 11, a first input terminal of the RS latch 11 and an output terminal of the RS latch 11 are located on a same NAND gate, and the third input terminal of the RS latch 11 and a second input terminal of the RS latch 11 are located on different NAND gates.

[0070] Specifically, when the first output signal A2 is a low level signal and the second output signal B2 is a high level signal, the current low level signal of the first output signal A2 can be latched and output by the D latch 1213 by switching the fourth input signal D1 to a high level signal, at this time, if a time for which a signal output from the output terminal of the RS latch 11 is converted from a low level signal to a high level signal due to a metastable state is greater than a delay time of the first delay device 1221, a high level signal of the signal output from the output terminal of the RS latch 11 generated too slowly can be prevented from affecting the first output signal A2 to maintain a low level signal output state by making the delay time of the second delay device 1212 greater than a setup time of the fourth input signal D1 switched to the high level signal.

[0071] Based on the above manner, the duration of the signal output from the output end of the RS latch 11 from a low-level signal to a high-level signal due to the metastability of the output end of the RS latch 11 can be avoided, and the situation that the second output signal B2 in the high-level state (first state) is output first, and the first output signal A2 in the high-level state (first state) is output later can be avoided. This situation can easily lead to the situation that the signal processing circuit 12 outputs the first output signal A2 without the first state and the second output signal B2 with the first state for a short time, for example, which can trigger the storage chip to enter the low-power stage of the semi-sleep mode. However, the signal processing circuit 12 outputs the first output signal A2 with the first state and the second output signal B2 with the first state quickly, which can easily misjudge that the storage chip can normally exit the semi-sleep mode, so that the storage chip exits the semi-sleep mode from the low-power stage of the semi-sleep mode, thereby increasing the possibility of errors or failures of the storage chip. Therefore, by avoiding this situation, the reliability of the storage device can be further improved.

[0072] The specific examples of the storage chip of the storage device having the semi-sleep mode will be described in detail. Referring to Figures 3 to 5 , Figure 3 is a waveform diagram of the first example of the present application, Figure 4 is a waveform diagram of the second example of the present application, Figure 5 is a waveform diagram of an embodiment of the output signal of the RS latch, as Figures 2 to 5 shown, for example:

[0073] The asynchronous signal processing circuit is applied to control the storage chip in the storage device to exit the semi-sleep mode, or control the storage chip in the storage device to transition from the normal stage to the low-power stage in the semi-sleep mode. The storage chip cyclically switches between the normal stage and the low-power stage when in the semi-sleep mode. In the normal stage, the running power of the storage chip is relatively high, which is convenient for normal operation. In the low-power stage, the running power of the storage chip is relatively low, which is usually used for sleep to reduce energy consumption and cannot normally operate. If the storage chip is in the normal stage when exiting the semi-sleep mode, it can normally operate. On the contrary, if the storage chip is in the low-power stage when exiting the semi-sleep mode, errors or failures can occur.

[0074] The first input signal A1 is switched to the first state (such as a high-level signal) when receiving the instruction to exit the semi-sleep mode.

[0075] The second input signal B1 is switched to the first state (such as a high-level signal) first, and then switched to the second state (such as a low-level signal) when the storage chip is switched from the normal stage to the low-power stage.

[0076] Specifically, the asynchronous signal processing circuit may also include a control logic module (not shown in the figure), which is used to control the memory chip to exit the semi-sleep mode in response to the first output signal A2 being in a first state (such as a high-level signal) and the second output signal B2 being in a first state (such as a high-level signal).

[0077] The control logic module can be a processor, a module formed by at least one processing circuit, or a module with processing capabilities constructed in other forms; no limitation is made here.

[0078] The control logic module is also used to control the memory chip to enter a low-power phase in response to the first output signal A2 being in a second state (such as a low-level signal) and the second output signal B2 being in a first state (such as a high-level signal).

[0079] Specifically, the second input signal B1 switches to a second state (e.g., a low-level signal) after the memory chip is in a low-power phase, and maintains the second state (e.g., a low-level signal) after the memory chip switches from the low-power phase to the normal phase, and switches to a first state (e.g., a high-level signal) and then switches to the second state (e.g., a low-level signal) when the memory chip switches from the normal phase to the low-power phase.

[0080] In the first example, such as Figure 2 and Figure 3 As shown, if the high-level state of the first input signal A1 received by the signal processing circuit 12 is earlier than the high-level state of the second input signal B1 received, it indicates that the moment the instruction to exit the semi-sleep mode is received is when the semi-sleep mode has not yet transitioned to the low-power stage. At this time, the signal A2* output by the output terminal of the RS latch 11 can be switched to a high-level signal, so that the selector 1222 connects its first input terminal and its output terminal. Based on the signal A2* output by the output terminal of the RS latch 11, the D latch 1213 generates and outputs a first high-level signal A2. Then, based on the first high-level signal A2, a third high-level signal C1 is generated, so that the selector 1222 outputs a second high-level signal B2. Thus, the first output signal A2 is output as a high-level signal, and the second output signal B2 is output as a high-level signal, and the high-level state of the first output signal A2 is earlier than the high-level state of the second output signal B2, thereby controlling the memory chip to exit the semi-sleep mode.

[0081] It should be noted that the fourth input signal D1 is specifically a low-level signal when the first output signal A2 outputs a low-level signal and the second output signal B2 outputs a high-level signal, and after triggering the storage chip to enter the low-power stage, the fourth input signal D1 is switched to a high-level signal, and the fourth input signal D1 will be switched to a low-level signal when the storage chip is converted from the low-power stage to the normal stage, that is, the fourth input signal D1 is a high-level signal in the low-power stage, and the fourth input signal D1 is a low-level signal in the normal stage.

[0082] In the process of the first example, since the high-level state of the first output signal A2 is earlier than the high-level state of the second output signal B2, the condition that the first output signal A2 outputs a low-level signal and the second output signal B2 outputs a high-level signal does not occur, that is, the storage chip does not trigger to enter the low-power stage, but is in the normal stage, so the fourth input signal D1 is a low-level signal all the time, and the fifth input signal E1 is a high-level signal all the time.

[0083] In the second example, as shown in Figure 2 and Figure 4 , if the high-level state of the first input signal A1 received by the signal processing circuit 12 is later than the high-level state of the second input signal B1 received, a period of time will be generated, if the second input signal B1 received by the signal processing circuit 12 is in a high-level state, and the first input signal A1 received is still in a low-level state, at this time, the first output signal A2 will be switched to a low-level signal with the output signal A2* of the output end of the RS latch 11 being a low-level signal, and the output signal A2* of the output end of the RS latch 11 will not change even if the first input signal A1 is switched to a high-level signal.

[0084] The output signal A2* of the output end of the RS latch 11 is a low-level signal, so the selector 1222 connects its second input end and its output end, so that the second input signal B1 of a high-level signal generates and outputs the second output signal B2 after delay processing, thereby realizing that the first output signal A2 outputs a low-level signal, and the second output signal B2 outputs a high-level signal, and controlling the storage chip to enter the low-power stage.

[0085] In the third example, as shown in Figure 2 and Figure 5 , the output signal of the output end of the RS latch 11 may cause a longer time to change between high and low levels due to the existence of metastable state, so two possibilities may occur:

[0086] The first possibility is that the signal outputted from the output terminal of the RS latch 11 is not completely switched from high level to low level, but returns to high level. In this case, the signal outputted from the output terminal of the RS latch 11 does not change at all, and does not affect the judgment of the asynchronous signal processing circuit on whether to exit the semi-sleep mode.

[0087] The second possibility is that the signal outputted from the output terminal of the RS latch 11 is switched from high level to low level for a very long time, that is, the output of the first NOT gate 1211 is switched from low level to high level for a very long time. When the signal outputted from the first NOT gate 1211 is a low level signal, it is usually the condition described in the second example. If, thereafter, the total time for which the signal outputted from the first NOT gate 1211 is switched from a low level signal to a high level signal is too long under the condition of the first example, and if Figure 1 If the D latch 1213 is not provided, the second input signal B1 will generate and output a high level signal second output signal B2 before the signal outputted from the first NOT gate 1211 at high level reaches the selector 1222 after delay processing, and then generate a high level signal first output signal A2 based on the slowly generated signal outputted from the first NOT gate 1211. This will easily lead to the situation that the control logic module controls the storage chip to exit the semi-sleep mode after controlling the storage chip to enter the low power consumption stage, which will increase the possibility of errors or faults of the storage chip.

[0088] If, thereafter, the total time for which the signal outputted from the first NOT gate 1211 is switched from a low level signal to a high level signal is too long under the condition of the first example, and if Figure 2 If the D latch 1213 is provided, the second input signal B1 will generate and output a high level signal second output signal B2 before the signal outputted from the first NOT gate 1211 at high level reaches the selector 1222 after delay processing, which will cause the control logic module to control the storage chip to enter the low power consumption stage and generate a high level signal fourth input signal D1, and the signal outputted from the D latch 1213 will be latched. Even if the slowly generated signal outputted from the first NOT gate 1211 appears later, it will not cause the signal outputted from the D latch 1213 to change, and the signal outputted from the D latch 1213 will remain at low level, thereby avoiding the above-mentioned situation that the control logic module controls the storage chip to exit the semi-sleep mode after controlling the storage chip to enter the low power consumption stage, and further improving the reliability of the storage device.

[0089] In addition, the fifth input signal E1 is an inverse signal of the fourth input signal D1, and the fifth input signal E1 is switched to a low-level signal, so that the output end of the RS latch 11 is switched to a high-level signal in the subsequent stage, that is, the signal output by the first NOT gate 1211 is maintained as a low-level signal, so that the selector 1222 can continuously maintain the second output signal B2 generated and output based on the second input signal B1, so that the control logic module can smoothly control the storage chip to enter the low-power consumption stage, so that when the RS latch 11 appears a metastable state due to temperature or other unexpected factors, the too slow signal output caused by the metastable state is ignored, so as to reduce the possibility of errors or failures of the storage device due to the signal output of the metastable state, and further improve the reliability of the storage device.

[0090] In an embodiment, in the asynchronous signal processing circuit as shown in Figure 2 , the output end of the selector 1222 can be connected to the input end of a driving enhancement module, and the second output signal B2 is output through the output end of the driving enhancement module.

[0091] In an embodiment, in the asynchronous signal processing circuit as shown in Figure 1 , the output end of the selector 1222 can be connected to the input end of a driving enhancement module, and the second output signal B2 is output through the output end of the driving enhancement module.

[0092] The output end of the first NOT gate 1211 can be connected to the input end of another driving enhancement module, and the first output signal A2 is output through the output end of the other driving enhancement module.

[0093] Specifically, the driving enhancement module can include a second NOT gate and a third NOT gate, the input end of the second NOT gate is the input end of the driving enhancement module, the output end of the second NOT gate is connected to the input end of the third NOT gate, and the output end of the third NOT gate is the output end of the driving enhancement module.

[0094] Based on the above manner, the driving capability of the asynchronous signal processing circuit can be effectively improved, so as to improve the reliability of the storage device.

[0095] The application also provides a storage device, referring to Figure 6 , Figure 6 is a structural schematic diagram of an embodiment of the storage device of the application, as shown in Figure 6 , the storage device 20 includes an asynchronous signal processing circuit 21, and the asynchronous signal processing circuit 21 can be the asynchronous signal processing circuit described in any one of the foregoing embodiments, which will not be described here.

[0096] Distinguishing from the prior art, in the technical solution of the application, the RS latch respectively receives the first input signal and the second input signal, the signal processing circuit is used for respectively receiving the signal output by the output end of the RS latch and the second input signal, the signal processing circuit is used for determining the timing relationship between the first input signal and the second input signal based on the received signal output by the output end of the RS latch, and in response to the first state of the received first input signal being earlier than the first state of the received second input signal, the first output signal with the first state and the second output signal with the first state are output, and the first state of the first output signal is earlier than the first state of the second output signal, and in response to none of the received first input signals being switched to the first state before the end of the first state of the received second input signal, the first output signal not switched to the first state and the second output signal with the first state are output. Based on the above-mentioned manner, after the signal processing circuit responds to the first state of the received first input signal being earlier than the first state of the received second input signal, even if the interval between the first input signal and the second input signal received by the RS latch is extremely short, the subsequent RS latch can still switch to the latch mode when the first input signal and the second input signal are received at the same time, and the output of the RS latch remains unchanged, therefore, in the case that the first input signal is received first and the second input signal is received after an extremely short interval, the signal processing circuit can continue to respond to the first state of the received first input signal being earlier than the first state of the received second input signal, and output the earlier first output signal and the later second output signal in turn, and in the case that none of the received first input signals is switched to the first state before the end of the first state of the received second input signal, even if the first input signal switched to the first state is received after the end of the first state of the second input signal, the situation can also be determined through the output of the first output signal not switched to the first state and the second output signal with the first state. In summary, the timing relationship between the first output signal and the second output signal output by the signal processing circuit can obtain the result of the timing judgment between the received first input signal and the second input signal, so that the asynchronous signal processing circuit can subsequently determine the sampling condition of the first input signal or the second input signal based on the current result of the timing judgment, and then perform the asynchronous exit operation based on the sampling condition. In further embodiments, it is more convenient to timely control and process the storage device where the asynchronous signal processing circuit is located, and the reliability of the storage device is improved.

[0097] In the description of the application, reference to terms such as "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" etc. is not necessarily a reference to the same embodiment or example. Such terms can mean different embodiments or examples. In addition, particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, the description can be in the general case not be limited to the same embodiment or example. Furthermore, a person skilled in the art can combine and combine different embodiments or examples described in the specification and the features of different embodiments or examples, without contradiction.

[0098] Furthermore, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as implying or implying a relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "multiple" is at least two, for example two, three, etc., unless otherwise explicitly specified.

[0099] Any process or method descriptions or descriptions in the flow charts or otherwise described herein can be understood as representing code modules, segments, or portions of code which include one or more executable instructions for performing specific logic functions or steps in the process, and the preferred embodiments of the application include additional implementations in which the functions are performed in a different order, in parallel, or in reverse order, according to the functions involved, as will be understood by those skilled in the art. The various embodiments of the application can be implemented in hardware, software, or a combination thereof.

[0100] The logic and / or steps represented in the flow diagrams and / or otherwise described herein, for example, can be embodied in non-transitory computer-readable media, executed by an instruction execution system, apparatus, or device, such as a personal computer, server, network device, or other computing / processing apparatuses that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In this regard, the "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can comprise any one of the following: electric connections (electronic devices), a portable computer diskette (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium upon which the program is printed, as the program can be electronically captured, via for instance an optical scanner, then compiled, interpreted, or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.

[0101] The above description is merely illustrative of the application, and is not intended to limit the scope of the application. Any equivalent structure or equivalent processes variant using the content of the specification and the drawings of the application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. An asynchronous signal processing circuit, characterized in that, include: An RS latch receives a first input signal and a second input signal, wherein the first input signal and the second input signal are asynchronous signals. A signal processing circuit is configured to receive the signal output from the output terminal of the RS latch and the second input signal, respectively, and determine the timing relationship between the first input signal and the second input signal based on the received signal output from the output terminal of the RS latch, and output a first output signal having the first state and a second output signal having the first state in response to the first state of the received first input signal being earlier than the first state of the received second input signal, such that the first state of the first output signal is earlier than the first state of the second output signal, and output a first output signal not switching to the first state and a second output signal having the first state in response to the first input signal not switching to the first state before the first state of the received second input signal ends; The asynchronous signal processing circuit is used to control the memory chip to exit the semi-sleep mode, and when the memory chip is in the semi-sleep mode, it controls the memory chip to cycle between the normal stage and the low-power stage. The first input signal switches to the first state when it receives an instruction to exit the semi-sleep mode; When the memory chip switches from the normal stage to the low-power stage, the second input signal first switches to the first state and then switches to the second state.

2. The asynchronous signal processing circuit according to claim 1, characterized in that, The signal processing circuit includes: A first circuit is connected to the output terminal of the RS latch. The first circuit is configured to output the first output signal in the first state in response to the inverse signal of the signal output by the output terminal of the RS latch being in the first state, and to output the first output signal in the second state in response to the inverse signal of the signal output by the output terminal of the RS latch being in the second state. The second circuit is connected to the output terminal of the RS latch. The second circuit is used to respond to the inverse signal of the signal output by the output terminal of the RS latch being in a first state, and then output the second output signal in the first state after the first output signal is in the first state. In response to the inverse signal of the signal output by the output terminal of the RS latch being in a second state, the second input signal is delayed to generate and output the second output signal in the first state.

3. The asynchronous signal processing circuit according to claim 2, characterized in that, The first circuit includes: The first NOT gate has its input connected to the output of the RS latch, and its output is used to output a first output signal.

4. The asynchronous signal processing circuit according to claim 3, characterized in that, The first state is a high-level state, and the second state is a low-level state; The second circuit includes: A first delay unit, the input of which is connected to the second input of the RS latch to receive the second input signal; A selector has a first input terminal for receiving a third input signal, which switches to a high level signal when the first output signal switches to a high level signal. The second input terminal of the selector is connected to the output terminal of the first delay unit. The selection terminal of the selector is connected to the output terminal of the first NOT gate. The selector is configured to connect its first input terminal and its output terminal in response to receiving a high level signal at the selection terminal, and to connect its second input terminal and its output terminal in response to receiving a low level signal at the selection terminal. The output terminal of the selector is used to output a second output signal.

5. The asynchronous signal processing circuit according to claim 4, characterized in that, The first circuit also includes: A second delay unit, the input of which is connected to the output of the first NOT gate; A D latch, wherein the input terminal of the D latch is connected to the output terminal of the second delay unit, the control terminal of the D latch is used to receive a fourth input signal, and the output terminal of the D latch is used to output the first output signal; The fourth input signal switches to a high-level signal when the first output signal is a low-level signal and the second output signal is a high-level signal, wherein the delay duration of the second delay unit is greater than the establishment duration for the fourth input signal to switch to a high-level signal; The third input terminal of the RS latch is used to receive the fifth input signal, wherein the fifth input signal and the fourth input signal are inverted signals. The third input terminal, the first input terminal, and the output terminal of the RS latch are located on the same NAND gate, and the third input terminal and the second input terminal of the RS latch are located on different NAND gates.

6. The asynchronous signal processing circuit according to claim 4 or 5, characterized in that, The delay duration of the first delayer is greater than the maximum setup time when the signal output from the output terminal of the RS latch switches from a high-level signal to a low-level signal.

7. The asynchronous signal processing circuit according to claim 1, characterized in that, The asynchronous signal processing circuit further includes: A control logic module, configured to control the memory chip to exit the semi-sleep mode in response to both the first output signal and the second output signal being in a first state; and The control logic module is further configured to control the memory chip to enter a low-power phase in response to the first output signal being in a second state and the second output signal being in a first state.

8. The asynchronous signal processing circuit according to claim 7, characterized in that, The second input signal switches to a second state after the memory chip is in a low-power phase, and remains in the second state after the memory chip switches from the low-power phase to the normal phase, and switches to a first state first and then to the second state when the memory chip switches from the normal phase to the low-power phase.

9. A storage device, characterized in that, Includes the asynchronous signal processing circuit as described in any one of claims 1 to 8.

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