Memory, control method thereof and memory system

Abstract

The embodiment of the invention provides a memory, a control method thereof and a memory system. The memory comprises a first circuit configured to receive an activation address, and determine a first row address according to a first rule and the activation address; the activation address is the address of the accessed storage line in the current access operation; a second circuit configured to receive the activation address and determine a second row address according to a second rule and the activation address; the determination mode of the second rule is different from the determination mode of the first rule; and a selection circuit coupled with the first circuit and the second circuit and configured to receive the first row address and the second row address and select one of the first row address and the second row address as an attack row address.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and relates to, but is not limited to, a memory and its control method, and a memory system. Background Art

[0002] A memory, such as a Dynamic Random Access Memory (DRAM), is a commonly used semiconductor device in a computer, and it can store data by storing charges in the capacitors of storage units. Since the charges stored in the capacitors will leak over time, the dynamic random access memory needs to periodically perform a normal Refresh operation. In some cases, in addition to the normal refresh, an additional row hammer refresh operation needs to be performed to prevent the occurrence of the Row Hammer Effect.

[0003] However, in the related art, there are still many problems to be solved in the process of performing the above refresh operations. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, including: a first circuit configured to receive an activation address and determine a first row address according to a first rule and the activation address; the activation address is the address of the storage row being accessed in the current access operation; a second circuit configured to receive the activation address and determine a second row address according to a second rule and the activation address; the determination method of the second rule is different from that of the first rule; a selection circuit coupled to both the first circuit and the second circuit, configured to receive the first row address and the second row address, and select one of the first row address and the second row address as the attacked row address.

[0005] In some embodiments, the first circuit includes an address processor; the address processor is used to store the addresses of multiple first storage rows and count the number of accesses to each of the first storage rows; the multiple first storage rows are multiple storage rows determined according to the number of accesses before the current access operation; the number of addresses of the first storage rows stored in the address memory is a fixed value; the second circuit includes a matching unit, and the matching unit is used to store the addresses of multiple second storage rows; the second storage rows are at least part of the storage rows accessed before the current access operation; the number of addresses of the second storage rows stored in the matching unit is a variable value.

[0006] In some embodiments, the method for determining the second rule includes: performing blurring processing on the activation address, and sequentially matching the blurred activation address with the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the fuzzy matching result shows a successful match, determining the activation address as the second row address.

[0007] In some embodiments, both the activation address and the addresses of the second memory rows include a first data bit and a second data bit arranged in sequence; sequentially matching the first data bit of the activation address with the first data bits of the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the first data bit of the activation address is the same as the first data bit of the address of at least one second memory row among all second memory rows, the fuzzy matching result shows a successful match; when the first data bit of the activation address is not the same as the first data bits of the addresses of all second memory rows, the fuzzy matching result shows a failed match.

[0008] In some embodiments, when the fuzzy matching result shows a failed match, determining the second row address as an empty address; and storing the activation address as the address of a new second memory row in the matching unit.

[0009] In some embodiments, the method for determining the first rule includes: sequentially comparing the activation address with the addresses of all first memory rows in the address processor; wherein, when the activation address matches the address of one of all first memory rows, increasing the count value of the first memory row that matches in the address processor by an increment value; and after increasing by one increment value, comparing the current count values of all first memory rows in the address processor, and determining the address of the first memory row corresponding to the current maximum count value as the first row address.

[0010] In some embodiments, the memory further includes: an address conversion circuit and a refresh circuit; wherein, the address conversion circuit is connected to the selection circuit and is configured to: receive the attacked row address; and determine the victim row address according to the attacked row address; the victim rows are at least one memory row above and below the attacked row in the physical position; the refresh circuit, connected to the address conversion circuit, is configured to: receive the victim row address, and perform a refresh operation on the victim row.

[0011] In some embodiments, the memory further includes: a control circuit; the control circuit is respectively connected to the first circuit, the second circuit, the selection circuit, and the refresh circuit, and is configured to: receive a refresh command, split the refresh command into a first control signal and a second control signal, and output the first control signal and / or the second control signal; wherein, the timing of the first control signal and the second control signal is alternately set at intervals.

[0012] In some embodiments, the control circuit includes: a first refresh control circuit and a second refresh control circuit; wherein, the first refresh control circuit is configured to: receive the refresh command and output a row hammer refresh signal based on the refresh command; the second refresh control circuit is connected to the first refresh control circuit and is configured to: receive the row hammer refresh signal, split the row hammer refresh signal into the first control signal and the second control signal; and output the first control signal to the first circuit, output the second control signal to the second circuit, output the first control signal or the second control signal to the selection circuit, and output the first control signal or the second control signal to the refresh circuit.

[0013] In some embodiments, the first circuit determines a first row address based on the first control signal according to a first rule and the activation address; the second circuit determines a second row address based on the second control signal according to a second rule and the activation address; the selection circuit selects one of the first row address and the second row address as the attack row address based on the first control signal or the second control signal; the refresh circuit performs a refresh operation on the victim row based on the first control signal or the second control signal.

[0014] In some embodiments, the first row address is the same as or different from the second row address.

[0015] The embodiments of the present disclosure also provide a memory system, including one or more memories as described in the above embodiments of the present disclosure; and a memory controller, coupled to the memory, for controlling the memory.

[0016] Embodiments of the present disclosure also provide a control method for a memory. The memory includes a first circuit, a second circuit, and a selection circuit. The control method includes: the first circuit receives an activation address and determines a first row address according to a first rule and the activation address. The activation address is the address of the memory row being accessed in the current access operation. The second circuit receives the activation address and determines a second row address according to a second rule and the activation address. The determination method of the second rule is different from that of the first rule. The selection circuit receives the first row address and the second row address and selects one of the first row address and the second row address as the attack row address.

[0017] In some embodiments, the first circuit includes an address processor; the second circuit includes a matching unit. The operation method includes: obtaining the addresses of a plurality of first memory rows and counting the number of accesses to each of the plurality of first memory rows; and storing the addresses of the plurality of first memory rows and the counting results in the address processor. The first memory rows are a plurality of memory rows determined according to the number of accesses before the current access operation. The number of addresses of the first memory rows stored in the address memory is a fixed value. And obtaining the addresses of a plurality of second memory rows and storing the addresses of the plurality of second memory rows in the matching unit. The second memory rows are at least some of the memory rows accessed before the current access operation. The number of addresses of the second memory rows stored in the matching unit is a variable value.

[0018] In some embodiments, determining the second row address according to the second rule and the activation address includes: performing fuzzy processing on the activation address, and sequentially matching the fuzzily processed activation address with the addresses of all the second memory rows in the matching unit to obtain a fuzzy matching result. When the fuzzy matching result shows a successful match, the activation address is determined as the second row address.

[0019] In some embodiments, both the activation address and the address of the second memory row include a first data bit and a second data bit arranged in sequence; the process of blurring the activation address and then matching the blurred activation address with the addresses of all the second memory rows in the matching unit one by one to obtain the result of the fuzzy matching includes: matching the first data bit of the activation address with the first data bits of the addresses of all the second memory rows in the matching unit one by one to obtain the result of the fuzzy matching; wherein, when the first data bit of the activation address is the same as the first data bit of the address of at least one second memory row among all the second memory rows, the result of the fuzzy matching is displayed as a successful match; when the first data bit of the activation address is not the same as the first data bits of the addresses of all the second memory rows, the result of the fuzzy matching is displayed as a failed match.

[0020] In some embodiments, the control method further includes: when the result of the fuzzy matching is displayed as a failed match, determining that the address of the second row is an empty address; and storing the activation address as the address of a new second memory row in the matching unit.

[0021] In some embodiments, determining the address of the first row according to the first rule and the activation address includes: comparing the activation address with the addresses of all the first memory rows in the address processor one by one; wherein, when the activation address matches the address of one of the first memory rows, increasing the count value of the first memory row in the address processor that matches by an increment value; and after increasing by one increment value, comparing the current count values of all the first memory rows in the address processor and determining the address of the first memory row corresponding to the current maximum count value as the address of the first row.

[0022] In some embodiments, the memory further includes: an address conversion circuit and a refresh circuit; wherein, the control method further includes: the address conversion circuit receiving the attacked row address; and determining the victim row address according to the attacked row address; the victim row is at least one memory row physically located above and below the attacked row; the refresh circuit receiving the victim row address and performing a refresh operation on the victim row.

[0023] In some embodiments, the memory further includes: a control circuit; wherein, the control method further includes: the control circuit receiving a refresh command, splitting the refresh command into a first control signal and a second control signal, and outputting the first control signal and / or the second control signal; wherein, the timing of the first control signal and the second control signal is alternately set at intervals.

[0024] In some embodiments, the control circuit includes: a first refresh control circuit and a second refresh control circuit; the control circuit receives the refresh command, splits the refresh command into a first control signal and a second control signal, and outputs the first control signal and / or the second control signal, including: the first refresh control circuit receives the refresh command and outputs a row hammer refresh signal based on the refresh command; the second refresh control circuit receives the row hammer refresh signal and splits the row hammer refresh signal into the first control signal and the second control signal; the control method further includes: outputting the first control signal to the first circuit, outputting the second control signal to the second circuit, outputting the first control signal or the second control signal to the selection circuit, and outputting the first control signal or the second control signal to the refresh circuit.

[0025] In some embodiments, the first circuit determines a first row address based on the first control signal, according to a first rule and the activation address; the second circuit determines a second row address based on the second control signal, according to a second rule and the activation address; the selection circuit selects one of the first row address and the second row address as the attack row address based on the first control signal or the second control signal; the refresh circuit performs a refresh operation on the victim row based on the first control signal or the second control signal.

[0026] The memory provided in the embodiments of the present disclosure includes a first circuit configured to receive an activation address and determine a first row address according to a first rule and the activation address; the activation address is the address of the storage row being accessed in the current access operation; a second circuit configured to receive the activation address and determine a second row address according to a second rule and the activation address; the determination method of the second rule is different from that of the first rule; a selection circuit coupled to both the first circuit and the second circuit, configured to receive the first row address and the second row address and select one of the first row address and the second row address as the attack row address. In the embodiments of the present disclosure, the activation address is judged by the first circuit in combination with the first rule, and it is determined whether the activation address is an attack row address according to the judgment result; the activation address is judged again by the second circuit in combination with the second rule to determine again whether the activation address is an attack row address, preventing the activation address from being determined as a non-attack row address when it does not meet the judgment criteria of the first rule. In this way, the probability that the activation address is determined as a non-attack row address can be reduced, the escaped attack rows can be reduced, and thus the row hammer effect on the adjacent rows of the accessed row can be reduced. Description of the Drawings

[0027] Figure 1Block diagram of an exemplary system with a memory provided in an embodiment of the present disclosure;

[0028] Figure 2 Schematic diagram of the row hammer effect provided in an embodiment of the present disclosure;

[0029] Figure 3 Schematic diagram of the composition structure of the memory provided in an embodiment of the present disclosure;

[0030] Figure 4 Block diagram of the row hammer refresh circuit provided in an embodiment of the present disclosure;

[0031] Figure 5 Block diagram of the first circuit provided in an embodiment of the present disclosure;

[0032] Figure 6 Block diagram of the second circuit provided in an embodiment of the present disclosure;

[0033] Figure 7 Schematic diagram of the result of the address fuzzy matching of multiple second memory rows provided in an embodiment of the present disclosure;

[0034] Figure 8a Timing diagram of the row hammer refresh signal, the first control signal, and the second control signal provided in an embodiment of the present disclosure;

[0035] Figure 8b Schematic diagram of the generation method of the first control signal and the second control signal provided in an embodiment of the present disclosure;

[0036] Figure 8c Corresponding timing schematic diagram of the row hammer refresh signal, the first control signal, the second control signal, and the Flag signal provided in an embodiment of the present disclosure;

[0037] Figure 9 Schematic diagram of the operation process of the second circuit provided in an embodiment of the present disclosure;

[0038] Figure 10 Schematic diagram of the implementation process of the control method of the memory provided in an embodiment of the present disclosure.

[0039] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed implementation manners

[0040] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] The present disclosure will be described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present disclosure.

[0042] In the embodiments of the present disclosure, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence.

[0043] Figure 1 is a block diagram of an exemplary system with a memory provided by the embodiments of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1 shown, the system 100 can include a host 110 and a memory system 120, and the memory system 120 has one or more memories 130 and a memory controller 140. The host 110 can be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host 110 can be configured to send data to the memory 130 or receive data from the memory 130.

[0044] In some embodiments, the memory controller 140 is coupled to the memory 130 and the host 110 and is configured to control the memory 130. The memory controller 140 may operate the memory 130 by providing a combination of various control signals CMD and address signals ADDR. For example, the memory controller 140 may control the memory 130 to perform a read operation via a read command RD. The memory controller 140 may control the memory 130 to perform a write operation via a write command WT. The memory controller 140 may also control the memory 130 to perform a refresh operation via a refresh command REF, etc. In some specific embodiments, the memory controller 140 may provide various signals to control the memory to perform access operations (such as writing and reading). For example, an activate command ACT, a read command RD, and a write command WT are used to access the memory 130. The activate command ACT is a row access command. The memory controller 140 issues the activate command ACT and the row address signal simultaneously. The memory 130 synchronously receives the activate command ACT and the row address signal and enables the word line of the memory cell array according to the row address signal.

[0045] In some embodiments, the memory controller 140 may also provide a read command RD to control the memory 130 to perform a read operation, or provide a write command WT to control the memory 130 to perform a write operation. Among them, the column address signal is issued simultaneously with the read command / write command. Exemplarily, the memory 130 may synchronously receive the read command RD and the column address signal and select the bit line of the memory cell array according to the column address signal, so as to perform a read operation on the data in the memory cell located at the intersection of the enabled word line and the selected bit line. Exemplarily, the memory 130 may synchronously receive the write command WT and the column address signal and select the bit line of the memory cell array according to the column address signal. The memory 130 may receive the data sent from the memory controller 140 during the write operation and may store the received data in the memory cell located at the intersection of the enabled word line and the selected bit line.

[0046] In some embodiments, the memory controller 140 may provide a refresh command REF to control the memory 130 to perform a refresh operation. Exemplarily, the memory controller 140 provides the refresh command REF to the memory 130 at a fixed period to perform a normal refresh operation. One refresh command REF is only valid for one memory row, and the memory 130 may sequentially perform refresh operations on all memory rows according to the refresh command REF. In some embodiments, when the memory 130 performs a refresh, it does not require external provision of row address information, and the memory can automatically generate row addresses sequentially internally.

[0047] Here, the memory 130 may include all types of memories that perform refresh operations to maintain data stored in the memory cells. For example, the memory 130 may include a dynamic random access memory (DRAM). The memory 130 may include a memory cell array and peripheral circuits coupled to the memory cell array. The memory cell array may be a DRAM memory cell array. Each DRAM memory cell may include a transistor and a capacitor. The gate of the transistor is connected to a word line, the source is connected to a bit line, and the drain is connected to the capacitor. The memory cell array includes multiple memory rows. The memory cells of each memory row are coupled to the same word line, and the word line is coupled to a row decoder. The column decoder is coupled to multiple memory columns through multiple bit lines respectively. The peripheral circuits may be coupled to the memory cell array through the word lines and bit lines. The peripheral circuits can control the turn-on and turn-off of the transistor by controlling the word line voltage, so as to read the data information stored in the capacitor through the bit line or write the data information into the capacitor.

[0048] It should be noted that in a DRAM, if a certain memory row is repeatedly accessed during the refresh period, it will cause the charge leakage of the memory cells in the memory rows physically adjacent to that memory row. This is the row hammer effect. Among them, the memory row that is repeatedly accessed is called the attacking row. The memory rows physically adjacent to the attacking row are called the victim rows. The victim rows have a charge loss problem due to the repeated access of the attacking row. If the number of accesses to the attacking row reaches a certain amount, the row hammer effect may cause data corruption in the victim rows. Figure 2 is a schematic diagram of the row hammer effect. As Figure 2 shown, the victim rows may be the two upper and lower memory rows (Row+1 and Row-1) physically adjacent to the attacking row (such as the Active Row), or the four upper and lower memory rows physically adjacent to the attacking row (for example, Row+2, Row+1, Row-1, and Row-2). The present disclosure does not make a limitation.

[0049] A relatively effective method to solve the row hammer effect is to perform a row hammer refresh operation, that is, target row refresh (TRR). Target row refresh means finding the attacking row and refreshing the victim rows adjacent to it. By refreshing the victim rows, the data in the memory cells of the victim rows is retained. Target row refresh can also be understood as victim row refresh, that is, performing a refresh operation on the victim rows. In some embodiments, the memory may track the row address signals synchronized with the activation commands sent by the memory controller, so as to obtain the number of accesses to each memory row, and then can determine the memory row with the most accesses within a period of time. This memory row with the most accesses is the attacking row. The memory can refresh the victim rows of the attacking row, thereby weakening the adverse effects of the row hammer effect.

[0050] Exemplarily, referring to Figure 3 , Figure 3 is a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 3 shows Figure 1 an example of the memory in Figure 3 As shown, the memory may include a memory cell array 131 and a peripheral circuit. Among them, the peripheral circuit may include a control logic circuit 132, an address buffer 133, a row hammer refresh circuit 134, a row decoder 135, a column decoder 136, an I / O gating circuit 137, a data I / O buffer 138, etc.

[0051] The address buffer 133 may receive an address signal ADDR from the memory controller 140 or the host 110, such as a row address signal and a column address signal, etc. The address buffer 133 may provide the received column address signal to the column decoder 136, and provide the received row address signal to the row decoder 135 and the row hammer refresh circuit 134. The address buffer 133 receiving the row address signal is synchronous with the control logic circuit 132 receiving the activation command ACT.

[0052] The control logic circuit 132 may receive various commands CMD from the memory controller 140 or the host 110 and generate various control signals for controlling the operation of the memory 130. Specifically, the command decoder 1321 in the control logic circuit 132 is used to receive various commands CMD and generate various control signals. The control logic circuit 132 may read data from or write data to the memory cell array 131 by using the control signals, or perform other operations. Exemplarily, the control logic circuit 132 may receive an activation command ACT to control the row decoder 135 to activate the memory row indicated by the row address signal. The control logic circuit 132 may receive a refresh command REF to control the row hammer refresh circuit 134 to perform a refresh operation on a certain memory row. Although Figure 3 the control logic circuit 132 and the address buffer 133 in Figure 3 are shown as separate components, the control logic circuit 132 and the address buffer 133 may also be an integrated component. Although

[0053] The row decoder 135 can decode the row address signal received from the address buffer 133 to select a word line WL corresponding to the accessed row address XADD from multiple word lines WL, and can connect the selected word line WL to the word line driver. The column decoder 136 can select a specific bit line BL from multiple bit lines BL connecting the memory cell array 131. The column decoder 136 can select one bit line or multiple bit lines BL in burst mode.

[0054] The data I / O buffer 138 can receive data from the host 110 or the memory controller 140 or transmit data to the host 110 or the memory controller 140. The I / O gating circuit 137 is connected to the data I / O buffer 138. The I / O gating circuit 137 can receive the data from the data I / O buffer 138 and write it into the memory cell array 131, or read the data from the memory cell array 131 and transmit it to the data I / O buffer 138.

[0055] In the embodiments of the present disclosure, the row hammer refresh circuit 134 can perform a normal refresh operation on the memory row or perform an additional row hammer refresh operation on the memory row. Refer to Figure 4 , when the row hammer refresh circuit 134 performs a normal refresh, it does not require external provision of row address information. It can automatically generate row addresses in sequence using the normal refresh address generator 2063. This row address is the victim row address, such as the normal refresh address. The refresh circuit 205 performs a refresh operation on the victim row, such as the memory row corresponding to the normal refresh address, at a fixed period based on the refresh command REF.

[0056] Next, in combination with Figure 4 , Figure 5 , Figure 6 , a detailed description of the row hammer refresh operation performed by the row hammer refresh circuit 134 will be given. Figure 4 is a block diagram of the row hammer refresh circuit; Figure 5 is a block diagram of the first circuit; Figure 6 is a block diagram of the second circuit.

[0057] Refer to Figure 4, the row hammer refresh circuit 134 further includes a first circuit 201 and a second circuit 202. Among them, the first circuit 201 can monitor the number of times a memory row is accessed and detect the row address of an attacked row that is frequently accessed during the refresh period. Exemplarily, the first circuit 201 is connected to the address buffer 133, and is used to receive the accessed row address XADD provided by the address buffer 133, count the number of times each memory row is accessed, determine the memory row with the most accessed times as the attacked row, and determine the row address to be refreshed of the victim row based on the attacked row. The first circuit 201 can respond to the refresh command REF to perform a refresh operation on the row address to be refreshed, so as to retain the data in the memory cells of the victim row (i.e., the adjacent memory row of the attacked row), thereby weakening the adverse effects caused by the row hammer effect.

[0058] Reference Figure 5 , the first circuit 201 may include a sampling circuit 2011 and an address processor; the address processor includes a plurality of address registers 2012 and a plurality of counters 2013. The plurality of address registers 2012 correspond to the plurality of counters 2013 one by one. Each address register is used to store a first memory row address, and the counter corresponding to the address register is used to record the number of times the first memory row is accessed. Here, the plurality of first memory rows are a plurality of memory rows determined according to the number of times accessed before the current access operation. Exemplarily, the sampling circuit 2011 samples the accessed row address XADD at a certain timing when activating the sampling signal generated by the sample generator, and determines the several memory rows with the most accessed times before the current access operation as the plurality of first memory rows; then, supplies the addresses of the plurality of sampled first memory rows to the address processor; the address processor stores the addresses of the plurality of first memory rows in the plurality of address registers 2012, where the plurality of counters 2013 are used to record the number of times the plurality of first memory rows are accessed.

[0059] Here, the number of address registers 2012 in the address memory is a fixed value. Therefore, the number of addresses of the first memory rows stored in the address memory is a fixed value. Exemplarily, the number of address registers is 6, and the number of counters is 6; then the sampling circuit samples the addresses of the plurality of memory rows before the current access operation, and stores the addresses of the first 6 memory rows with the most accessed times before the current access operation as the addresses of the first memory rows in the address registers 2012.

[0060] When performing the current access operation, the first row address is determined using the first rule. Specifically, the address of the memory row being accessed in the current access operation, i.e., the activation address, is compared one by one with the addresses of all the first memory rows in the address processor. When the activation address matches the address of one of the first memory rows, the count value of the first memory row in the address processor that matches is incremented by an increment value. After incrementing by one increment value, the current count values of all the first memory rows in the address processor are compared, and the address of the first memory row corresponding to the current maximum count value is determined as the first row address.

[0061] In some embodiments, referring to Figure 5 , the first circuit further includes a comparator 2014. When performing the current access operation, the activation address is compared one by one with the addresses of the first memory rows in a plurality of address registers. When the activation address matches the address of one of the first memory rows, it indicates that the memory row being accessed in the current access operation has been frequently accessed before the current access operation. At this time, the count value of the counter of the first memory row that matches in the address processor is incremented by 1. Then, the count values of all the counters in the address processor are compared. The address of the first memory row with the largest count value among the plurality of counters is determined as the first row address.

[0062] The second circuit 202 is connected to the address buffer 133 and is used to receive the accessed row address XADD provided by the address buffer 133. Based on the second rule, it detects whether the memory row being accessed in the current access operation has been accessed before the current access operation. If it has been accessed, it indicates that the accessed memory row has been accessed more frequently. The second circuit 202 can respond to the refresh command REF to perform a refresh operation on the victim row (i.e., the adjacent memory row of the memory row being accessed in the current access operation) to retain the data in the memory cells of the victim row, thereby reducing the adverse effects caused by the row hammer effect.

[0063] Referring to Figure 6, the second circuit 202 may include a sampling circuit 2021, a matching unit 2022, a comparison circuit 2023, and a latch 2024; the matching unit 2022 may be configured to store addresses of multiple second memory rows; the second memory rows are at least some of the memory rows accessed before the current access operation; the sampling circuit 2021 may be configured to sample all accessed row addresses XADD within a certain time sequence, and the comparison circuit 2023 may be configured to match one by one the address (activation address) of the currently accessed row obtained by sampling with the addresses of the multiple second memory rows stored in the matching unit 2022. Here, the matching method may specifically include: performing fuzzy processing on the activation address, and matching the fuzzy processed activation address with the addresses of all second memory rows in the matching unit one by one to obtain a fuzzy matching result; when the fuzzy matching result shows a successful match, it indicates that the memory row accessed in the current access operation has been accessed in a previous access operation. At this time, the activation address may be determined as the second row address. In some embodiments, the number of successful matches may also be limited. In other words, when the number of access times corresponding to the activation address reaches a preset threshold T, the activation address is output as the second row address. The preset threshold T may be selected and set according to the implementation situation. It should be noted that the sampling circuit 2021 in the second circuit 202 may be the same sampling circuit as the sampling circuit 2011 in the first circuit 201, or may be a different sampling circuit, which is not limited in this disclosure.

[0064] The specific matching process will be described in detail below.

[0065] In some embodiments, both the activation address and the addresses of the second memory rows include a first data bit and a second data bit arranged in sequence; the first data bits of the activation address are matched one by one with the first data bits of the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the first data bit of the activation address is the same as the first data bit of the address of at least one second memory row among all second memory rows, the fuzzy matching result shows a successful match; when the first data bit of the activation address is not the same as the first data bits of the addresses of all second memory rows, the fuzzy matching result shows a failed match.

[0066] Refer to Figure 7 , Figure 7Shows the results of the address fuzzy matching of multiple second storage rows; Exemplarily, both the activation address and the address of the second storage row are XXYY (such as 0111, 0110, 0101, 0100, etc.), Exemplarily, the first data bit is XX and the second data bit is YY; Exemplarily, the activation address is 01ZZ (ZZ can be any one of 11, 10, 01, 00); The addresses of multiple second storage rows are 1000, 0111, 0110, 0101, 0100, and 0011 respectively. Perform one-by-one matching of 01ZZ with 1000, 0111, 0110, 0101, 0100, and 0011. The first data bits of 01ZZ and 0111, 0110, 0101, 0100 are the same, indicating a successful match; In some other embodiments, during the matching process, 0111, 0110, 0101, 0100 can be recognized as the same fuzzy address, and the first data bit of this same fuzzy address is the same as the first data bit of the activation address, then 0111, 0110, 0101, 0100 match successfully with the activation address 01ZZ. On the contrary, the first data of 01ZZ and 1000, 0011 are not the same, indicating a failed match.

[0067] Here, when the result of the fuzzy matching shows a successful match, determine that the activation address is the second row address. When the result of the fuzzy matching shows a failed match, determine that the second row address is an empty address; and store the activation address as the address of a new second storage row in the matching unit; In other words, the number of addresses of the second storage row stored in the matching unit is a variable value; It can determine whether to increase the number of addresses of the second storage row in the matching unit according to the result of the fuzzy matching. It should be noted that by using the fuzzy matching method to determine the second row address, the matching success rate between the activation address and the address of the second storage row can be increased, and the probability of determining the activation address as the second row address can be increased.

[0068] In some embodiments, the first row address and the second row address can be the same or different.

[0069] Reference Figure 6 , Based on the result of the fuzzy matching, set the Flag signal output by the comparison circuit; Among them, when the result of the fuzzy matching shows a successful match, set the Flag signal to 1. When the result of the fuzzy matching shows a failed match, set the Flag signal to 0. In addition, the latch 2024 can be used to store the second row address; Among them, after the second row address is updated, the address stored in the latch 2024 is updated accordingly.

[0070] Return reference Figure 4, after the first row address and the second row address are sent to the selection circuit 203, the selection circuit 203 determines the attack row address based on the refresh command. Here, the attack row address is one of the first row address and the second row address.

[0071] Reference Figure 4 , the row hammer refresh circuit 134 further includes a control circuit 206, and the control circuit 206 is respectively connected to the first circuit 201, the second circuit 202, the selection circuit 203, and the refresh circuit 205, and is configured to: receive the refresh command, split the refresh command into a first control signal and a second control signal, and output the first control signal and / or the second control signal.

[0072] Here, the control circuit includes: a first refresh control circuit 2061 and a second refresh control circuit 2062; wherein, the first refresh control circuit 2061 is configured to: receive the refresh command and output a row hammer refresh signal RHR based on the refresh command. The second refresh control circuit 2062 is connected to the first refresh control circuit 2061 and is configured to: receive the row hammer refresh signal RHR and split the row hammer refresh signal RHR into a first control signal RHR1 and a second control signal RHR2.

[0073] Reference Figure 8a , Figure 8b , Figure 8c , Figure 8a is a timing diagram of the row hammer refresh signal, the first control signal, and the second control signal; Figure 8b is a schematic diagram of the generation method of the first control signal RHR1 and the second control signal RHR2; Figure 8c is a corresponding timing schematic diagram of the row hammer refresh signal RHR, the first control signal RHR1, the second control signal RHR2, and the Flag signal. Reference Figure 8a , the timing alternating interval between the first control signal RHR1 and the second control signal RHR2 is set; exemplarily, the timing ratio of the first control signal RHR1 to the second control signal RHR2 is 2:1; it should be understood that the timing ratio of the first control signal RHR1 to the second control signal RHR2 can be selected and set according to actual requirements. Reference Figure 8b , in the embodiments of the present disclosure, the row hammer refresh signal RHR can be split into a first control signal RHR1 and a second control signal RHR2 through a combination of circuits such as a pulse counter, an AND gate circuit, and a NOT gate circuit. The related technologies of the pulse counter, the AND gate circuit, and the NOT gate circuit are relatively mature and will not be elaborated here. Reference Figure 8c, the second circuit 202 samples the address of the accessed row when the sampling signal (Sample) is 1 (high level), and sets the Flag signal to 1 (high level) when the match is successful. The Flag signal and the row hammer refresh signal RHR together determine the first control signal RHR1. Then, according to the count value of the pulse counter, the second control signal RHR2 is determined; the falling edge of the second control signal RHR2 is synchronized with the falling edge of the Flag signal. It should be noted that for the signal shown in the dashed box in Figure 8c , when the Flag signal is 0 and the second control signal RHR2 is 1, the second control signal RHR2 is invalid, and the first control signal RHR1 corresponding to the timing is effective.

[0074] The second refresh control circuit 2062 is configured to output the first control signal RHR1 to the first circuit 201, and to output the second control signal RHR2 to the second circuit 202, output the first control signal RHR1 or the second control signal RHR2 to the selection circuit 203, and output the first control signal RHR1 or the second control signal RHR2 to the refresh circuit. After the first control signal RHR1 is output to the first circuit 201, the first circuit 201 operates; after the second control signal RHR2 is output to the second circuit 202, the second circuit 202 operates. Similarly, the selection circuit 203 selects the first row address as the attack row address based on the first control signal RHR1; selects the second row address as the attack row address based on the second control signal RHR2.

[0075] Reference Figure 4 , the row hammer refresh circuit 134 further includes an address conversion circuit 204 and a refresh circuit 205; wherein, the address conversion circuit 204 is connected to the selection circuit 203 and is configured to: receive the attack row address; and determine the victim row address according to the attack row address; the physical location of the victim row is at least one memory row above and below the attack row. The refresh circuit 205, connected to the address conversion circuit 204, is configured to: receive the victim row address and perform a refresh operation on the victim row.

[0076] It should be noted that the first circuit 201 determines the first row address based on the first control signal RHR1 according to the first rule and the activation address; the second circuit 202 determines the second row address based on the second control signal RHR2 according to the second rule and the activation address; the selection circuit 203 selects one of the first row address and the second row address as the attack row address based on the first control signal RHR1 or the second control signal RHR2; the refresh circuit 205 performs a refresh operation on the victim row based on the first control signal RHR1 or the second control signal RHR2.

[0077] In the embodiments of the present disclosure, the activation address can be judged by the first circuit in combination with the first rule, and whether the activation address is an attack row address can be determined according to the judgment result; the activation address can be judged again by the second circuit in combination with the second rule to determine again whether the activation address is an attack row address, so as to prevent the activation address from being determined as a non-attack row address when it does not meet the judgment criteria of the first rule. In this way, the probability that the activation address is determined as a non-attack row address can be reduced, the escaped attack rows can be reduced, and thus the row hammer effect on the adjacent rows of the accessed row can be reduced.

[0078] Based on the above row hammer refresh circuit, the following will describe in detail the process of performing the above operation of the second circuit in the embodiments of the present disclosure; wherein, Figure 9 will be used to describe in detail the process of performing the above operation of the second circuit in the embodiments of the present disclosure; wherein, Figure 9 is a schematic diagram of the operation process of the second circuit shown in the embodiments of the present disclosure.

[0079] As Figure 9 shown, execute 901 to start the current access operation. Execute 902, and the address of the accessed row arrives. Execute 903, sample the accessed row address XADD based on the activation command of the current access operation, and determine that the address of the current accessed row is obtained by sampling. If the activation address is not obtained, execute 908, and the row hammer refresh operation performed by the second circuit ends. If the activation address is obtained, execute 904, perform fuzzy processing on the activation address, and match the fuzzily processed activation address with the addresses of all the second storage rows in the matching unit one by one to obtain the result of fuzzy matching. When the result of fuzzy matching shows a successful match, determine that the activation address is the second row address. When the result of fuzzy matching shows a failed match, determine that the second row address is an empty address.

[0080] Execute 905 to determine whether the number of successful matches has reached the preset threshold T; if the number of successful matches has reached the preset threshold T, execute 906, set the Flag signal to 1, and output the activation address as the second row address; and execute 908, and the row hammer refresh operation performed by the second circuit ends. If the number of successful matches has not reached the preset threshold T, execute 907, and store the activation address as the address of a new second storage row in the matching unit.

[0081] Based on the above memory, the embodiments of the present disclosure further provide a memory system, including one or more memories as described in the above embodiments of the present disclosure; and a memory controller, coupled to the memory, for controlling the memory.

[0082] Based on the above memory, the embodiments of the present disclosure further provide a control method for a memory, referring to Figure 10 Figure 10Schematic diagram of the implementation process of a control method for a memory provided in an embodiment of the present disclosure; the control method includes:

[0083] 1001: The first circuit in the memory receives the activation address and determines the first row address according to the first rule and the activation address; the activation address is the address of the memory row being accessed in the current access operation.

[0084] 1002: The second circuit in the memory receives the activation address and determines the second row address according to the second rule and the activation address; the determination method of the second rule is different from that of the first rule.

[0085] 1003: The selection circuit in the memory receives the first row address and the second row address and selects one of the first row address and the second row address as the attacked row address.

[0086] In some embodiments, the first circuit includes an address processor; the second circuit includes a matching unit; the operation method includes: obtaining the addresses of multiple first memory rows and counting the number of accesses to each of the multiple first memory rows; storing the addresses of the multiple first memory rows and the result of the count in the address processor; the first memory rows are multiple memory rows determined according to the number of accesses before the current access operation; the number of addresses of the first memory rows stored in the address memory is a fixed value; and

[0087] obtaining the addresses of multiple second memory rows and storing the addresses of the multiple second memory rows in the matching unit; the second memory rows are at least part of the memory rows accessed before the current access operation; the number of addresses of the second memory rows stored in the matching unit is a variable value.

[0088] In some embodiments, the determining the second row address according to the second rule and the activation address includes: performing fuzzy processing on the activation address, and performing one-by-one matching between the fuzzily processed activation address and the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the fuzzy matching result shows a successful match, it is determined that the activation address is the second row address.

[0089] In some embodiments, both the activation address and the address of the second memory row include a first data bit and a second data bit arranged in sequence; the step of performing fuzzy processing on the activation address and then matching the fuzzy-processed activation address with the addresses of all second memory rows in the matching unit to obtain the result of the fuzzy match includes: matching the first data bit of the activation address with the first data bits of the addresses of all second memory rows in the matching unit one by one to obtain the result of the fuzzy match; wherein, when the first data bit of the activation address is the same as the first data bit of the address of at least one second memory row among all the second memory rows, the result of the fuzzy match is displayed as a successful match; when the first data bit of the activation address is not the same as the first data bits of the addresses of all the second memory rows, the result of the fuzzy match is displayed as a failed match.

[0090] In some embodiments, the control method further includes: when the result of the fuzzy match is displayed as a failed match, determining that the second row address is an empty address; and storing the activation address as the address of a new second memory row in the matching unit.

[0091] In some embodiments, determining the first row address according to the first rule and the activation address includes: comparing the activation address with the addresses of all first memory rows in the address processor one by one; wherein, when the activation address matches the address of one of the first memory rows among all the first memory rows, increasing the count value of the first memory row in the address processor that matches by an increment value; and after increasing by one increment value, comparing the current count values of all first memory rows in the address processor and determining the address of the first memory row corresponding to the current maximum count value as the first row address.

[0092] In some embodiments, the memory further includes: an address conversion circuit and a refresh circuit; wherein, the control method further includes: the address conversion circuit receiving the attacked row address; and determining the victim row address according to the attacked row address; the victim rows are at least one memory row physically located above and below the attacked row; the refresh circuit receiving the victim row address and performing a refresh operation on the victim rows.

[0093] In some embodiments, the memory further includes: a control circuit; wherein, the control method further includes: the control circuit receiving a refresh command, splitting the refresh command into a first control signal and a second control signal, and outputting the first control signal and / or the second control signal; wherein, the timing of the first control signal and the second control signal is alternately set at intervals.

[0094] In some embodiments, the control circuit includes: a first refresh control circuit and a second refresh control circuit; the control circuit receives the refresh command, splits the refresh command into a first control signal and a second control signal, and outputs the first control signal and / or the second control signal, including: the first refresh control circuit receives the refresh command and outputs a row hammer refresh signal based on the refresh command; the second refresh control circuit receives the row hammer refresh signal and splits the row hammer refresh signal into the first control signal and the second control signal; the control method further includes: outputting the first control signal to the first circuit, outputting the second control signal to the second circuit, outputting the first control signal or the second control signal to the selection circuit, and outputting the first control signal or the second control signal to the refresh circuit.

[0095] In some embodiments, the first circuit determines a first row address based on the first control signal, according to a first rule and the activation address; the second circuit determines a second row address based on the second control signal, according to a second rule and the activation address; the selection circuit selects one of the first row address and the second row address as the attack row address based on the first control signal or the second control signal; the refresh circuit performs a refresh operation on the victim row based on the first control signal or the second control signal.

[0096] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the components shown or discussed are direct couplings.

[0097] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0099] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A memory, characterized in that, comprising: a first circuit configured to receive an activation address and determine a first row address according to a first rule and the activation address; the activation address is the address of the memory row being accessed in the current access operation; a second circuit configured to receive the activation address and determine a second row address according to a second rule and the activation address; the determination method of the second rule is different from that of the first rule; a selection circuit coupled to both the first circuit and the second circuit, configured to receive the first row address and the second row address, and select one of the first row address and the second row address as the attacked row address.

2. The memory according to claim 1, characterized in that, the first circuit includes an address processor; the address processor is used to store the addresses of multiple first memory rows and count the number of accesses to each of the first memory rows; the multiple first memory rows are multiple memory rows determined according to the number of accesses before the current access operation; the number of addresses of the first memory rows stored in the address memory is a fixed value; the second circuit includes a matching unit, and the matching unit is used to store the addresses of multiple second memory rows; the second memory rows are at least part of the memory rows accessed before the current access operation; the number of addresses of the second memory rows stored in the matching unit is a variable value.

3. The memory according to claim 2, characterized in that, the determination method of the second rule includes: performing fuzzy processing on the activation address, and matching the fuzzy processed activation address with the addresses of all second memory rows in the matching unit one by one to obtain a fuzzy matching result; wherein, when the fuzzy matching result shows a successful match, it is determined that the activation address is the second row address.

4. The memory according to claim 3, characterized in that, both the activation address and the addresses of the second memory rows include a first data bit and a second data bit arranged in sequence; matching the first data bit of the activation address with the first data bits of the addresses of all second memory rows in the matching unit one by one to obtain a fuzzy matching result; wherein, when the first data bit of the activation address is the same as the first data bit of the addresses of at least one second memory row among all second memory rows, the fuzzy matching result shows a successful match; when the first data bit of the activation address is not the same as the first data bits of the addresses of all second memory rows, the fuzzy matching result shows a failed match.

5. The memory according to claim 4, characterized in that, when the fuzzy matching result shows a failed match, it is determined that the second row address is an empty address; and, store the activation address as the address of a new second memory row in the matching unit.

6. The memory according to claim 2, characterized in that, the determination method of the first rule includes: comparing the activation address with the addresses of all first memory rows in the address processor one by one; Wherein, when the activation address matches the address of one of all the first memory rows, increment the count value of the first memory row that matches in the address processor by an increment value; and After incrementing by one such increment value, compare the current count values of all the first memory rows in the address processor, and determine the address of the first memory row corresponding to the current maximum count value as the first row address.

7. The memory according to claim 1, wherein, the memory further includes: an address conversion circuit and a refresh circuit; wherein, the address conversion circuit is connected to the selection circuit and is configured to: receive the attacked row address; and determine the victim row address according to the attacked row address; the victim row is at least one memory row physically located above and below the attacked row; the refresh circuit, connected to the address conversion circuit, is configured to: receive the victim row address, and perform a refresh operation on the victim row.

8. The memory according to claim 7, wherein, the memory further includes: a control circuit; the control circuit is respectively connected to the first circuit, the second circuit, the selection circuit, and the refresh circuit and is configured to: receive a refresh command, split the refresh command into a first control signal and a second control signal, and output the first control signal and / or the second control signal; wherein, the timing of the first control signal and the second control signal is alternately set at intervals.

9. The memory according to claim 8, wherein, the control circuit includes: a first refresh control circuit and a second refresh control circuit; wherein, the first refresh control circuit is configured to: receive the refresh command and output a row hammer refresh signal based on the refresh command; the second refresh control circuit, connected to the first refresh control circuit, is configured to: receive the row hammer refresh signal, and split the row hammer refresh signal into the first control signal and the second control signal; and output the first control signal to the first circuit, output the second control signal to the second circuit, output the first control signal or the second control signal to the selection circuit, and output the first control signal or the second control signal to the refresh circuit.

10. The memory according to claim 9, wherein, the first circuit determines the first row address based on the first control signal, according to the first rule and the activation address; the second circuit determines the second row address based on the second control signal, according to the second rule and the activation address; the selection circuit selects one of the first row address and the second row address as the attacked row address based on the first control signal or the second control signal; the refresh circuit performs a refresh operation on the victim row based on the first control signal or the second control signal.

11. The memory according to claim 1, wherein, the first row address is the same as or different from the second row address.

12. A memory system, wherein, comprising one or more memories as described in any one of claims 1-11; and a memory controller, coupled to the memory, for controlling the memory.

13. A method for controlling a memory, characterized in that the memory includes a first circuit, a second circuit, and a selection circuit; wherein, the control method includes: the first circuit receives an activation address and determines a first row address according to a first rule and the activation address; the activation address is the address of the memory row to be accessed in the current access operation; the second circuit receives the activation address and determines a second row address according to a second rule and the activation address; the determination manner of the second rule is different from that of the first rule; the selection circuit receives the first row address and the second row address, and selects one of the first row address and the second row address as the attacked row address.

14. The control method according to claim 13, characterized in that the first circuit includes an address processor; the second circuit includes a matching unit; the operation method includes: acquiring the addresses of a plurality of first memory rows, and counting the number of accesses to each of the plurality of first memory rows; storing the addresses of the plurality of first memory rows and the result of the counting in the address processor; the first memory rows are a plurality of memory rows determined according to the number of accesses before the current access operation; the number of addresses of the first memory rows stored in the address memory is a fixed value; and acquiring the addresses of a plurality of second memory rows, and storing the addresses of the plurality of second memory rows in the matching unit; the second memory rows are at least some of the memory rows accessed before the current access operation; the number of addresses of the second memory rows stored in the matching unit is a variable value.

15. The control method according to claim 14, characterized in that determining the second row address according to the second rule and the activation address includes: performing fuzzy processing on the activation address, and sequentially matching the fuzzy-processed activation address with the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the fuzzy matching result shows a successful match, it is determined that the activation address is the second row address.

16. The control method according to claim 15, characterized in that both the activation address and the address of the second memory row include a first data bit and a second data bit arranged in sequence; performing fuzzy processing on the activation address, and sequentially matching the fuzzy-processed activation address with the addresses of all second memory rows in the matching unit to obtain the fuzzy matching result, includes: sequentially matching the first data bit of the activation address with the first data bits of the addresses of all second memory rows in the matching unit to obtain a fuzzy matching result; wherein, when the first data bit of the activation address is the same as the first data bit of the address of at least one second memory row among all second memory rows, the fuzzy matching result shows a successful match; When the first data bit of the activation address is different from the first data bits of the addresses of all the second memory rows, the result of the fuzzy match is displayed as a match failure.

17. The control method according to claim 16, wherein, the control method further includes: when the result of the fuzzy match is displayed as a match failure, determining that the second row address is an empty address; and storing the activation address as the address of a new second memory row in the matching unit.

18. The control method according to claim 14, wherein, determining the first row address according to the first rule and the activation address includes: comparing the activation address with the addresses of all the first memory rows in the address processor one by one; wherein, when the activation address matches the address of one of all the first memory rows, increasing the count value of the first memory row in the address processor that matches by an increment value; and after increasing by one such increment value, comparing the current count values of all the first memory rows in the address processor and determining the address of the first memory row corresponding to the current maximum count value as the first row address.

19. The control method according to claim 13, wherein, the memory further includes: an address conversion circuit and a refresh circuit; wherein, the control method further includes: the address conversion circuit receives the attacked row address; and determines the victim row address according to the attacked row address; the victim rows are at least one memory row each above and below the attacked row in the physical position; the refresh circuit receives the victim row address and performs a refresh operation on the victim rows.

20. The control method according to claim 19, wherein, the memory further includes: a control circuit; wherein, the control method further includes: the control circuit receives a refresh command, splits the refresh command into a first control signal and a second control signal, and outputs the first control signal and / or the second control signal; wherein, the timing of the first control signal and the second control signal is alternately set at intervals.

21. The control method according to claim 20, wherein, the control circuit includes: a first refresh control circuit and a second refresh control circuit; the control circuit receives the refresh command, splits the refresh command into a first control signal and a second control signal, and outputs the first control signal and / or the second control signal, including: the first refresh control circuit receives the refresh command and outputs a row hammer refresh signal based on the refresh command; the second refresh control circuit receives the row hammer refresh signal and splits the row hammer refresh signal into the first control signal and the second control signal; the control method further includes: outputting the first control signal to the first circuit, outputting the second control signal to the second circuit, outputting the first control signal or the second control signal to the selection circuit, and outputting the first control signal or the second control signal to the refresh circuit.

22. The control method according to claim 21, Characterized in that, The first circuit determines a first row address based on the first control signal, according to a first rule and the activation address; The second circuit determines a second row address based on the second control signal, according to a second rule and the activation address; The selection circuit selects one of the first row address and the second row address as the attack row address based on the first control signal or the second control signal; The refresh circuit performs a refresh operation on the victim row based on the first control signal or the second control signal.

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