Read retry method and device for flash memory chip and storage medium

Abstract

The invention discloses a read retry method and equipment for a flash memory chip and a storage medium, and belongs to the technical field of data processing. The method comprises the following steps: after a read retry process of a flash memory chip is triggered, determining an error rate and / or a read sensing voltage for triggering the read retry process, inputting the triggered error rate and / or the read sensing voltage into a read offset model corresponding to the flash memory chip, and obtaining a retry voltage output by the read offset model, and performing read retry on the flash memory chip through the retry voltage, adjusting the retry voltage based on a read retry result, and when the read retry result is successful, updating the read sensing voltage based on the corresponding retry voltage and storing the read sensing voltage. According to the method, the corresponding read offset models are set for different flash memory chip models, the retry voltage is selected for read retry, the number of retry times needed for successful read retry is reduced, and the service life of the flash memory chip is prolonged.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a read retry method, device, and storage medium for a flash memory chip. Background Art

[0002] The NAND flash memory chip will gradually age with the number of write and erase cycles, resulting in an offset of the read sensing voltage used for data reading of the flash memory chip. To ensure the normal use of the flash memory chip, the flash memory chip obtains a retry voltage from a preset read retry table, performs a read retry on the flash memory chip with the retry voltage, and saves the retry voltage with successful reading as the read sensing voltage to ensure that data can be read normally during the subsequent use of the flash memory chip.

[0003] However, due to the relatively high granularity of the retry voltages in the read retry table, during the reading process of the flash memory chip, it is necessary to perform a relatively large number of read retries on the chip to determine the voltage threshold of the flash memory chip. During this process, the continuous retry of the read sensing voltage will further affect the read sensing voltage of the flash memory chip and cause aging. This results in a short service life of the flash memory chip.

[0004] The above content is only used to assist in understanding the technical solution of this application, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a read retry method, device, and storage medium for a flash memory chip, aiming to solve the technical problem that the flash memory chip is further aged due to excessive read retry times, resulting in a short service life.

[0006] To achieve the above purpose, this application provides a read retry method for a flash memory chip, and the method includes the following steps: After triggering the read retry process of the flash memory chip, determine the error rate and / or read sensing voltage that trigger the read retry process; Input the triggered error rate and / or read sensing voltage into the read offset model corresponding to the flash memory chip, and obtain the retry voltage output by the read offset model; Perform a read retry on the flash memory chip with the retry voltage, and adjust the retry voltage based on the read retry result; When the read retry result is successful, update and save the read sensing voltage based on the corresponding retry voltage.

[0007] In one embodiment, before the step of obtaining the read offset model corresponding to the flash memory chip model of the flash memory cell after triggering the read retry process of the flash memory cell, it further includes: Verify the read data of the data page in the flash memory chip through a check code, and identify the error data in the data page according to the verification result; Calculate the bit error rate of the data page according to the ratio of the bit error data to the number of read data; When the bit error rate is greater than the bit error rate threshold, select the data page corresponding to the bit error data as the target data page; Trigger the read retry process of the target data page.

[0008] In one embodiment, the steps of performing read retry on the flash memory chip through the retry voltage and adjusting the retry voltage based on the read retry result include: Perform a read operation on the flash memory chip through the retry voltage to obtain the read retry data of the flash memory chip; Calculate the retry bit error rate of the read retry data; When the retry bit error rate is higher than the bit error rate threshold, adjust the retry voltage according to the retry bit error rate and the read offset model.

[0009] In one embodiment, after triggering the read retry process of the flash memory cell, before the step of obtaining the read offset model of the flash memory chip model corresponding to the flash memory cell, further include: Obtain the historical read retry data of the flash memory chip model; Based on the historical read sensing voltage and / or historical bit error rate, obtain the historical retry voltage and the retry result corresponding to the historical retry voltage in the historical read retry data; According to the retry result, calculate the read retry success probability corresponding to the historical retry voltage under the historical read sensing voltage and / or historical bit error rate; Construct a mapping relationship between the historical retry voltage and the read retry success probability under different historical read sensing voltages and / or historical bit error rates; Based on the mapping relationship, generate a read offset model and associate the read offset model with the flash memory chip model.

[0010] In one embodiment, the steps of obtaining the read offset model of the flash memory chip model corresponding to the flash memory chip after triggering the read retry process of the flash memory chip include: After triggering the read process, obtain the attribute information of the flash memory chip; Determine the flash memory chip model according to the attribute information; In the model database, obtain the read offset model associated with the flash memory chip signal.

[0011] In one embodiment, when the read retry result is successful, after the step of updating and saving the read sensing voltage based on the corresponding retry voltage, further include: According to the bit error rate and / or read sensing voltage, associate and save the retry voltage and the read retry result of the retry voltage to the historical read retry data to update the historical read retry data; Adjust the mapping relationship according to the updated historical read retry data; Update the read offset model based on the adjusted mapping relationship.

[0012] In one embodiment, when the read retry result is successful, the steps of updating and saving the read sensing voltage based on the corresponding retry voltage include: When the read retry result is successful, determine the data page corresponding to the read retry and the retry voltage; Update the retry voltage to the read sensing voltage of the data page; Synchronize the target read sensing voltages of all other data pages of the flash memory chip according to the read sensing voltage.

[0013] In one embodiment, the steps of determining the retry voltage according to the read offset model based on the error rate and / or the read sensing voltage that trigger the read retry process include: Obtain the read retry table of the flash memory chip, and in the read retry table, obtain the read retry voltage of the flash memory chip; Input the error rate and / or the read sensing voltage, and the read retry voltage into the read offset model; Determine the success probability of the read retry voltage according to the output result of the read offset model; Select the retry voltage from the read retry voltages based on the success probability.

[0014] In addition, to achieve the above object, the present application also provides a read retry device for a flash memory chip, the device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program is configured to implement the steps of the read retry method for the flash memory chip as described above.

[0015] In addition, to achieve the above object, the present application also provides a storage medium, the storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium, and when the computer program is executed by a processor, it implements the steps of the read retry method for the flash memory chip as described above.

[0016] One or more technical solutions proposed by the present application have at least the following technical effects: In the present application, different read offset models are set for different flash memory chip models. When performing read retry on the flash memory chip, by inputting the error rate and / or the read sensing voltage that trigger the read retry process into the corresponding read offset model of the flash memory chip, the retry voltage output by the read offset model is obtained, and the offset of the sensing voltage is predicted through the read offset model, so as to reduce the number of continuous trial and error in the read retry of the flash memory chip. During the read retry process, the offset of the retry voltage is adjusted by scanning, reducing the number of times the flash memory chip adjusts the read sensing voltage through read retry, and avoiding the aging of the chip caused by frequent read retry, thereby improving the service life of the flash memory chip. Description of the Drawings

[0017] The accompanying drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with this application, and are used together with the description to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic flowchart of the first embodiment of the read retry method for the flash memory chip of this application; Figure 2 It is a schematic flowchart of the second embodiment of the read retry method for the flash memory chip of this application; Figure 3 It is a schematic flowchart of the third embodiment of the read retry method for the flash memory chip of this application; Figure 4 It is a schematic flowchart of the fourth embodiment of the read retry method for the flash memory chip of this application; Figure 5 It is a schematic structural diagram of the read retry device of the flash memory chip in the hardware operating environment related to the solution of the embodiment of this application.

[0020] The realization of the purpose of this application, functional features, and advantages will be further described with reference to the embodiments and the accompanying drawings. Specific Embodiments

[0021] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0022] To better understand the above technical solutions, the following will describe the above technical solutions in detail with reference to the accompanying drawings of the description and specific embodiments.

[0023] The main solution of the embodiment of this application is: after triggering the read retry process of the flash memory chip, determine the error rate and / or read sensing voltage that trigger the read retry process; input the triggered error rate and / or the read sensing voltage into the corresponding read offset model of the flash memory chip, and obtain the retry voltage output by the read offset model; perform read retry on the flash memory chip through the retry voltage, and adjust the retry voltage based on the read retry result; when the read retry result is successful, update and save the read sensing voltage based on the corresponding retry voltage.

[0024] In the related art, a flash memory chip performs read retry and adjustment on a read sensing voltage through a set read retry table. Among them, due to the high granularity of the read retry table, during the read process of the flash memory chip, the chip needs to be retried a relatively large number of times to determine the voltage threshold of the flash memory chip. And in this process, the continuous retry of the read sensing voltage will further affect the read sensing voltage of the flash memory chip and cause aging. This results in a short service life of the flash memory chip.

[0025] In this application, different read offset models are set for different flash memory chip models. When performing read retry on the flash memory chip, by inputting the error rate and / or read sensing voltage that trigger the read retry process into the corresponding read offset model of the flash memory chip, the retry voltage output by the read offset model is obtained. The offset of the sensing voltage is predicted through the read offset model to reduce the number of continuous trial-and-error during the read retry of the flash memory chip. And during the read retry process, the offset of the retry voltage is adjusted by scanning, reducing the number of times the flash memory chip adjusts the read sensing voltage through read retry, and avoiding the aging of the chip caused by frequent read retry, thereby improving the service life of the flash memory chip.

[0026] To better understand the above technical solution, the exemplary embodiments of this application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of this application and to be able to fully convey the scope of this application to those skilled in the art.

[0027] It should be noted that the execution subject of this embodiment can be a flash memory management system, or a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a flash memory controller, or a read retry device of a flash memory chip that can implement the above functions. This embodiment does not make a specific limitation on this. The following takes the flash memory management system as an example to illustrate this embodiment and the following embodiments.

[0028] Based on this, the embodiment of this application provides a read retry method for a flash memory chip, referring to Figure 1 , Figure 1 which is a schematic flowchart of the first embodiment of the read retry method for the flash memory chip of this application.

[0029] In this embodiment, the read retry method for the flash memory chip includes steps S10 to S40: Step S10: After triggering the read retry process of the flash memory chip, determine the error rate and / or read sensing voltage that trigger the read retry process; It should be noted that when a flash memory chip stores data through flash memory cells, different voltage levels are distinguished according to the charge storage amount, so as to represent different data. When the flash memory management system reads the data of the flash memory chip, it determines the read sensing voltage of the flash memory chip and applies a voltage of corresponding magnitude to the flash memory chip, and obtains the data according to the conduction state of the flash memory cells in the flash memory chip. For example, the flash memory management system sets the read sensing voltage to 5V. If the flash memory cell conducts at this read sensing voltage, the data of the flash memory cell is 1, and if it does not conduct, the data is 0. However, due to the coupling effect caused by the read, programming operations of adjacent word lines or the erase operation of adjacent blocks, etc., the voltage of the flash memory cells storing the data may shift, generating a read offset of the voltage. When the voltage offset exceeds a certain range, it will cause data reading errors, thus triggering the read retry process.

[0030] In this embodiment, according to the data reading error situation that triggers the read retry process, the flash memory management system can determine the bit error rate of the data reading error, that is, the proportion of the error data in all the read data. At the same time, based on the process information of the read retry process, the read sensing voltage that triggers the read retry of the flash memory chip can be determined.

[0031] Step S20: Input the triggered bit error rate and / or the read sensing voltage into the read offset model corresponding to the flash memory chip, and obtain the retry voltage output by the read offset model; In this embodiment, based on the bit error rate and / or the read sensing voltage of the data reading error situation, the flash memory management system can determine the voltage offset based on the read offset model corresponding to the flash memory chip model, and determine the retry voltage according to the voltage offset and the read sensing voltage.

[0032] It should be noted that since the structures and components of flash memory chips of different flash memory chip models are different, in the flash memory management system, different read offset models are set according to different flash memory chip models. The read offset model is used to determine the correlation between the read sensing voltage and the read offset in each data page of the flash memory chip, so that the flash memory management system can determine the most appropriate retry voltage for read retry based on the read offset model. Among them, the flash memory management system can be deployed on a cloud server or in a terminal device responsible for reading and writing the flash memory chip. The terminal device can be optionally an electronic device such as a computer, a tablet computer or a mobile phone, which has an interaction function with the flash memory chip and a data processing function.

[0033] Optionally, the terminal device can automatically detect the device information, i.e., the attribute information, of the connected hardware device. After triggering the reading process, the flash memory management system can obtain the attribute information of the flash memory chip locally on the terminal, and determine the flash memory chip model of the flash memory chip by matching the attribute information with the pre-stored flash memory chip model information. Through the flash memory chip model, the flash memory management system can obtain the read offset model associated with the flash memory chip signal in the model database.

[0034] As an alternative implementation for obtaining the retry voltage, the flash memory management system can directly determine, in the read offset model, the voltage offset with the highest probability or the voltage with the highest read retry success probability at the read sense voltage based on the read sense voltage, so as to determine the retry voltage. Alternatively, the flash memory management system can also determine the voltage offset and thus the retry voltage based on the bit error rate according to the number of errors or the error ratio of the read data.

[0035] As another alternative implementation for obtaining the retry voltage, the flash memory management system can determine the retry voltage in the offset model based on both the bit error rate and the read sense voltage. The flash memory management system determines, through the read offset model, the read retry success probabilities of different read retry voltages for the flash memory chip of this flash memory chip model under this bit error rate or bit error rate range and the read sense voltage, so as to select the retry voltage with the highest success probability.

[0036] Optionally, the read offset model can be generated in a training manner based on deep learning and historical read retry data. Alternatively, the read retry voltage can also be used to construct a mapping relationship between the read offset, the read sense voltage, and the determined retry voltage success probability through big data analysis based on historical read retry data. This mapping relationship can be a calculation formula for calculating the read retry success probability based on the read offset, the read sense voltage, and / or the bit error rate, or a mapping table between the read offset, the read sense voltage, and / or the bit error rate and the read retry success probability.

[0037] Optionally, since the flash memory chip usually contains a read retry table set by the flash memory chip manufacturer based on the chip structure. The flash memory management system can initially obtain candidate read retry voltages based on the read retry table and input the read retry voltages into the read offset model. The read offset model determines the success probability of the read retry voltage based on the bit error rate and / or the read sense voltage, so as to reduce the complexity of data processing by the read offset model and improve the response speed of the system. Specifically, the flash memory management system inputs the bit error rate, the read sense voltage, and the read retry voltage into the read offset model, determines the success probability of the read retry voltage according to the output result of the read offset model, and selects the retry voltage from the read retry voltages based on this success probability.

[0038] Step S30: Perform a read retry on the flash memory chip using the retry voltage, and adjust the retry voltage based on the read retry result; In this embodiment, after the flash memory management system obtains the retry voltage and performs a read retry on the flash memory chip, it determines the read retry result based on the read retry data read after the read retry. Among them, when the read retry result is a failure, the flash memory management system needs to adjust the retry voltage and perform a read retry again until the read retry result is a success, so that the flash memory management system can successfully read the data in the flash memory chip.

[0039] Specifically, the flash memory management system reads the read retry data of the flash memory chip through the retry voltage, and determines the read retry result by calculating the retry error rate of the read retry data. Among them, if the retry error rate is higher than the error rate threshold, it is determined that the read retry fails. If it is higher, it is determined that the read retry result is a success.

[0040] As an alternative implementation of adjusting the retry voltage, when the retry error rate is higher than the error rate threshold, the retry voltage is adjusted according to the retry error rate and the read offset model. The flash memory management system can use the retry voltage of the previous read retry as the read sensing voltage, and in the read offset model, select the retry voltage with the highest read retry success rate again according to the retry error rate and / or the retry voltage.

[0041] As another alternative implementation of adjusting the retry voltage, after the flash memory management system determines the error rate and error data of the data read from the flash memory chip, it records the error information of the read data. Among them, the error information contains the error data. After the flash memory management system determines that the read retry fails, it determines the retry error data in the read retry data and determines whether the retry error data is the original error data or the newly added error data. When there are more newly appeared error data, greater than the preset quantity threshold or the preset error quantity ratio, it means that the voltage offset between the retry voltage and the read sensing voltage is relatively large, and the flash memory management system will reduce the retry voltage according to the preset voltage adjustment amount. Or, when there are more original error data, greater than the preset quantity threshold or the preset error quantity ratio, it means that the voltage offset between the retry voltage and the read sensing voltage is relatively small, and the flash memory management system will increase the retry voltage according to the preset voltage adjustment amount. Among them, the voltage adjustment amount is the voltage change amount preset by the flash memory management system for a single adjustment of the retry voltage based on the read retry mechanism.

[0042] Step S40: When the read retry result is successful, update and save the read sensing voltage based on the corresponding retry voltage.

[0043] In this embodiment, when the read retry result is successful, the flash memory management system ends the loop of read retry and adjustment of the retry voltage, and updates the read sensing voltage of the flash memory chip to the same voltage value as the retry voltage at which the read retry is successful.

[0044] It should be noted that the flash memory chip performs read and write operations on data in units of data pages. Among them, for NAND flash memories with a capacity of less than 2 Gb, the page capacity is usually 512 bytes, along with 16 bytes of check information, while for NAND flash memories with a capacity of more than 2 Gb, the page capacity is expanded to 2048 bytes, along with 64 bytes of check information, or larger. At the same time, the flash memory performs erase operations in units of blocks (Blocks). Each block contains a certain number of data pages, and the number of data pages depends on the capacity of the flash memory and the page size. When reading or writing data, the flash memory chip transmits commands and addressing information through the I / O interface, and then transfers the data to or from the page register in units of pages.

[0045] In one embodiment, since the flash memory management system calculates the bit error rate based on the read data corresponding to the data page and performs read retry on the read data of the data page when performing verification of the flash memory data page. Therefore, after the flash memory management system performs read retry on the data page and completes the update of the read sensing voltage, it determines the data page corresponding to the read retry and the retry voltage, and synchronously updates this retry voltage or the read sensing voltage to the target read sensing voltages of other data pages or other blocks of the flash memory chip, so as to achieve the unification of the read sensing voltages of the flash memory chip.

[0046] Optionally, the flash memory management system can record the read sensing voltages of the entire flash memory chip, or can separately record the read sensing voltages of each data page or data block.

[0047] In the embodiments of the present application, different read offset models are set for different flash memory chip models. When performing read retry on the flash memory chip, the retry voltage with the highest read retry success probability is obtained through the read offset model, and during the read retry process, the offset of the retry voltage is adjusted by scanning, reducing the number of times the flash memory chip adjusts the read sensing voltage through read retry, avoiding the aging of the chip caused by frequent read retries, and thus improving the service life of the flash memory chip.

[0048] Based on the same inventive concept, the present application also provides a second embodiment. Refer to Figure 2 , Figure 2 which is a schematic flow chart of the second embodiment of the read retry method for the flash memory chip of the present application.

[0049] In this embodiment, before triggering the read retry process of the flash memory chip and obtaining the read offset model corresponding to the flash memory chip model of the flash memory chip as described in step S10, steps S11 to S14 are further included: Step S11: Verify the read data of the data page in the flash memory chip through a check code, and identify the error data in the data page according to the verification result; Step S12: Calculate the error rate of the data page according to the ratio of the quantity of the error data to the read data; Step S13: When the error rate is greater than the error rate threshold, select the data page corresponding to the error data as the target data page; Step S14: Trigger the read retry process of the target data page.

[0050] In this embodiment, the flash memory management system further includes an Error Checking and Correction (ECC) mechanism. Based on ECC, when the flash memory management system stores data into the flash memory chip, it will calculate the check code of the data to be stored based on a preset check code algorithm, and store the check code and the data to be stored into the flash memory chip together. At the same time, ECC can calculate the target check code for the read data every time the flash memory management system reads the flash memory chip and obtains the read data, and compare the target check code with the check code read together with the read data, so as to determine whether the read data is in error.

[0051] Optionally, when ECC detects an error within the error correction range, it can directly correct the error through a decoder. After the correction is completed, the system will evaluate the error rate of the data, that is, the original error level without ECC correction. If the error rate is too high and exceeds the error correction capability range of ECC, then ECC will not be able to correct all errors, that is, trigger a read retry.

[0052] Exemplarily, after the error data can be determined through the check code, the flash memory management system will calculate the error rate of the data page according to the ratio of the quantity of the error data to the read data. Among them, when the error rate is greater than the error rate threshold, the flash memory management system will use this data page as the target data page and trigger the read retry process of this data page.

[0053] Since the system introduced in the second embodiment of the present application is the system adopted for implementing the method of the first embodiment of the present application, based on the method introduced in the first embodiment of the present application, those skilled in the art can understand the specific structure and variations of the system, so it will not be elaborated here. Any system adopted by the method of the first embodiment of the present application falls within the scope of protection of the present application.

[0054] Based on the same inventive concept, the present application further provides a third embodiment, referring toFigure 3 , Figure 3 It is a schematic flowchart of the third embodiment of the read retry method for the flash memory chip of the present application.

[0055] In this embodiment, the read retry method for the flash memory chip includes steps S01 to S05: Step S01: Obtain the historical read retry data of the flash memory chip model; Step S02: Based on the historical read sensing voltage and / or historical error rate, obtain the historical retry voltage and the retry result corresponding to the historical retry voltage in the historical read retry data; Step S03: According to the retry result, calculate the read retry success probability corresponding to the historical retry voltage under the historical read sensing voltage and / or the historical error rate; Step S04: Construct a mapping relationship between the historical retry voltage and the read retry success probability under different historical read sensing voltages and / or historical error rates; Step S05: Based on the mapping relationship, generate the read offset model and associate the read offset model with the flash memory chip model.

[0056] In this embodiment, by obtaining the historical read retry data of the flash memory chip model, it is possible to determine the retry results of the flash memory chip of this flash memory chip model under different historical error rates and / or historical read sensing voltages through different historical retry voltages. Among them, based on the retry results of the historical retry voltage, it is possible to determine the read retry success probability of the retry voltage under different historical read sensing voltages and / or historical error rates, thereby constructing a mapping relationship between the historical read sensing voltage and / or historical error rate, and the historical retry voltage, and the read retry success probability. Based on this mapping relationship, it is possible to generate the read offset model of this flash memory chip model and store the read offset model associated with the flash memory chip model.

[0057] Since the system introduced in the third embodiment of the present application is the system adopted for implementing the method of the first embodiment of the present application, based on the method introduced in the first embodiment of the present application, those skilled in the art can understand the specific structure and variations of the system, so it will not be elaborated here. Any system adopted by the method of the first embodiment of the present application falls within the scope of protection of the present application.

[0058] Based on the same inventive concept, the present application also provides a fourth embodiment, refer to Figure 4 , Figure 4 It is a schematic flowchart of the fourth embodiment of the read retry method for the flash memory chip of the present application.

[0059] In this embodiment, when the read retry result is successful as described in step S40, after updating and saving the read sensing voltage based on the corresponding retry voltage, steps S51 to S53 are further included: Step S51: Associate and save the retry voltage and the read retry result of the retry voltage to the historical read retry data according to the bit error rate and / or the read sensing voltage, so as to update the historical read retry data; Step S52: Adjust the mapping relationship according to the updated historical read retry data; Step S53: Update the read offset model based on the adjusted mapping relationship.

[0060] In this embodiment, after the flash memory management system completes the read retry of the flash memory chip, it can record the bit error rate and / or the read sensing voltage, as well as the retry voltage and the read retry result of the retry voltage during the read retry process, so as to update the historical read retry data. Further, based on the updated historical read retry data, the flash memory management system can adjust the mapping relationship in the read offset model. The adjusted mapping relationship determines the success probability of different retry voltages based on the updated historical read retry data, so as to update the read offset model.

[0061] Since the system introduced in Embodiment 4 of the present application is the system adopted for implementing the method of Embodiment 1 of the present application, based on the method introduced in Embodiment 1 of the present application, those skilled in the art can understand the specific structure and variations of the system, so it will not be elaborated here. Any system adopted for the method of Embodiment 1 of the present application falls within the scope of protection of the present application.

[0062] The present application provides a read retry device for a flash memory chip, the device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the read retry method of the flash memory chip in Embodiment 1 above.

[0063] Next, refer to Figure 5, which shows a schematic structural diagram of a read retry device of a flash memory chip suitable for implementing the embodiments of the present application. The read retry device of the flash memory chip in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description: tablet computers), PMPs (Portable Media Player), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The read retry device of the flash memory chip shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present application.

[0064] As Figure 5 shown, the read retry device of the flash memory chip may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the read retry device of the flash memory chip are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the read retry device of the flash memory chip to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a read retry device of a flash memory chip having various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or had alternatively.

[0065] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product that includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by a processing device 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are executed.

[0066] The read retry device for a flash memory chip provided by the present application adopts the read retry method for a flash memory chip in the above-mentioned embodiment, and can solve the technical problem that the flash memory chip is further aged due to excessive read retry times, resulting in a short service life. Compared with the prior art, the beneficial effects of the read retry device for a flash memory chip provided by the present application are the same as those of the read retry method for a flash memory chip provided in the above-mentioned embodiment, and other technical features in the read retry device for a flash memory chip are the same as the features disclosed in the method of the previous embodiment, and will not be elaborated here.

[0067] It should be understood that each part disclosed in the present application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0068] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0069] The present application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the read retry method for a flash memory chip in the above-mentioned embodiment.

[0070] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in combination with an instruction execution system, device, or component. The program code contained on the computer-readable storage medium can be transmitted by any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0071] The above computer-readable storage medium can be included in the read retry device of the flash memory chip; it can also exist independently and not be assembled into the read retry device of the flash memory chip.

[0072] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by the read retry device of the flash memory chip, the read retry device of the flash memory chip is caused to: after triggering the read retry process of the flash memory chip, determine the error rate and / or read sensing voltage that trigger the read retry process; input the triggered error rate and / or the read sensing voltage into the read offset model corresponding to the flash memory chip, and obtain the retry voltage output by the read offset model; perform read retry on the flash memory chip through the retry voltage, and adjust the retry voltage based on the read retry result; when the read retry result is successful, update the read sensing voltage and save it based on the corresponding retry voltage.

[0073] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN: Local Area Network) or a wide area network (WAN: Wide Area Network), or it can be connected to an external computer (for example, by connecting through an Internet service provider using the Internet).

[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and this module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks can occur in a different order than that marked in the accompanying drawings. For example, two consecutively represented blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0075] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0076] The readable storage medium provided in this application is a computer-readable storage medium. The computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for performing the above-mentioned read retry method of the flash memory chip, and can solve the technical problem that the flash memory chip is further aged due to excessive read retry times, resulting in a short service life. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the read retry method of the flash memory chip provided in the above embodiments, and will not be elaborated here.

[0077] The above are only some embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A read retry method for a flash memory chip, characterized in that: The method comprises the following steps: After triggering a read retry process of the flash memory chip, determining a bit error rate and / or a read sensing voltage that triggers the read retry process; Triggering the bit error rate and / or the read sensing voltage, inputting a read offset model corresponding to the flash memory chip, and acquiring a retry voltage output by the read offset model; Performing a read retry on the flash memory chip using the retry voltage, and adjusting the retry voltage based on a read retry result; When the read retry result is successful, the read sensing voltage is updated and saved based on the corresponding retry voltage.

2. The method according to claim 1, characterized in that After triggering the read retry process of the flash memory unit, before the step of obtaining the read offset model of the flash memory unit corresponding to the flash memory chip model, it also includes: Verifying the read data of the data page in the flash memory chip by using a verification code, and identifying the bit error data in the data page according to the verification result; Calculating a bit error rate of the data page according to a ratio of the number of bit error data to the number of read data; When the bit error rate is greater than a bit error rate threshold, selecting a data page corresponding to the bit error data as a target data page; The read retry process of the target data page is triggered.

3. The method according to claim 1, characterized in that The step of performing a read retry on the flash memory chip by using the retry voltage and adjusting the retry voltage based on the read retry result comprises: By using the retry voltage, performing a read operation on the flash memory chip to obtain read retry data of the flash memory chip; Calculating a retry bit error rate of the read retry data; When the retry bit error rate is higher than a bit error rate threshold, the retry voltage is adjusted according to the retry bit error rate and the read offset model.

4. The method according to claim 1, characterized in that After triggering the read retry process of the flash memory unit, before the step of obtaining the read offset model of the flash memory unit corresponding to the flash memory chip model, it also includes: Obtain historical read retry data of the flash memory chip model; Based on the historical read sensing voltage and / or the historical bit error rate, obtaining a historical retry voltage and a retry result corresponding to the historical retry voltage in the historical read retry data; According to the retry result, calculating the read retry success probability corresponding to the historical retry voltage under the historical read sensing voltage and / or the historical bit error rate; Constructing a mapping relationship between the historical retry voltage and the read retry success probability under different historical read sensing voltages and / or historical bit error rates; Based on the mapping relationship, the read offset model is generated, and the read offset model is associated with the flash memory chip model.

5. The method according to claim 4, characterized in that After triggering the read retry process of the flash memory chip, the step of obtaining the read offset model of the flash memory chip corresponding to the flash memory chip model includes: After triggering the reading process, obtaining the attribute information of the flash memory chip; Determine the flash memory chip model according to the attribute information; The read offset model associated with the flash memory chip signal is obtained in the model database.

6. The method according to claim 4, characterized in that After the step of updating and saving the read sensing voltage based on the corresponding retry voltage when the read retry result is successful, the method further includes: According to the bit error rate and / or the read sensing voltage, the retry voltage and the read retry result of the retry voltage are associated and saved in the historical read retry data to update the historical read retry data; Adjusting the mapping relationship according to the updated historical read retry data; Based on the adjusted mapping relationship, the read offset model is updated.

7. The method according to claim 1, characterized in that When the read retry result is successful, the step of updating and saving the read sensing voltage based on the corresponding retry voltage includes: When the read retry result is successful, determining the data page corresponding to the read retry and the retry voltage; Updating the retry voltage to the read sensing voltage of the data page; The target read sensing voltages of all other data pages of the flash memory chip are synchronized according to the read sensing voltage.

8. The method according to claim 1, characterized in that The step of determining the retry voltage according to the read offset model based on the bit error rate and / or the read sensing voltage that triggers the read retry process comprises: Obtaining a read retry table of the flash memory chip, and obtaining a read retry voltage of the flash memory chip from the read retry table; Inputting the bit error rate and / or the read sense voltage and the read retry voltage into the read offset model; Determining the success probability of the read retry voltage according to the output result of the read offset model; The retry voltage is selected from the read retry voltages based on the success probability.

9. A read retry device for a flash memory chip, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the read retry method for the flash memory chip according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the read-retry method for the flash memory chip according to any one of claims 1 to 8 are implemented.

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