Memory chip interference test method and device, and storage medium

Abstract

The invention provides a memory chip interference test method and device and a storage medium. The method comprises the following steps: establishing connection between a storage chip and a test platform; introducing an interference signal to an environment where the memory chip is located, wherein the interference signal generates an electromagnetic field to enable the memory chip to be in an interference environment of the electromagnetic field; adjusting a preset feature of the interference signal according to a preset rule, and sending an access instruction to the memory chip after adjustment, so that the memory chip performs at least one of data reading, writing and erasing according to the access instruction; and controlling the test platform to obtain the error rate and / or the speed of the access result of the storage chip, and reproducing the interference factor of the storage chip according to the error rate and / or the speed. According to the method, the interference of the memory chip in an actual scene can be flexibly and effectively simulated, and performance problems possibly encountered by the memory chip can be well reproduced, so that quick positioning and deep analysis and improvement of related problems are facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of chip testing, and particularly relates to a method and device for testing interference of a storage chip, and a storage medium. Background Art

[0002] With the rapid development of integrated circuit technology, the functions and performance of storage chips have been continuously improved, which has led to a significant increase in the operating frequency and signal transmission rate of storage chips. Therefore, storage chips have the characteristics of high frequency, a large number of transistors, low power supply voltage, and small processing size. In a complex actual application environment, storage chips are often faced with various wireless signal interferences, which may cause a high error rate in the data reading and writing stages of storage chips, resulting in performance degradation or even failure. Therefore, during the entire production cycle of storage chips, testing them is one of the important links to ensure their actual performance and product qualification. However, traditional testing methods only obtain the error rate of the access results of storage chips in one or more relatively fixed interference environments and make improvements based on this. The less and relatively fixed interference environments are difficult to effectively simulate the interferences in the actual scenario, thus making it difficult to reproduce the performance problems that storage chips may encounter, and ultimately being unfavorable for the rapid positioning and in-depth analysis and improvement of various subsequent problems. Summary of the Invention

[0003] In view of this, the present application provides a method and device for testing interference of a storage chip, and a storage medium, which can improve the difficulty of effectively simulating the interference of a storage chip in an actual scenario and thus the difficulty of reproducing the possible performance problems, as well as the resulting disadvantage of being unfavorable for the rapid positioning and in-depth analysis and improvement of related problems.

[0004] A method for testing interference of a storage chip provided by the present application includes:

[0005] Establish a connection between the storage chip and the test platform;

[0006] Introduce an interference signal into the environment where the storage chip is located, and the interference signal generates an electromagnetic field to make the storage chip in the interference environment of the electromagnetic field;

[0007] Adjust the preset characteristics of the interference signal according to a preset rule, and immediately send an access instruction to the storage chip after the adjustment, so that the storage chip performs at least one of data reading, writing, and erasing according to the access instruction;

[0008] Control the test platform to obtain the error rate and / or speed of the access result of the storage chip, and reproduce the interference factors of the storage chip according to the error rate and / or speed.

[0009] Optionally, the preset characteristics of the interference signal include at least one of frequency, amplitude, power, and modulation method.

[0010] Optionally, adjusting the preset features of the interference signal according to the preset rules includes at least one of the following:

[0011] In a closed test chamber, controlling the interference signal to maintain a preset frequency and gradually adjust the power;

[0012] In an open test environment, switching the modulation mode of the interference signal.

[0013] Optionally, an interference signal is introduced into the environment where the storage chip is located through an antenna array.

[0014] Optionally, adjusting the preset features of the interference signal according to the preset rules includes:

[0015] Taking the position where the storage chip is located as the intersection position, determining a plurality of reference cross-sections;

[0016] Obtaining the main interference direction of each antenna;

[0017] Adjusting each antenna so that the main interference direction of each antenna is located on the corresponding reference cross-section.

[0018] Optionally, the angle between any two adjacent reference cross-sections is equal.

[0019] Optionally, adjusting each antenna so that the main interference direction of each antenna is located on the corresponding reference cross-section includes:

[0020] Adjusting the radiation unit of each antenna to be perpendicular to the corresponding reference cross-section.

[0021] Optionally, controlling the test platform to obtain the error rate of the access result of the storage chip includes:

[0022] In the writing stage, generating a redundant code based on the data of the access instruction;

[0023] Storing the data of the access instruction and the redundant code simultaneously;

[0024] In the reading stage, reading out the data and the redundant code together, and checking for errors through the redundant code to obtain the error rate of the access result.

[0025] A storage chip interference test device provided by the present application includes:

[0026] A test platform for establishing a connection with the storage chip;

[0027] An interference component for introducing an interference signal into the environment where the storage chip is located;

[0028] A controller, the interference component and the test platform are respectively connected to the controller. Between the test platform, the interference component and the controller, the test of the storage chip is performed by the interference test method described in any one of the above.

[0029] A storage medium provided by this application stores an interference test program. When the interference test program is executed by a processor, the steps of the interference test method described in any one of the above are implemented.

[0030] As described above, this application adjusts the preset characteristics of the interference signal according to a preset rule, and sends an access instruction to the storage chip immediately after the adjustment, so that the storage chip performs at least one of data reading, writing, and erasing according to the access instruction. Then, the test platform is controlled to obtain the error rate and / or speed of the access result of the storage chip, and the interference factors of the storage chip are reproduced according to the error rate and / or speed. By adjusting the preset characteristics of the interference signal, the interference of the storage chip in the actual scenario can be flexibly and effectively simulated, so that the performance problems that the storage chip may encounter can be better reproduced, which is conducive to the rapid positioning and in-depth analysis and improvement of related problems. Description of the Drawings

[0031] Figure 1 is a schematic flowchart of the interference test method according to an embodiment of this application;

[0032] Figure 2 is a schematic structural diagram of the interference test device according to an embodiment of this application;

[0033] Figure 3 is a schematic structural diagram of the test platform and the storage chip establishing a connection according to an embodiment of this application;

[0034] Figure 4 is a schematic diagram of the position of an antenna array and a storage chip provided by an embodiment of this application;

[0035] Figure 5 is a schematic diagram of dividing the signal transmission direction pattern into multiple regions according to this application. Detailed Embodiments

[0036] To solve the above problems existing in the prior art, this application provides an interference test method and device for a storage chip, and a storage medium. These several protection subjects are based on the same concept, and the principles of solving problems are basically the same or similar. The implementation manners of each protection subject can be referred to each other, and the repeated parts will not be elaborated.

[0037] In the solutions of various protection themes of this application, the preset characteristics of the interference signal are adjusted according to preset rules, and after the adjustment, an access instruction is sent to the storage chip immediately, so that the storage chip performs at least one of data reading, writing, and erasing according to the access instruction, and then controls the test platform to obtain the error rate and / or speed of the access result of the storage chip, and reproduces the interference factors of the storage chip according to the error rate and / or speed. By adjusting the preset characteristics of the interference signal, the interference of the storage chip in the actual scenario can be flexibly and effectively simulated, and the performance problems that the storage chip may encounter can be reproduced, which is conducive to the rapid positioning and in-depth analysis and improvement of related problems.

[0038] To make the purpose, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, rather than all embodiments. Without conflict, the following various embodiments and their technical features can be combined with each other, and they also belong to the technical solutions of this application.

[0039] Figure 1 It is a schematic flowchart of an interference test method according to an embodiment of this application. This interference test method can also be called a "method", and is at least applicable to performing interference tests on storage chips. The execution subject of each step can be an interference test device, or a storage medium, a processor, etc. with related functions.

[0040] As Figure 1 shown, this method at least includes the following steps S1 to S4.

[0041] S1: Establish a connection between the storage chip and the test platform.

[0042] Combined with Figure 2 and Figure 3 shown in the test device scenario, the test platform 2 is used to establish a connection with the storage chip 1 that needs to be subjected to an interference test. The test platform 2 can include one or more communication boards 21. The structures of the multiple communication boards 21 set can be exactly the same or different. Taking the same structure as an example, each communication board 21 can be provided with one or more interfaces. Therefore, the communication board 21 can realize the connection with the corresponding number of test boards 22. Each test board 22 is provided with a corresponding connection port for accessing the storage chip 1 to be tested. In this way, a connection required for testing can be established between the test platform 2 and each storage chip 1. The test boards 22 in the figure are connected to the interfaces of the communication boards 21 one by one. It should be understood that the number of communication boards 21, test boards 22, and the storage chips 1 that can be correspondingly accessed can be determined adaptively according to actual scenario requirements, and this application does not limit them.

[0043] The interference component 23 is used to introduce interference signals into the environment where the storage chip 1 is located. That is, the interference component 23 can be regarded as a signal generator for generating wireless signals within a preset frequency range, such as supporting a frequency range of 100 kHz to 10 GHz, and supporting a power adjustment range of -90 dBm to +33 dBm.

[0044] In one example, the test platform 2 can provide a closed test chamber for the storage chip 1, and the interference component 23 can extend into the closed test chamber to introduce interference signals.

[0045] In other examples, the test platform 2 can provide an open test environment for the storage chip 1, and the interference component 23 can be adjacent to the storage chip 1.

[0046] Combined Figure 2 and Figure 3 As shown, the test platform 2 can also be provided with a controller 24. In other examples, the controller 24 can be independently arranged outside the test platform 2, that is, the controller 24 is a separate device arranged outside the test platform 2, such as a host computer. The interference component 23 and other structural elements of the test platform 2 are respectively connected to the controller 24, and the test of the storage chip 1 is performed among the test platform 2, the interference component 23 and the controller 24 through the method.

[0047] It should be noted that the connection method between the above-mentioned various components, or the interface type, is not limited in this application. For example, the controller 24 can be provided with TCP (Transmission Control Protocol) interfaces and UDP (User Datagram Protocol) interfaces to establish a connection with the test platform 2. TCP is the transmission control protocol, and UDP is the user datagram protocol. Therefore, the test platform 2 and the controller 24 can transmit corresponding data in parallel through these two types of interfaces. The test platform 2 does not need to store the relevant data generated by the test additionally, ensuring the parallel transmission of log data and instruction data and improving the transmission efficiency.

[0048] S2: Introduce interference signals into the environment where the storage chip is located, and the interference signals generate an electromagnetic field to make the storage chip in an electromagnetic field interference environment.

[0049] In Figures 2 to 4 In the scenario shown, the interference component 23 can be an antenna array composed of several antennas 231. Herein, the embodiment of the present application introduces interference signals into the environment where the storage chip 1 is located through the antenna array.

[0050] S3: Adjust the preset features of the interference signal according to preset rules, and send an access instruction to the storage chip immediately after the adjustment, so that the storage chip performs at least one of data reading, writing, and erasing according to the access instruction.

[0051] The access instruction can be at least one of a read instruction, a write instruction, and an erase instruction, so that the storage chip reads, writes, or erases corresponding data according to the access instruction.

[0052] S4: Control the test platform to obtain the error rate and / or speed of the access result of the storage chip, and reproduce the interference factors of the storage chip according to the error rate and / or speed.

[0053] The preset features of the interference signal include but are not limited to at least one of frequency, amplitude, power, and modulation method. The modulation method includes but is not limited to at least one of AM (amplitude modulation), FM (frequency modulation), PM (phase modulation), and QPSK (quadrature phase shift keying) modulation.

[0054] In one example, step S3 can be implemented as: in a closed test chamber, control the interference signal to maintain a preset frequency and gradually adjust the power. For example, in a closed test chamber, build a wireless interference signal simulation system, inject an interference signal with a working frequency of 2.4 GHz into the test environment, and gradually increase the power from -30 dBm (for example, with a power difference) to +10 dBm, successfully reproducing the intermittent data error problem that occurs in the actual application of storage chip 1.

[0055] In other examples, step S3 can be implemented as: in an open test environment, switch the modulation method of the interference signal. For example, in an open test environment, by setting different modulation methods, such as AM and QPSK, simulate the influence of the interference signal on the read and write performance of a certain type of storage chip, and accordingly obtain that the storage chip is particularly sensitive to interference at a specific frequency.

[0056] In the scenario of introducing an interference signal into the environment where the storage chip is located through an antenna array, step S3 may include the following steps S31 to S33:

[0057] S31: Determine a plurality of reference cross-sections with the position of the storage chip as the intersection position;

[0058] S32: Obtain the main interference direction of each antenna; and,

[0059] S33: Adjust each antenna so that the main interference direction of each antenna is located on the corresponding reference cross-section.

[0060] Combined with Figure 2 、 Figure 3 and Figure 4As shown, after connecting the storage chip 1 to the test platform 2, the position of the storage chip 1 is relatively fixed, and each reference cross-section ( Figure 4 shown by each straight line therein) can be regarded as a cross-section of the test environment at different angles. Optionally, the angle between any two adjacent reference cross-sections is equal, so that these antennas 231 are arranged relatively uniformly with respect to the storage chip 1, and the electromagnetic field interference of the interference signal on the storage chip 1 is relatively uniform, which is more conducive to simulating a real interference scenario.

[0061] Each antenna 231 can be set at different positions in the test environment. The main interference direction of each antenna 231 can be regarded as the best radiation direction of the signal of each antenna 231. In the main interference direction, the electromagnetic wave signal intensity of the antenna 231 is the highest, and the generated electromagnetic field intensity is the highest.

[0062] In one example, the present application can directly use the plane perpendicular to the radiation unit of the antenna 231 as the main interference direction of the antenna 231. Herein, step S33 can adjust the radiation unit of each antenna 231 to be perpendicular to the corresponding reference cross-section, so that the main interference direction of each antenna 231 is located on the corresponding reference cross-section. When the main interference direction is located on the corresponding reference cross-section, the interference signal generated by the corresponding antenna 231 best meets the test requirements.

[0063] In other examples, the method for determining the main interference direction of the antenna 231 includes:

[0064] First, determine a reference plane for each antenna 231. The reference plane can be the plane where the radiation unit of the antenna 231 is located or a plane parallel to the plane where the radiation unit of the antenna 231 is located; the main rotation direction corresponding to each antenna 231 will change with the orientation and azimuth of the antenna 231; then, obtain the signal transmission direction diagram of each antenna 231 on the corresponding reference plane. For example, the signal transmission direction diagram of the corresponding type of antenna 231 in the actual environment can be obtained through simulation testing. The signal transmission direction diagram obtained by simulation testing is in 3D form, and then obtain the pulse wave transmission direction on its reference plane and form a signal transmission direction diagram based on this; then, divide the signal transmission direction diagram into a plurality of regions arranged in an array, such as Figure 5 the multiple rectangular regions shown, and obtain the signal intensity difference between each region and the adjacent region in multiple directions; accumulate the signal intensity differences of all regions in the signal transmission direction diagram in multiple directions and obtain the sum of the accumulations; then, assign corresponding weight coefficients to the angles corresponding to each direction according to the sum of the signal intensity differences in multiple directions; finally, use the sum of the products of the angles corresponding to each direction and the corresponding weight coefficients as the main rotation direction.

[0065] Combined with Figure 5As shown, taking the signal transmission pattern of a single antenna 231 as a rectangle, and multiple directions including the horizontal direction, the vertical direction, and two bisecting directions (respectively the first bisecting direction and the second bisecting direction) between the horizontal direction and the vertical direction as examples, the sum of the accumulated signal intensity differences in the horizontal direction is K 1 , the sum of the accumulated signal intensity differences in the vertical direction is K 2 , the sum of the accumulated signal intensity differences in the first bisecting direction is K 3 , the sum of the accumulated signal intensity differences in the second bisecting direction is K 4 , according to the sum of the accumulated signal intensity differences K 1 、K 2 、K 3 、K 4 , calculate the corresponding weight coefficients x 1 、x 2 、x 3 、x 4 , and x 1 +x 2 +x 3 +x 4 =1; The sum S of the products of the angles corresponding to the horizontal direction, the vertical direction, the first bisecting direction, and the second bisecting direction and the corresponding weight coefficients, that is, S = x 1 *S 1 +x 2 *S 2 +x 3 *S 3 +x 4 *S 4 , S is used as the main direction of the trunk, S 1 、S 2 、S 3 、S 4 respectively represent the angles corresponding to the horizontal direction, the vertical direction, the first bisecting direction, and the second bisecting direction. For example, S 1 can be 180°, S 2 can be 90°, S 3 can be 45°, S 4 can be 135°.

[0066] Herein, step S33 can be achieved by continuously adjusting the orientation and azimuth of each antenna 231, and after the adjustment, obtaining the main interference direction of each antenna 231 according to the above method, and finally making the main interference direction of each antenna 231 located on the corresponding reference section. When the main interference direction is located on the corresponding reference section, the interference signal generated by the corresponding antenna 231 best meets the test requirements.

[0067] Please continue to refer to Figure 1, this application affects the storage chip through electromagnetic force, and characterizes the test results according to the error rate and / or speed (i.e., access speed) of the access results of the storage chip.

[0068] Taking the error rate as an example, in step S4, in the writing stage, a redundant code is generated based on the data of the access instruction, and the data of the access instruction and the redundant code are stored simultaneously; in the reading stage, the data and the redundant code are read out together, and the error is checked through the redundant code to obtain the error rate of the access result. Taking the speed as an example, in step S4, this application can detect whether there is an obvious extension in the erasing of the nor flash (flash memory) of the storage chip, etc., to obtain the access speed. According to the error rate and / or speed, the embodiments of this application can reproduce the interference factors of the storage chip, and by adjusting the preset characteristics of the interference signal, flexibly and effectively simulate the interference of the storage chip in the actual scenario, reproduce the performance problems that the storage chip may encounter, so as to facilitate the rapid positioning and in-depth analysis and improvement of related problems.

[0069] The embodiments of this application also provide a storage chip interference test device, including:

[0070] A test platform for establishing a connection with the storage chip;

[0071] An interference component for introducing an interference signal into the environment where the storage chip is located;

[0072] A controller, the interference component and the test platform are respectively connected to the controller.

[0073] For the specific structure and connection method between these structural elements, reference can be made to the foregoing Figure 2 example, which will not be elaborated here. Between the test platform, the interference component and the controller, the test of the storage chip is performed through the interference test method described in any of the foregoing embodiments.

[0074] The embodiments of this application also provide a storage medium, on which an interference test program is stored. This interference test program is essentially a computer program, and when this interference test program is executed by a processor, it realizes the steps of the interference test method in any example.

[0075] This storage medium includes but is not limited to any one of read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk and optical disc.

[0076] Since the program stored in the storage medium can execute the steps in the interference test method of any embodiment provided by this application, the beneficial effects achievable by the interference test method of any of the foregoing embodiments can be realized. For details, see the foregoing embodiments and will not be elaborated here.

[0077] An embodiment of this application also provides a storage chip, including a memory and a processor. An interference test program is stored on the memory. When the interference test program is executed by the processor, the steps of the interference test method of any of the foregoing embodiments are implemented; and / or, the storage chip is provided with a storage medium as in the above example, and the processor loads the storage medium to execute the steps of the interference test method, thereby realizing the beneficial effects achievable by the interference test method of the corresponding embodiment.

[0078] The above are only some embodiments of this application and do not limit the patent scope of this application. For those of ordinary skill in the art, any equivalent structural transformation made using the content of this specification and the drawings is equally included in the patent protection scope of this application.

[0079] In this article, step codes such as S1 and S2 are used. The purpose is to more clearly and briefly express the corresponding content and do not constitute a substantial limitation in order. Those skilled in the art may execute S2 first and then S1 in specific implementations, etc., but these should all be within the protection scope of this application.

[0080] Although terms such as "first" and "second" are used in this article to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. In addition, the singular forms "a", "an" and "the" are also intended to include the plural forms. The terms "or" and "and / or" are interpreted inclusively, or mean any one or any combination. An exception to this definition only occurs when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

Claims

1. A memory chip interference test method, characterized in that: include: Establishing a connection between the memory chip and the test platform; Introducing an interference signal into the environment where the memory chip is located, wherein the interference signal generates an electromagnetic field so that the memory chip is in an interference environment of the electromagnetic field; Adjusting the preset characteristics of the interference signal according to a preset rule, and sending an access instruction to the storage chip after the adjustment, so that the storage chip performs at least one of data reading, writing and erasing according to the access instruction; The test platform is controlled to obtain an error rate and / or speed of an access result of the storage chip, and the interference factor of the storage chip is reproduced according to the error rate and / or speed.

2. The method according to claim 1, characterized in that The preset characteristics of the interference signal include at least one of frequency, amplitude, power and modulation mode.

3. The method according to claim 2, characterized in that The adjusting the preset feature of the interference signal according to the preset rule includes at least one of the following: In a closed test room, controlling the interference signal to maintain a preset frequency and gradually adjusting the power; In an open test environment, the modulation mode of the interference signal is switched.

4. The method according to any one of claims 1 to 3, characterized in that An interference signal is introduced into the environment where the storage chip is located through the antenna array.

5. The method according to claim 4, characterized in that The adjusting the preset feature of the interference signal according to the preset rule includes: Taking the location of the memory chip as the intersection location, determining a plurality of reference cross sections; Obtain the main interference direction of each antenna; Each antenna is adjusted so that the main interference direction of each antenna is located on the corresponding reference cross section.

6. The method according to claim 5, characterized in that The angles between any two adjacent reference cross sections are equal.

7. The method according to claim 5, characterized in that The step of adjusting each antenna so that the main interference direction of each antenna is located on the corresponding reference cross section includes: The radiation elements of each antenna are adjusted to be perpendicular to the corresponding reference cross section.

8. The method according to claim 1, characterized in that The controlling the test platform to obtain the error rate of the access result of the storage chip includes: In the writing phase, a redundant code is generated based on the data of the access instruction; storing the data of the access instruction and the redundant code simultaneously; In the reading phase, the data and the redundant code are read out together, and errors are checked through the redundant code to obtain the error rate of the access result.

9. A memory chip interference test device, characterized in that: include: A test platform, used for establishing a connection with a memory chip; An interference component, used for introducing an interference signal into the environment where the memory chip is located; The controller, the interference component and the test platform are respectively connected to the controller, and the test platform, the interference component and the controller perform the test of the memory chip through the interference test method described in any one of claims 1 to 8.

10. A storage medium, characterized in that: An interference test program is stored, and when the interference test program is executed by a processor, the interference test method according to any one of claims 1 to 8 is implemented.

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