Heterogeneous wafer structure and preparation method thereof

Abstract

According to the preparation method of the heterogeneous wafer structure provided by the embodiment of the invention, the first bonding structure is provided; the first bonding structure comprises a first single crystal wafer, a first dielectric layer and a second single crystal wafer which are sequentially stacked, and a defect layer is arranged in the first single crystal wafer; providing a wafer structure; the wafer structure comprises a third single crystal wafer and a second dielectric layer located on the third single crystal wafer; etching the wafer structure from the surface of the second dielectric layer to form a symmetrical groove structure located on the surface of the third single crystal wafer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; bonding the first bonding structure and the wafer structure to obtain a second bonding structure; the second bonding structure is subjected to annealing treatment, so that the second bonding structure is peeled off along the defect layer, the heterogeneous wafer structure is obtained, the annealing temperature of preparation of the heterogeneous wafer structure is effectively improved through the method, and the bonding strength and the reuse frequency of the heterogeneous wafer structure are increased.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a heterogeneous wafer structure and a method for preparing the same. Background Art

[0002] Ion beam stripping and transfer technology is one of the best ways to achieve heterogeneous integration of physically mismatched materials. However, for large-sized and highly physically mismatched heterogeneous wafers, it is difficult to use the single bonding, stripping, and transfer method to prepare heterogeneous wafers. Usually, the heterogeneous wafers need to be bonded first, then thinned, and the heterogeneous wafer structure is used as a master wafer to achieve multiple stripping and transfer to prepare sub-wafers. However, due to the large size and large physical mismatch, the annealing temperature cannot be too high during the preparation of the heterogeneous wafer structure, otherwise there will be a risk of fragmentation. At the same time, when using the heterogeneous wafer structure bonding and stripping to prepare sub-wafers, due to the too large thermal stress, the thickness of the functional layer of the heterogeneous wafer structure itself is not easy to be too thick, otherwise there will be a risk of debonding. This seriously limits the number of uses of the heterogeneous wafer structure and increases the processing cost of the heterogeneous wafer structure.

[0003] Therefore, it is crucial to provide a heterogeneous wafer structure and a method for preparing the same to improve the disadvantages of being fragile and having a small functional layer thickness during the heterogeneous integration of large-sized and highly mismatched heterogeneous wafer structures caused by thermal pressure in the prior art, and to increase the reuse times of the heterogeneous wafer structure. Summary of the Invention

[0004] This application provides a heterogeneous wafer structure and a method for preparing the same to at least solve the above problems existing in the related art.

[0005] To solve the above technical problems, the technical solution of this application is as follows:

[0006] According to the first aspect of the embodiments of this application, a method for preparing a heterogeneous wafer structure is provided. The method includes:

[0007] Providing a first bonding structure; the first bonding structure includes a first single-crystal wafer, a first dielectric layer, and a second single-crystal wafer that are sequentially stacked, and a defect layer is provided in the first single-crystal wafer;

[0008] Providing a wafer structure; the wafer structure includes a third single-crystal wafer and a second dielectric layer located on the third single-crystal wafer;

[0009] Etching the wafer structure from the surface of the second dielectric layer to form a symmetric groove structure on the surface of the third single-crystal wafer; the depth of the symmetric groove structure is equal to the thickness of the second dielectric layer;

[0010] Perform a bonding process on the first bonding structure and the wafer structure along the surface of the first single-crystalline wafer and the surface of the second dielectric layer to obtain a second bonding structure;

[0011] Anneal the second bonding structure so that the second bonding structure peels off along the defect layer to obtain the heterogeneous wafer structure; the heterogeneous wafer structure includes the wafer structure and a part of the first single-crystalline wafer transferred onto the wafer structure.

[0012] In an optional embodiment, after annealing the second bonding structure at a high temperature so that the second bonding structure peels off along the defect layer to obtain the heterogeneous wafer structure, the preparation method further includes:

[0013] Chamfer the first single-crystalline wafer in the heterogeneous wafer structure to obtain a first chamfer;

[0014] Perform a planarization process on the surface of the first single-crystalline wafer in the heterogeneous wafer structure to remove the defect layer.

[0015] In an optional embodiment, providing the first bonding structure includes:

[0016] Provide a preset first single-crystalline wafer having an ion implantation surface;

[0017] Perform ion implantation on the preset first single-crystalline wafer along the ion implantation surface to form the defect layer at a preset depth of the preset first single-crystalline wafer;

[0018] Provide the second single-crystalline wafer and form the first dielectric layer on the surface of the second single-crystalline wafer to obtain a second wafer structure;

[0019] Bond the preset first single-crystalline wafer and the second wafer structure along the ion implantation surface and the surface of the first dielectric layer to obtain a preset first bonding structure;

[0020] Chamfer the preset first single-crystalline wafer in the preset first bonding structure to obtain a second chamfer located at the edge of the preset first single-crystalline wafer;

[0021] And perform a thinning process on the preset first single-crystalline wafer in the preset first bonding structure to obtain the first bonding structure including the first single-crystalline wafer, the first dielectric layer, and the second single-crystalline wafer from top to bottom.

[0022] In an optional embodiment, providing a wafer structure includes:

[0023] Provide the third single-crystalline wafer;

[0024] A second dielectric layer is formed on one side surface of the third single-crystalline wafer.

[0025] In an alternative embodiment, the first single-crystalline wafer, the second single-crystalline wafer, and the third single-crystalline wafer have the same size and are all greater than or equal to 4 inches.

[0026] In an alternative embodiment, the width of the symmetric trench structure is 1 μm - 20 μm, and the ends of the symmetric trench structure do not extend to the edge of the third single-crystalline wafer.

[0027] In an alternative embodiment, the material of the first dielectric layer is at least one of silicon oxide, polysilicon, silicon nitride, and aluminum oxide; the first dielectric layer and the second dielectric layer have the same material and equal thicknesses;

[0028] The material of the second single-crystalline wafer includes any one of silicon, silicon carbide, diamond, sapphire, and quartz; the second single-crystalline wafer and the third single-crystalline wafer have the same material and equal thicknesses;

[0029] The first single-crystalline wafer includes any one of gallium oxide, lithium niobate, lithium tantalate, silicon carbide, indium phosphide, gallium arsenide, gallium antimonide, indium antimonide, and gallium nitride.

[0030] In an alternative embodiment, the width of the first chamfer is less than the distance between the end of the symmetric trench and the edge of the first single-crystalline wafer;

[0031] The depth of the first chamfer is greater than the thickness of the first single-crystalline wafer and less than the sum of the thicknesses of the first single-crystalline wafer and the second dielectric layer.

[0032] In an alternative embodiment, the distance between the end of the symmetric trench and the edge of the first single-crystalline wafer is greater than the width of the second chamfer;

[0033] The thickness of the first single-crystalline wafer is 3 μm - 50 μm.

[0034] In a second aspect of the embodiments of the present application, a heterogeneous wafer structure is provided, and the heterogeneous wafer structure includes:

[0035] A third single-crystalline wafer;

[0036] A second dielectric layer, located on the surface of the third single-crystalline wafer, and a symmetric trench structure is provided in the second dielectric layer; the depth of the symmetric trench structure is equal to the thickness of the second dielectric layer;

[0037] A first single-crystalline wafer, located on the surface of the second dielectric layer.

[0038] The present application provides a heterogeneous wafer structure and a preparation method thereof. Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0039] The preparation method of the heterogeneous wafer structure provided by the embodiment of the present application includes: providing a first bonding structure, where the first bonding structure includes a first single-crystal wafer, a first dielectric layer, and a second single-crystal wafer stacked in sequence, and a defect layer is provided in the first single-crystal wafer; providing a wafer structure, where the wafer structure includes a third single-crystal wafer and a second dielectric layer on the third single-crystal wafer; etching the wafer structure from the surface of the second dielectric layer to form a symmetric trench structure on the surface of the third single-crystal wafer, where the depth of the symmetric trench structure is equal to the thickness of the second dielectric layer; performing a bonding process on the first bonding structure and the wafer structure along the surface of the first single-crystal wafer and the surface of the second dielectric layer to obtain a second bonding structure; performing a high-temperature annealing process on the second bonding structure to peel the second bonding structure along the defect layer to obtain a heterogeneous wafer structure. The heterogeneous wafer structure can be used as a master wafer for ion beam peeling and transfer technology. During the formation of the master wafer, the introduction of the trench structure can effectively reduce the thermal stress, increase the annealing temperature for preparing the master wafer, increase the bonding strength of the master wafer, and at the same time enable the preparation of a thicker master wafer and increase the reuse times of the master wafer. Moreover, the trench structure adopts a symmetric structure, which can uniformly release the stress, avoid cracking of the first single-crystal wafer due to uneven stress release, and adopt double-sided same-structure bonding during the preparation of the master wafer, which can effectively balance the stress on both sides of the first single-crystal wafer, further reduce the risk of high-temperature annealing fragmentation, and enable the prepared heterogeneous wafer structure to be reused multiple times.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 is a schematic flow chart of a preparation method of a heterogeneous wafer structure provided by an embodiment of the present application.

[0043] Figure 2 is a schematic structural diagram of a first bonding structure provided by an embodiment of the present application.

[0044] Figure 3 is a schematic structural diagram of a wafer structure provided by an embodiment of the present application.

[0045] Figure 4 It is a schematic structural diagram of a second bonding structure provided by an embodiment of the present application.

[0046] Figure 5 It is a schematic structural diagram of an annealing process provided by an embodiment of the present application.

[0047] Figure 6 It is a schematic structural diagram of a heterogeneous wafer structure provided by an embodiment of the present application.

[0048] Figure 7 It is a schematic structural diagram of a heterogeneous wafer structure after chamfering provided by an embodiment of the present application.

[0049] Figure 8 It is a schematic structural diagram of a heterogeneous wafer structure after planarization provided by an embodiment of the present application.

[0050] Figure 9 It is a schematic structural diagram of a reuse process of a heterogeneous wafer structure provided by an embodiment of the present application.

[0051] Figure 10 It is a schematic flow diagram of a preparation process of a first bonding structure provided by an embodiment of the present application.

[0052] The following is an explanation of the reference numerals:

[0053] 100 - First single - crystal wafer; 101 - Defect layer;

[0054] 200 - Second single - crystal wafer;

[0055] 300 - First dielectric layer;

[0056] 400 - Third single - crystal wafer;

[0057] 500 - Second dielectric layer; 501 - Symmetric trench structure; Detailed implementation manners

[0058] The following provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below in a simplified manner. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present application may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0059] In addition, spatial relative terms, such as "below...", "beneath", "lower", "...above", "upper", "front", "back", "...over" and similar terms, may be used in the present application for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than the orientation depicted in the figures.

[0060] As described in the background art, in the physical mismatch material heterogeneous integration, the ion beam stripping and transfer technology is one of the best paths. When it is applied to the integration of large-size and large-physical-mismatch heterogeneous wafers, due to the large size and large physical mismatch, the annealing temperature in the preparation process of the mother wafer cannot be too high, resulting in a high risk of mother wafer fragmentation. And when preparing the daughter wafer by bonding and stripping the mother wafer, due to the too large thermal stress, the number of times the mother wafer can be used is severely limited, and the processing cost of the mother wafer is increased.

[0061] It should be noted that in the embodiments of the present application, large physical mismatch is equivalent to large mismatch, which means that in the fields of materials science and semiconductors, due to the large difference in lattice constants between the substrate and the epitaxial layer, it is difficult for the epitaxial layer to perfectly match the lattice structure of the substrate. This mismatch will cause stress accumulation and the generation of crystal defects (such as dislocations), thereby affecting the electrical, optical and other properties of the material. Large size means that the diameter of the wafer is large. The use of such large-size wafers can significantly improve production efficiency, reduce costs, and meet the needs of large-scale integrated circuit manufacturing.

[0062] Based on this, the embodiments of the present application provide a method for preparing a heterogeneous wafer structure, as Figure 1 shown, the preparation method includes:

[0063] S11: Provide a first bonding structure; the first bonding structure includes a first single-crystal wafer 100, a first dielectric layer 300, and a second single-crystal wafer 200 stacked in sequence, and a defect layer 101 is provided in the first single-crystal wafer 100.

[0064] In the embodiments of the present application, the first bonding structure can be a structure obtained after a series of processing techniques. Specifically, as Figure 2 shown, the first bonding structure is at least sequentially from bottom to the second single-crystal wafer 200, the first dielectric layer 300, and the first single-crystal wafer 100. Optionally, the sizes of the first single-crystal wafer 100 and the second single-crystal wafer 200 are the same.

[0065] Optionally, there is a large difference in lattice constants between the materials of the first single-crystal wafer and the second single-crystal wafer in the present application, that is, it satisfies large mismatch.

[0066] S13: Provide a wafer structure; the wafer structure includes a third single-crystalline wafer 400 and a second dielectric layer 500 located on the third single-crystalline wafer 400.

[0067] In an embodiment of the present application, the wafer structure includes a third single-crystalline wafer 400 and a second dielectric layer 500 located on the surface of the third single-crystalline wafer 400.

[0068] S15: Etch the wafer structure from the surface of the second dielectric layer 500 to form a symmetric trench structure 501 located on the surface of the third single-crystalline wafer 400; the depth of the symmetric trench structure 501 is equal to the thickness of the second dielectric layer 500.

[0069] In an embodiment of the present application, after obtaining the wafer structure, using one side surface of the second dielectric layer 500 as the etching surface, specifically, using the side surface of the second dielectric layer 500 away from the third wafer structure as the etching surface, etch the second dielectric layer 500 in the wafer structure to form a symmetric trench structure 501 located in the second dielectric layer 500. Specifically, as Figure 3 shown, and the depth of the symmetric trench structure 501 is equal to the thickness of the second dielectric layer 500.

[0070] The symmetric trench structure 501 refers to an axisymmetric trench structure, and the axis in the axisymmetry passes through the center of the third single-crystalline wafer 400. Optionally, the symmetric trench structure 501 can be Figure 3 the "rice" shape shown, that is, the symmetric trench structure 501 includes 4 trenches passing through the center of the circle, and the included angle between each trench is 45°; the symmetric trench can also be other shapes, for example, a total of 6 trenches passing through the center of the circle are prepared, and the included angle between each trench is 30°. It can also be a "field" - shaped trench, etc.

[0071] Optionally, the etching process uses photolithography technology. Specifically, prepare a photoresist on the surface of the second dielectric layer 500, pattern the photoresist, transfer the preset symmetric trench structure 501 to the photoresist, and then use the patterned photoresist as a mask and the surface of the third single-crystalline wafer 400 as an etching stop layer to etch the second dielectric layer 500 to obtain the symmetric trench structure 501 located on the surface of the third single-crystalline wafer 400.

[0072] In an embodiment of the present application, the introduction of the trench structure plays a role in releasing thermal stress during the subsequent bonding annealing process. Therefore, the annealing temperature of the master wafer preparation can be increased, the bonding strength of the master wafer can be increased, and at the same time, the preparation of a thicker master wafer can be achieved, increasing the reuse times of the master wafer; and the trench structure is symmetric, enabling the stress to be released evenly, avoiding cracking of the wafer due to uneven stress release.

[0073] In an optional embodiment, the width of the symmetric trench structure 501 is 1 μm - 20 μm, and the ends of the symmetric trench structure 501 do not extend to the edge of the third single-crystal wafer 400.

[0074] In the embodiments of the present application, the width of the symmetric trench is set between 1 μm and 20 μm. Specifically, it means that the width of each trench in the symmetric trench structure 501 is between 1 μm and 20 μm, and the ends of the symmetric trench structure 501 do not extend to the ends of the third single-crystal wafer 400, that is, the trench does not extend to the wafer edge to communicate with the atmosphere. This is to prevent the hetero-wafer structure from cracking at the edge trench during the subsequent preparation process or after the preparation, and at the same time ensure that the hetero-wafer structure prepared will not introduce difficult-to-remove dirt in the trench during the subsequent cleaning process.

[0075] Optionally, the distance between the ends of the symmetric trench structure 501 and the edge of the third single-crystal wafer 400 is ≥ 3 mm.

[0076] S17: Bond the first bonding structure and the wafer structure along the surfaces of the first single-crystal wafer 100 and the second dielectric layer 500 to obtain a second bonding structure.

[0077] In the embodiments of the present application, bonding treatment is performed with the surface of the first single-crystal wafer 100 in the first bonding structure and the surface of the second dielectric layer 500 of the wafer structure as the bonding surfaces to obtain a second bonding structure. The structural schematic diagram of the second bonding structure is as Figure 4 shown. From top to bottom, the second bonding structure is successively the third single-crystal wafer 400, the second dielectric layer 500, the first single-crystal wafer 100, the first dielectric layer 300, and the second single-crystal wafer 200; there is a defect layer 101 formed by ion implantation inside the first single-crystal wafer 100, and a symmetric trench structure 501 is provided in the second dielectric layer 500.

[0078] Optionally, the bonding treatment method adopts the prior art and is not specifically limited in the present application.

[0079] The specific process conditions of the bonding treatment are determined according to the size of the first single-crystal wafer 100 and the materials of the first single-crystal wafer 100, the second dielectric layer 500, and the third single-crystal wafer 400.

[0080] In the embodiments of the present application, during the preparation process of the hetero-wafer structure, double-sided same-structure bonding is adopted on both sides of the first single-crystal wafer 100, which can effectively balance the stress on both sides of the first single-crystal wafer 100 and further reduce the risk of fragmentation during the subsequent high-temperature annealing process.

[0081] S19: Anneal the second bonding structure so that the second bonding structure peels along the defect layer 101 to obtain the heterogeneous wafer structure; the heterogeneous wafer structure includes the wafer structure and a part of the first single-crystalline wafer 100 transferred onto the wafer structure.

[0082] In the embodiments of the present application, as Figure 5 shown, after obtaining the second bonding structure, perform high-temperature annealing on the second bonding structure to make the second bonding structure peel along the defect layer 101 to obtain a heterogeneous wafer structure and a target heterogeneous wafer structure. Among them, the heterogeneous wafer structure is the master wafer of the ion beam peeling and transfer technology and can be reused multiple times for preparing the target heterogeneous wafer, while the target heterogeneous wafer is the sub-wafer, that is, the heterogeneous integrated material prepared this time.

[0083] Specifically, the heterogeneous wafer structure includes the wafer structure and a part of the first single-crystalline wafer 100 transferred onto the wafer structure, that is, the heterogeneous wafer structure from top to bottom is the first single-crystalline wafer 100, the second dielectric layer 500, and the third single-crystalline wafer 400 in sequence, and a symmetric trench structure 501 is provided in the second dielectric layer 500, and there may be a residual defect layer 101 on the surface of the first single-crystalline wafer 100. As Figure 6 shown, the target heterogeneous wafer structure includes the second single-crystalline wafer 200, the first dielectric layer 300, and the first single-crystalline wafer 100 stacked in sequence.

[0084] Optionally, the heterogeneous wafer structure can be used directly or after post-processing as the master wafer for the next bonding of the first single-crystalline wafer 100 and the second single-crystalline wafer 200, which improves the usage times of the master wafer in the ion beam peeling and transfer technology and reduces the processing cost of the master wafer.

[0085] It should be noted that the master wafer prepared by the above method can be reused at least 3 more times, that is, the reuse times of the heterogeneous wafer structure provided in the embodiments of the present application ≥ 3.

[0086] The method for preparing a heterogeneous wafer structure provided by an embodiment of the present application includes providing a first bonding structure; the first bonding structure includes a first single-crystalline wafer 100, a first dielectric layer 300, and a second single-crystalline wafer 200 that are sequentially stacked, and a defect layer 101 is provided in the first single-crystalline wafer 100; providing a wafer structure; the wafer structure includes a third single-crystalline wafer 400 and a second dielectric layer 500 located on the third single-crystalline wafer 400; etching the wafer structure from the surface of the second dielectric layer 500 to form a symmetric trench structure 501 on the surface of the third single-crystalline wafer 400; the depth of the symmetric trench structure 501 is equal to the thickness of the second dielectric layer 500; performing a bonding process on the first bonding structure and the wafer structure along the surface of the first single-crystalline wafer 100 and the surface of the second dielectric layer 500 to obtain a second bonding structure; performing a high-temperature annealing process on the second bonding structure to cause the second bonding structure to peel along the defect layer 101 to obtain a heterogeneous wafer structure. The heterogeneous wafer structure can be used as a master wafer for ion beam peeling and transfer technology. During the formation of the master wafer, the introduction of the trench structure can effectively reduce the thermal stress, increase the annealing temperature for master wafer preparation, increase the bonding strength of the master wafer, and at the same time enable the preparation of a thicker master wafer and increase the reuse times of the master wafer; and the trench structure adopts a symmetric structure, which can evenly release stress, avoid cracking of the first single-crystalline wafer 100 due to uneven stress release, and adopt double-sided same-structure bonding during the preparation of the master wafer, which can effectively balance the stress magnitudes on both sides of the first single-crystalline wafer 100, further reduce the risk of high-temperature annealing fragments, and enable the prepared heterogeneous wafer structure to be reused multiple times.

[0087] In an optional embodiment, the first single-crystalline wafer 100, the second single-crystalline wafer 200, and the third single-crystalline wafer 400 have the same size and are all greater than or equal to 4 inches.

[0088] In an optional embodiment, the material of the first dielectric layer 300 is at least one of silicon oxide, polysilicon, silicon nitride, and aluminum oxide; the first dielectric layer 300 and the second dielectric layer 500 have the same material and equal thickness;

[0089] The material of the second single-crystalline wafer 200 includes any one of silicon, silicon carbide, diamond, sapphire, and quartz; the second single-crystalline wafer 200 and the third single-crystalline wafer 400 have the same material and equal thickness;

[0090] The first single-crystalline wafer 100 includes any one of gallium oxide, lithium niobate, lithium tantalate, silicon carbide, indium phosphide, gallium arsenide, gallium antimonide, indium antimonide, and gallium nitride.

[0091] In the embodiments of the present application, the above preparation method is applicable to the integration process of large-sized heterogeneous wafers. The large size specifically means that the sizes of the first single-crystal wafer 100, the second single-crystal wafer 200, and the third single-crystal wafer 400 are the same and are all greater than or equal to 4 inches.

[0092] Optionally, the sizes of the first single-crystal wafer 100, the second single-crystal wafer 200, and the third single-crystal wafer 400 are preferably 4 - 12 inches.

[0093] Furthermore, in order to ensure that the bonding structures on both sides of the first single-crystal wafer 100 are exactly the same, the materials and thicknesses of the second single-crystal wafer 200, the third single-crystal wafer 400, the first dielectric layer 300, and the second dielectric layer 500 are controlled to be exactly the same. In this way, the double-sided same-structure bonding is adopted in the mother wafer preparation process, which can effectively balance the stress on both sides of the first single-crystal wafer 100 and further reduce the risk of fragmentation during the subsequent high-temperature annealing process.

[0094] It should be noted that the material selection of the first single-crystal wafer 100 and the second single-crystal wafer 200 results in a large lattice mismatch and a large difference in thermal expansion coefficient between the first single-crystal wafer 100 and the second single-crystal wafer 200. That is to say, there is a large mismatch between the first single-crystal wafer 100 and the second single-crystal wafer 200, or between the first single-crystal wafer 100 and the third single-crystal wafer 400.

[0095] In the embodiments of the present application, by limiting the sizes, materials, and thicknesses of the first single-crystal wafer 100, the second single-crystal wafer 200, and the third single-crystal wafer 400, the above preparation method can be applicable to the application scenarios of large-sized and large-mismatch heterogeneous wafer integration. And by ensuring that the double-sided same-structure bonding is adopted in the mother wafer preparation process, the stress on both sides of the first single-crystal wafer 100 can be effectively balanced, and the risk of fragmentation during high-temperature annealing can be further reduced.

[0096] In an optional embodiment, after the above step S19, the above preparation method further includes:

[0097] S21: Chamfer the first single-crystal wafer 100 in the heterogeneous wafer structure to obtain a first chamfer.

[0098] S23: Planarize the surface of the first single-crystal wafer 100 in the heterogeneous wafer structure to remove the defective layer 101.

[0099] In an optional embodiment, in the above step S21, the width of the first chamfer is less than the distance between the end of the symmetric groove and the edge of the first single-crystal wafer 100;

[0100] The depth of the first chamfer is greater than the thickness of the first single-crystalline wafer 100 and less than the sum of the thicknesses of the first single-crystalline wafer 100 and the second dielectric layer 500.

[0101] In the embodiment of the present application, in the above step S21, the obtained heterogeneous wafer structure (i.e., the master wafer) is chamfered to obtain a structure as Figure 7 shown, which can prevent film peeling at the edge of the master wafer during subsequent reuse and improve the mechanical strength.

[0102] Optionally, the chamfering process mainly includes the following steps:

[0103] (1) Cleaning: Remove the dirt and impurities on the surface of the first single-crystalline wafer 100 to ensure the cleanliness of the chamfered surface.

[0104] (2) Positioning: Fix the heterogeneous wafer structure on the workbench using a precision positioning system.

[0105] (3) Processing: Round the acute angle at the edge of the first single-crystalline wafer 100 by mechanical grinding or chemical etching.

[0106] (4) Detection: Detect the chamfered first single-crystalline wafer 100, including parameters such as surface roughness and angle size, to ensure the expected effect.

[0107] In the embodiment of the present application, the depth of the first chamfer is greater than the thickness of the first single-crystalline wafer 100 and less than the sum of the thicknesses of the first single-crystalline wafer 100 and the second dielectric layer 500, which is to ensure that the first chamfer extends into the second dielectric layer 500. Further, control the chamfer width to be less than the width from the top of the trench to the surface of the first single-crystalline wafer 100, which can maintain the integrity of the edge of the master wafer, prevent cracking during subsequent reuse of the master wafer, and also ensure that no difficult-to-remove dirt is introduced into the trench during subsequent cleaning of the master wafer.

[0108] In the above step S23, the present application also needs to planarize one side surface of the first single-crystalline wafer 100 of the heterogeneous wafer structure to remove the residual defect layer 101 on the surface of the first single-crystalline wafer 100, forming a reusable master wafer, as Figure 8 shown. This master wafer can be reused multiple times through implantation, bonding, and peeling, and multiple sub-wafers can be fabricated. Since there is a symmetric trench structure 501 in the master wafer, the thermal stress can be greatly released. Therefore, even a relatively thick master wafer will not debond during the peeling annealing process, increasing the reuse times of the master wafer.

[0109] Optionally, the embodiments of the present application do not limit the method of planarization. For example, the planarization process may be one or more of mechanical grinding and polishing, chemical mechanical polishing (CMP), plasma etching, high-temperature heat treatment, etc.

[0110] In an alternative embodiment, after the above step S23, the embodiments of the present application further include a method for reusing a heterogeneous wafer structure, as Figure 9 shown, the specific process includes:

[0111] S25: Using the surface of the first single-crystal wafer 100 away from the second single-crystal wafer 200 as a new ion implantation surface, perform ion implantation on the first single-crystal wafer 100 in the heterogeneous wafer structure to form a new defect layer 101, or an ion implantation loss layer, in the first single-crystal wafer 100.

[0112] S26: Provide a new wafer structure, where the new wafer structure includes the second single-crystal wafer 200 and a first dielectric layer 300 on the surface of the second single-crystal wafer 200. That is to say, the new wafer structure is exactly the same as the wafer structure in step S13.

[0113] S27: Using the surface of the first dielectric layer 300 and the surface of the first single-crystal wafer 100 as bonding surfaces, bond the heterogeneous wafer structure and the new wafer structure to obtain a third bonded structure. The structure of the third bonded structure is the same as that of the second bonded structure, except that the thickness of the first single-crystal wafer 100 in the third bonded structure is less than the thickness of the first single-crystal wafer 100 in the second wafer.

[0114] S28: Perform high-temperature annealing treatment on the third bonded structure to cause the third bonded structure to peel along the defect layer 101, obtaining a new heterogeneous wafer structure and a target wafer structure.

[0115] S29: Perform chamfering treatment and planarization treatment on the new heterogeneous wafer structure to obtain a reusable master wafer.

[0116] It can be understood that the above processes S25 - S29 are actually exactly the same as steps S11 - S23, that is, it can be described as repeating steps S11 - S23, which is the reuse process of the heterogeneous wafer structure.

[0117] In an alternative embodiment, in the above step S11, the above providing the first bonded structure includes:

[0118] S111: Provide a preset first single-crystal wafer 100, where the preset first single-crystal wafer 100 has an ion implantation surface.

[0119] S112: Perform ion implantation on the preset first single-crystal wafer 100 along the ion implantation surface, so as to form the defect layer 101 at a preset depth of the preset first single-crystal wafer 100.

[0120] S113: Provide the second single-crystal wafer 200, and form the first dielectric layer 300 on the surface of the second single-crystal wafer 200 to obtain a second wafer structure;

[0121] S114: Bond the preset first single-crystal wafer 100 and the second wafer structure along the ion implantation surface and the surface of the first dielectric layer 300 to obtain a preset first bonding structure;

[0122] S115: Chamfer the preset first single-crystal wafer 100 in the preset first bonding structure to obtain a second chamfer at the edge of the preset first single-crystal wafer 100;

[0123] S116: And thin the preset first single-crystal wafer 100 in the preset first bonding structure to obtain the first bonding structure which from top to bottom is the first single-crystal wafer 100, the first dielectric layer 300 and the second single-crystal wafer 200.

[0124] The following will specifically describe the first bonding structure of the present invention and its preparation in conjunction with the attached drawing x.

[0125] In step S111, the preset first single-crystal wafer 100 refers to a wafer that has not undergone any treatment, has the same material as the first single-crystal wafer 100, and the preset first single-crystal wafer 100 has an ion implantation surface. Specifically, the preset first single-crystal wafer 100 has an upper surface and a lower surface, both of which can be used as the ion implantation surface.

[0126] In step S112, ion implantation is performed on the ion implantation surface to form a defect layer 101 at a preset depth in the preset first single-crystal wafer 100.

[0127] Optionally, the method of performing the ion implantation includes any one of hydrogen ion implantation, helium ion implantation, and co-implantation of hydrogen and helium ions.

[0128] Specifically, the preset depth refers to the distance between the defect layer 101 formed after ion implantation and the ion implantation surface of the preset single-crystal wafer. The preset depth is set according to the structure of the sub-wafer to be actually prepared. When ions are implanted from the implantation surface, the energy of the ion implantation is sufficient to enable the implanted ions to reach this preset depth and form the implanted defect layer 101 at the preset depth.

[0129] In step S113, a second single-crystal wafer 200 is provided, and a first dielectric layer 300 is formed on the surface of the second single-crystal wafer 200, thereby forming the second wafer structure.

[0130] Optionally, the method for forming the first dielectric layer 300 includes, but is not limited to, deposition, in-situ growth, etc.

[0131] Optionally, after the first dielectric layer 300 is formed, post-treatments such as planarization and thinning can be performed on it.

[0132] In step S114, the surface of the first dielectric layer 300 of the second wafer structure is bonded to the ion implantation surface of a preset first single-crystal wafer 100 to obtain a preset first bonding structure. Specifically, the preset first bonding structure

[0133] Optionally, the bonding process uses existing technologies and is not specifically limited in this application.

[0134] In step S115, chamfering is performed on one side of the preset first single-crystal wafer 100 in the preset first bonding structure to obtain a second chamfer at the edge of the preset first single-crystal wafer 100. The depth of the second chamfer is not specifically limited in this application and is determined according to the actual application scenario.

[0135] In step S116, thinning and surface planarization are performed on the surface of one side of the preset first single-crystal wafer 100 in the obtained preset first bonding structure to obtain a first bonding structure. The first bonding structure includes, from top to bottom, a first single-crystal wafer 100, a first dielectric layer 300, and a second single-crystal wafer 200. Herein, the first single-crystal wafer 100 refers to the structure of the preset first single-crystal wafer 100 after chamfering and thinning.

[0136] Optionally, the planarization process includes polishing.

[0137] In the embodiments of this application, by thinning the first single-crystal wafer 100 first during the preparation of the first bonding structure, the thermal stress during the subsequent preparation of the heterogeneous wafer structure can be effectively reduced, and the mechanical stability of the heterogeneous wafer structure can be improved.

[0138] In an optional embodiment, the distance between the end of the symmetric groove and the edge of the first single-crystal wafer 100 is greater than the width of the second chamfer;

[0139] The thickness of the first single-crystal wafer 100 is 3 μm - 50 μm.

[0140] In the embodiments of the present application, since the preparation processes of the first bonding structure and the wafer structure are two independent processes, during the preparation process, it is necessary to control the distance between the end of the symmetric trench structure 501 and the edge of the first single-crystal wafer 100 to be greater than the width of the second chamfer, so as to ensure that the end of the symmetric trench structure 501 does not communicate with the edge of the first single-crystal wafer 100, thereby ensuring the integrity of the edge of the master wafer, avoiding the master wafer from cracking along the trench from the edge, and at the same time ensuring that no dirt is introduced into the trench during the subsequent cleaning process of the master wafer.

[0141] In an alternative embodiment, in the above step S13, providing a wafer structure includes:

[0142] S131: Providing the third single-crystal wafer 400;

[0143] S132: Forming a second dielectric layer 500 on one side surface of the third single-crystal wafer 400.

[0144] In the embodiments of the present application, the third single-crystal wafer 400 and the second single-crystal wafer 200 have the same material and thickness, and the second dielectric layer 500 and the first dielectric layer 300 have the same material and thickness.

[0145] Optionally, the preparation method of the second dielectric layer 500 includes but is not limited to deposition, in-situ growth, etc.

[0146] In the embodiments of the present application, a wafer structure is prepared through the above process. The wafer structure is exactly the same as the structure on one side of the first single-crystal wafer 100 in the first bonding. In this way, it can be ensured that after the wafer structure and the first bonding structure are bonded, the structures on both sides of the first single-crystal wafer 100 are exactly the same.

[0147] The embodiments of the present application further provide a heterogeneous wafer structure. The heterogeneous wafer structure is formed based on the preparation method described in any of the above embodiments. The heterogeneous wafer structure includes:

[0148] A third single-crystal wafer 400;

[0149] A second dielectric layer 500, located on the surface of the third single-crystal wafer 400, and a symmetric trench structure 501 is provided in the second dielectric layer 500; the depth of the symmetric trench structure 501 is equal to the thickness of the second dielectric layer 500;

[0150] A first single-crystal wafer 100, located on the surface of the second dielectric layer 500.

[0151] In an alternative embodiment, the edge of the first single-crystal wafer 100 has a first chamfer, and the width of the first chamfer is less than the distance between the end of the symmetric trench and the edge of the first single-crystal wafer 100;

[0152] The depth of the first chamfer is greater than the thickness of the first single-crystalline wafer 100 and less than the sum of the thicknesses of the first single-crystalline wafer 100 and the second dielectric layer 500.

[0153] In an optional embodiment, the width of the symmetric trench structure 501 is 1 μm - 20 μm, and the end of the symmetric trench structure 501 does not extend to the edge of the third single-crystalline wafer 400.

[0154] In an optional embodiment, the first single-crystalline wafer 100 and the third single-crystalline wafer 400 have the same size and are both greater than or equal to 4 inches.

[0155] In an optional embodiment, the first single-crystalline wafer 100 includes any one of gallium oxide, lithium niobate, lithium tantalate, silicon carbide, indium phosphide, gallium arsenide, gallium antimonide, indium antimonide, and gallium nitride;

[0156] The material of the second dielectric layer 500 is at least one of silicon oxide, polysilicon, silicon nitride, and aluminum oxide;

[0157] The material of the third single-crystalline wafer 400 includes any one of silicon, silicon carbide, diamond, sapphire, and quartz.

[0158] The heterogeneous wafer structure provided by the embodiments of the present application can be used as a master wafer for large-size and large-mismatch heterogeneous wafer integration, so that a semiconductor structure including the first single-crystalline wafer 100 can be prepared.

[0159] The embodiments of the present application further provide an electronic device, and the electronic device includes a semiconductor structure prepared by using the above heterogeneous wafer structure.

[0160] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the protection scope of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, it is not limited to the embodiments listed. Those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the essence and scope of the technical solutions of the present invention.

Claims

1. A method for preparing a heterogeneous wafer structure, characterized in that: The preparation method comprises: Providing a first bonding structure; the first bonding structure comprises a first single crystal wafer, a first dielectric layer, and a second single crystal wafer which are stacked in sequence, and a defect layer is provided in the first single crystal wafer; Providing a wafer structure; the wafer structure comprises a third single crystal wafer and a second dielectric layer located on the third single crystal wafer; Etching the wafer structure from the surface of the second dielectric layer to form a symmetrical groove structure located on the surface of the third single crystal wafer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; Performing a bonding process on the first bonding structure and the wafer structure along a surface of the first single crystal wafer and a surface of the second dielectric layer to obtain a second bonding structure; The second bonding structure is annealed to peel off the second bonding structure along the defective layer to obtain the heterogeneous wafer structure; the heterogeneous wafer structure includes the wafer structure and a portion of the first single crystal wafer transferred to the wafer structure.

2. The preparation method according to claim 1, characterized in that: After the second bonding structure is subjected to high temperature annealing so as to be peeled off along the defective layer to obtain the heterogeneous wafer structure, the preparation method further includes: Performing chamfering processing on the first single crystal wafer in the heterogeneous wafer structure to obtain a first chamfer; The surface of the first single crystal wafer in the heterogeneous wafer structure is planarized to remove the defective layer.

3. The preparation method according to claim 1, characterized in that: The providing of a first bonding structure comprises: Providing a preset first single crystal wafer, wherein the preset first single crystal wafer has an ion implantation surface; Performing ion implantation on the preset first single crystal wafer along the ion implantation surface to form the defect layer at a preset depth of the preset first single crystal wafer; Providing the second single crystal wafer, and forming the first dielectric layer on the surface of the second single crystal wafer to obtain a second wafer structure; Bonding the preset first single crystal wafer and the second wafer structure along the ion implantation surface and the surface of the first dielectric layer to obtain a preset first bonding structure; Performing chamfering processing on the preset first single crystal wafer in the preset first bonding structure to obtain a second chamfer located at the edge of the preset first single crystal wafer; And the preset first single crystal wafer in the preset first bonding structure is thinned to obtain the first bonding structure which is the first single crystal wafer, the first dielectric layer and the second single crystal wafer from top to bottom.

4. The preparation method according to claim 1, characterized in that: The invention provides a wafer structure, comprising: Providing the third single crystal wafer; A second dielectric layer is formed on a surface of one side of the third single crystal wafer.

5. The preparation method according to claim 1, characterized in that: The first single crystal wafer, the second single crystal wafer and the third single crystal wafer have the same size and are all greater than or equal to 4 inches.

6. The preparation method according to claim 1, characterized in that: The width of the symmetrical groove structure is 1 μm-20 μm, and the end of the symmetrical groove structure does not extend to the edge of the third single crystal wafer.

7. The preparation method according to claim 1, characterized in that: The material of the first dielectric layer is at least one of silicon oxide, polysilicon, silicon nitride, and aluminum oxide; the first dielectric layer and the second dielectric layer are made of the same material and have the same thickness; The material of the second single crystal wafer includes any one of silicon, silicon carbide, diamond, sapphire, and quartz; the material of the second single crystal wafer and the third single crystal wafer are the same, and the thickness is equal; The first single crystal wafer includes any one of gallium oxide, lithium niobate, lithium tantalate, silicon carbide, indium phosphide, gallium arsenide, gallium antimonide, indium antimonide, and gallium nitride.

8. The preparation method according to claim 2, characterized in that: The width of the first chamfer is smaller than the distance between the end of the symmetrical groove and the edge of the first single crystal wafer; The depth of the first chamfer is greater than the thickness of the first single crystal wafer and less than the sum of the thicknesses of the first single crystal wafer and the second dielectric layer.

9. The preparation method according to claim 3, characterized in that: The distance between the end of the symmetrical groove and the edge of the first single crystal wafer is greater than the width of the second chamfer; The thickness of the first single crystal wafer is 3 μm-50 μm.

10. A heterogeneous wafer structure, characterized in that: The heterogeneous wafer structure comprises: The third single crystal wafer; A second dielectric layer is located on the surface of the third single crystal wafer, and a symmetrical groove structure is provided in the second dielectric layer; the depth of the symmetrical groove structure is equal to the thickness of the second dielectric layer; The first single crystal wafer is located on the surface of the second dielectric layer.

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