Broadband gain-controllable limiting amplifier circuit and optical module

Abstract

The embodiment of the invention provides a broadband gain-controllable limiting amplifier circuit and an optical module. The broadband gain-controllable limiting amplifier circuit comprises a plurality of differential amplification modules which are connected in series and used for amplifying input signals step by step; the differential amplification module comprises a differential amplification circuit, a proportional current source and a current adjusting circuit, and the proportional current source is used for outputting a second current at an output end of the proportional current source according to a preset proportion and a first current input at an input end of the proportional current source to serve as a tail current of the differential amplification circuit; the current adjusting circuit comprises a plurality of parallel current sources for inputting current to the input end of the proportional current source, at least one of the parallel current sources is provided with a corresponding switch component, and the switch component is used for switching on or switching off the current input to the input end of the proportional current source by the corresponding current source so as to adjust the first current.

Description

[0001] Related Applications

[0002] This application claims the priority of the Chinese patent application with the application number 2024209228671 and the title "Wideband Gain-Controllable Limiting Amplifier Circuit and Optical Module", which was filed on April 29, 2024. The entire text thereof is incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of optical communications, and in particular, to a wideband gain-controllable limiting amplifier circuit and an optical module. Background Art

[0004] In the field of optical communications, especially in the optical chip transceiver circuit, the signal frequency is very high, and the optical signal is usually weak. Due to the weak signal and high operating frequency band, in the design of the optical chip transceiver circuit, an ultra-wideband circuit is used to process the signal. At the same time, in the transceiver circuit, especially in the analog signal part, the requirements of low noise and high linearity also need to be met. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a wideband gain-controllable limiting amplifier circuit and an optical module.

[0006] According to a first aspect of the embodiments of the present disclosure, a wideband gain-controllable limiting amplifier circuit is provided. The wideband gain-controllable limiting amplifier circuit includes: a plurality of differential amplification modules, wherein the plurality of differential amplification modules are connected in series for gradually amplifying an input signal; the differential amplification module includes: a differential amplification circuit, a proportional current source, and a current regulation circuit, wherein

[0007] The proportional current source is configured to output a second current at the output end of the proportional current source according to a first current input at the input end of the proportional current source in a predetermined proportion to serve as the tail current of the differential amplification circuit;

[0008] The current regulation circuit: includes a plurality of parallel current sources that input current to the input end of the proportional current source, wherein at least one current source among the plurality of parallel current sources has a corresponding switch component, and the switch component is configured to conduct or cut off the current input by the corresponding current source to the input end of the proportional current source to adjust the first current.

[0009] In some embodiments, the differential amplification circuit includes: a first transistor, a second transistor, a first resistor, and a second resistor; wherein

[0010] The first end of the first resistor, the first end of the second resistor are connected to a power supply,

[0011] The second terminal of the first resistor is connected to the first terminal of the first transistor and serves as the first output terminal, and the second terminal of the second resistor is connected to the first terminal of the second transistor and serves as the second output terminal;

[0012] The second terminal of the first transistor and the second terminal of the second transistor are connected to the output terminal of the proportional current source;

[0013] The control terminal of the first transistor serves as the first input terminal of the differential amplifier circuit, and the control terminal of the second transistor serves as the second input terminal of the differential amplifier circuit.

[0014] In some embodiments, the differential amplifier circuit further includes: a first inductor and a second inductor; wherein,

[0015] The first inductor is disposed between the first terminal of the first resistor and the power supply;

[0016] The second inductor is disposed between the first terminal of the second resistor and the power supply.

[0017] In some embodiments, the proportional current source includes: a third transistor and a fourth transistor, wherein,

[0018] The first terminal of the fourth transistor is connected to the control terminal of the fourth transistor and serves as the input terminal of the proportional current source to input the first current;

[0019] The first terminal of the third transistor serves as the output terminal of the proportional current source to output the second current;

[0020] The control terminal of the third transistor is connected to the control terminal of the fourth transistor;

[0021] The second terminals of the third transistor and the fourth transistor are connected to the power ground.

[0022] In some embodiments, the plurality of parallel current sources include at least one of the following:

[0023] A first current source directly connected to the input terminal of the proportional current source;

[0024] N second current sources respectively connected to the input terminal of the proportional current source through corresponding switching components, where N is an integer greater than or equal to 1.

[0025] In some embodiments, the switching component includes a switching transistor, wherein,

[0026] The first end of the switching transistor is connected to the second current source, the second end of the switching transistor is connected to the proportional current source input terminal, the control end of the switching transistor is used to input a control signal, and the switching transistor turns on or off the connection between the second current source and the proportional current source input terminal based on the control of the control signal.

[0027] In some embodiments, there are three second current sources, and the output current ratios of the three second current sources are 1:2:4.

[0028] In some embodiments, the minimum output current among the three second current sources is equal to one-Ith of the output current of the first current source, where I is an integer greater than or equal to 1; or

[0029] the minimum output current among the three second current sources is equal to J times the output current of the first current source, where J is an integer greater than or equal to 1.

[0030] According to a second aspect of the embodiments of the present disclosure, an optical module is provided, and the optical module includes the broadband gain controllable limiting amplifier circuit according to the first aspect.

[0031] According to the embodiments of the present disclosure, the broadband gain controllable limiting amplifier circuit includes: a plurality of differential amplification modules, wherein the plurality of differential amplification modules are connected in series for gradually amplifying an input signal; the differential amplification module includes: a differential amplification circuit, a proportional current source, and a current adjustment circuit, wherein the proportional current source is used to output a second current at the proportional current source output terminal according to a first current input at the proportional current source input terminal in a predetermined ratio to serve as the tail current of the differential amplification circuit; the current adjustment circuit: includes a plurality of parallel current sources that input current to the proportional current source input terminal, wherein at least one of the plurality of parallel current sources has a corresponding switching component, and the switching component is used to conduct or cut off the current input by the corresponding current source to the proportional current source input terminal to adjust the first current. In this way, on the one hand, the cascaded differential amplification modules are used to achieve cascaded amplification of the signal. Compared with the method of using a single-stage amplification module for amplification, the gain multiple of each differential amplification module in the cascaded differential amplification modules can be reduced, and the distortion problem caused by a higher gain can be reduced. On the other hand, the differential amplification module can suppress the common-mode noise of the signal and improve the signal accuracy. On the third hand, the amplification gain of each differential amplification module can be adjusted through the proportional current source and the current adjustment circuit, which improves the flexibility of gain adjustment and meets different amplification requirements of the signal. Description of the Drawings

[0032] Figure 1It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0033] Figure 2 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0034] Figure 3 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0035] Figure 4 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0036] Figure 5 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0037] Figure 6 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0038] Figure 7 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0039] Figure 8 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0040] Figure 9 It is a schematic diagram of the composition structure of a broadband gain - controllable limiting amplifier circuit shown according to an exemplary embodiment;

[0041] Figure 10 It is a schematic diagram of the composition structure of an optical module shown according to an exemplary embodiment. Detailed implementation manners

[0042] To make the technical solutions and beneficial effects of the present invention more obvious and understandable, the following will be described in detail by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0043] The embodiments of the present disclosure are not exhaustive. They are only schematic illustrations of some embodiments and do not constitute specific limitations on the protection scope of the present disclosure. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution obtained by removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be arbitrarily exchanged. In addition, the optional implementation manners in an embodiment can be combined arbitrarily; moreover, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and an embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0044] In each embodiment of the present disclosure, unless otherwise specified or there is a logical conflict, the terms and / or descriptions among the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0045] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and do not limit the present disclosure.

[0046] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "said", "aforementioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0047] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0048] In some embodiments, terms such as "at least one (at least one of, at least one item, at least one)", "one or more", "a plurality of", "multiple", etc. can be replaced with each other.

[0049] In some embodiments, notations such as "at least one of A and B", "A and / or B", "in one case A, in another case B", "one case A, another case B", etc. may, depending on the circumstances, include the following technical solutions: In some embodiments, A (performing A independently of B); in some embodiments, B (performing B independently of A); in some embodiments, selecting to perform from A and B (A and B are selectively performed); in some embodiments, A and B (both A and B are performed). The same applies when there are more branches such as A, B, C, etc.

[0050] In some embodiments, notations such as "A or B" may, depending on the circumstances, include the following technical solutions: In some embodiments, A (performing A independently of B); in some embodiments, B (performing B independently of A); in some embodiments, selecting to perform from A and B (A and B are selectively performed). The same applies when there are more branches such as A, B, C, etc.

[0051] Prefix words such as "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different described objects and do not constitute limitations on the position, order, priority, value, or content of the described objects. For the statements of the described objects, refer to the description in the claims or the context of the embodiments. There should be no redundant limitations due to the use of prefix words. For example, when the described object is "field", the ordinal numbers before "field" in "first field" and "second field" do not limit the position or order between the "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of "first field" and "second field". Another example, when the described object is "level", the ordinal numbers before "level" in "first level" and "second level" do not limit the priority between the "levels". Another example, the value of the described object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, when the described object is "device", "first device" and "second device" can be the same device or different devices, and their types can be the same or different; another example, when the described object is "information", "first information" and "second information" can be the same information or different information, and their contents can be the same or different.

[0052] In some embodiments, "including A", "containing A", "used to indicate A", "carrying A" can be interpreted as directly carrying A or as indirectly indicating A.

[0053] In some embodiments, terms such as "...", "determining...", "in the case of...", "when...", "when...", "if...", "if..." can be mutually replaced.

[0054] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", etc. may be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. may be replaced with each other.

[0055] In some embodiments, a device or the like may be interpreted as physical or virtual, and its name is not limited to the name described in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", "subject", etc. may be replaced with each other.

[0056] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure may be implemented as an independent embodiment, and any combination of any element, any row, and any column may also be implemented as an independent embodiment.

[0057] As Figure 1 and Figure 2 shown, this embodiment provides a broadband gain controllable limiting amplifier circuit 1 (abbreviated as amplifier circuit). The broadband gain controllable limiting amplifier circuit 1 includes: a plurality of differential amplification modules 10, wherein the plurality of differential amplification modules 10 are connected in series for gradually amplifying an input signal; the differential amplification module 10 includes: a differential amplification circuit 110, a proportional current source 120, and a current adjustment circuit 130, wherein,

[0058] The proportional current source 120 is configured to output a second current at an output end of the proportional current source 120 according to a first current input at an input end of the proportional current source 120 in a predetermined proportion, so as to serve as a tail current of the differential amplification circuit 110;

[0059] The current adjustment circuit 130: includes a plurality of parallel current sources 131 that input current to an input end of the proportional current source 120, wherein at least one current source 131 among the plurality of parallel current sources 131 has a corresponding switch component 132, and the switch component 132 is configured to conduct or cut off the current input by the corresponding current source 131 to the input end of the proportional current source 120, so as to adjust the first current.

[0060] Here, the broadband gain controllable limiting amplifier circuit 1 can be applied to the field of optical communication for amplifying signals. For example, the broadband gain controllable limiting amplifier circuit 1 is used to amplify the signal obtained after photoelectric conversion.

[0061] The broadband gain controllable limiting amplifier circuit 1 includes multiple differential amplification modules 10. Each differential amplification module 10 serves as one stage of amplification. The output signal of the previous-stage differential amplification module 10 is used as the input signal of the next-stage differential amplification module 10, forming a cascaded amplification circuit. Thus, the input signal is amplified stage by stage. Among them, the input signal can include a differential input signal.

[0062] In a possible implementation, the tail current can include the current flowing through the transistors in the differential pair of the differential amplification circuit 110.

[0063] In a possible implementation, the tail current is used to adjust the gain and linear input range of the differential amplification circuit 110.

[0064] In a possible implementation, the proportional current source 120 can include a current mirror.

[0065] In a possible implementation, the predetermined ratio can include 1:1.

[0066] In a possible implementation, the proportional current source 120 outputs the second current as the tail current of the differential amplification circuit 110, which can include: the proportional current source 120 extracts the second current from the transistors in the differential pair of the differential amplification circuit 110 to serve as the tail current.

[0067] Multiple parallel current sources 131 input current to the proportional current source 120 in parallel. That is, the first current is the sum of the currents output by the multiple parallel current sources 131 to the proportional current source 120.

[0068] In a possible implementation, a switch component 132 can conduct or cut off the current output from one current source 131 to the proportional current source 120, thereby playing a role in adjusting the second current, that is, the tail current of the differential amplification circuit 110. By adjusting the tail current, the gain of the differential amplification circuit 110 can be adjusted. Through the proportional current source 120 and the current adjustment circuit 130, the amplification gain of each differential amplification module 10 can be adjusted to meet different amplification requirements of the signal.

[0069] In a possible implementation, a proportional current source 120 and a current regulation circuit 130 correspond to a differential amplification module 10. That is, in each differential amplification module 10, there is a proportional current source 120 and a current regulation circuit 130. Each differential amplification module 10 having a proportional current source 120 and a current regulation circuit 130 can achieve individual adjustment of the gain of each differential amplification module 10, improving the flexibility of gain adjustment of each differential amplification module 10.

[0070] Thus, on the one hand, cascading the differential amplification modules 10 realizes cascaded amplification of the signal. Compared with the method of using a single-stage amplification module for amplification, it can reduce the gain multiple of each differential amplification module 10 in the cascaded differential amplification modules 10, reducing the distortion problem caused by a higher gain. On the other hand, using the differential amplification module 10 can suppress the common-mode noise of the signal, improving the signal accuracy. On the third hand, the amplification gain of each differential amplification module 10 can be adjusted through the proportional current source 120 and the current regulation circuit 130, improving the flexibility of gain adjustment and meeting different amplification requirements of the signal.

[0071] In a possible implementation, a proportional current source 120 and a current regulation circuit 130 correspond to M differential amplification modules 10. That is, among the M differential amplification modules 10, the same proportional current source 120 and current regulation circuit 130 are adopted. The proportional current source 120 (such as a current mirror) can copy M second currents in a predetermined ratio as the tail current of the differential amplification circuit 110 in the M differential amplification modules 10. Wherein, M is an integer greater than or equal to 1. In a possible implementation, M is the total number of differential amplification modules 10. The M differential amplification modules 10 having a proportional current source 120 and a current regulation circuit 130 can achieve overall adjustment of the gain of multiple differential amplification modules 10, reducing the number of the proportional current source 120 and the current regulation circuit 130 and reducing the cost.

[0072] In some embodiments, as Figure 3 shown, the differential amplification circuit 110 includes: a first transistor, a second transistor, a first resistor, and a second resistor; wherein,

[0073] The first end of the first resistor, the first end of the second resistor are connected to the power supply,

[0074] The second end of the first resistor is connected to the first end of the first transistor and serves as the first output terminal, and the second end of the second resistor is connected to the first end of the second transistor and serves as the second output terminal;

[0075] The second ends of the first transistor and the second transistor are connected to the output terminal of the proportional current source 120;

[0076] The control terminal of the first transistor serves as the first input terminal of the differential amplifier circuit 110, and the control terminal of the second transistor serves as the second input terminal of the differential amplifier circuit 110.

[0077] It should be noted that the transistors in the embodiments of the present application may be field effect transistors or bipolar transistors. Among them, the field effect transistors may include N-type transistors and P-type transistors. In specific implementation, the gates of the above-mentioned N-type transistors and P-type transistors serve as their control electrodes, and according to the signals of the gates of each transistor and their types, their first ends may be used as source electrodes and the second ends as drain electrodes, or their first ends may be used as drain electrodes and the second ends as source electrodes. In this embodiment, unless otherwise specified, N-type transistors are taken as examples for illustration, where the control terminal is the gate, the first end is used as the drain electrode, and the second end is used as the source electrode.

[0078] In a possible implementation manner, the differential amplifier circuit 110 adopts a common-source circuit.

[0079] Figure 3 In, INN and INP are input signals, which are respectively input to the first input terminal and the second input terminal of the differential amplifier circuit 110. The differential amplifier circuit 110 amplifies the input signals, and outputs two output signals, OUTP and OUTN, at the second output terminal and the second output terminal of the differential amplifier circuit 110 respectively.

[0080] Figure 3 In, the second end of the first transistor is connected to the second transistor, and the third transistor is controlled by VB to generate a tail current.

[0081] In a possible implementation manner, the resistance value of the first resistor is equal to the resistance value of the second resistor; the first transistor is the same as the second transistor (such as having the same size).

[0082] Figure 4 is Figure 3 A schematic diagram of the circuit on one side of the differential amplifier circuit 110 Figure 5 is Figure 4 An equivalent schematic diagram of the circuit.

[0083] Figure 4 and Figure 5 In, CL is the input capacitance of the load (such as the next-stage differential amplifier circuit 110) of the differential amplifier circuit 110. From Figure 5 it can be seen that Figure 4 The transfer function of the amplifier circuit shown is as shown in expression (1):

[0084]

[0085] Among them, ω represents the angular frequency of the signal, g mrepresents the transconductance of the input transistor, C L represents the input capacitance of the load (such as the next-stage differential amplifier circuit) of the differential amplifier circuit 110.

[0086] As shown in 4, the amplifier circuit has a pole ω p , as shown in Expression (2):

[0087]

[0088] That is Figure 3 the differential amplifier circuit 110 has a pole.

[0089] In some embodiments, as Figure 6 shown, the differential amplifier circuit 110 further includes: a first inductor and a second inductor;

[0090] Wherein,

[0091] the first inductor is disposed between the first end of the first resistor and the power supply;

[0092] the second inductor is disposed between the first end of the second resistor and the power supply.

[0093] In a possible implementation, the resistance value of the first resistor is equal to the resistance value of the second resistor; the first transistor is the same as the second transistor (such as having the same size); the inductance value of the first inductor is equal to the inductance value of the second inductor.

[0094] Figure 7 is Figure 6 an equivalent schematic diagram of the circuit on one side of the differential amplifier circuit 110.

[0095] From Figure 7 it can be seen that Figure 6 the transfer function of one side of the differential amplifier circuit 110 is as shown in Expression (3):

[0096]

[0097] Wherein, ω represents the angular frequency of the signal, g m represents the transconductance of the input transistor, C L represents the input capacitance of the load (such as the next-stage differential amplifier circuit) of the differential amplifier circuit 110.

[0098] It can be seen that compared with Expression (2), there is a zero point in Expression (3), that is Figure 6 the differential amplifier circuit 110 has a zero point. Relative to Figure 3 the case where the differential amplifier circuit 110 has a pole and the gain amplitude will decay when the signal frequency increases. Figure 6Due to the introduction of inductive elements, the differential amplifier circuit shown will add a zero point in the circuit as the frequency increases, thereby expanding the bandwidth in the high-frequency band. Therefore, when using a cascaded structure for amplification, the bandwidth and gain can be ensured to remain unchanged within a certain range, thereby improving the linearity of the circuit and further ensuring the linearity of the system as a whole.

[0099] By adding an inductor in the differential amplifier circuit 110 and introducing a new zero point to compensate for the circuit poles, the working stability and linearity of the differential amplifier circuit 110 in the wide frequency band range are further ensured, thereby effectively improving the expansion and application of the amplifier circuit at higher frequencies.

[0100] In some embodiments, as Figure 8 and Figure 9 shown, the proportional current source 120 includes: a third transistor and a fourth transistor, wherein,

[0101] The first end of the fourth transistor is connected to the control end of the fourth transistor, serving as the input end of the proportional current source 120;

[0102] The first end of the third transistor serves as the output end of the proportional current source 120;

[0103] The control end of the third transistor is connected to the control end of the fourth transistor;

[0104] The second end of the third transistor, the second end of the fourth transistor, and the power ground are connected.

[0105] As Figure 8 and Figure 9 shown, the third transistor and the fourth transistor form a current mirror. The third transistor can copy the first current flowing through the first end and the second end of the fourth transistor according to a predetermined ratio to obtain a second current, and use the second current as the tail current of the differential amplifier circuit 110. By changing the transconductance of the first transistor and the second transistor.

[0106] In some embodiments, the multiple parallel current sources 131 include at least one of the following:

[0107] A first current source directly connected to the input end of the proportional current source 120;

[0108] N second current sources respectively connected to the input end of the proportional current source 120 through corresponding switch components 132, where N is an integer greater than or equal to 1.

[0109] Exemplarily, as Figure 8 and Figure 9 shown, the multiple parallel current sources 131 may include a first current source IB4 and three second current sources: IB1, IB2, and IB3.

[0110] The currents output by IB1, IB2, and IB3 to the input terminal of the proportional current source 120 are respectively controlled by the switching component 132.

[0111] The output current of the second current source can be controlled to be combined with the output current of the first current source and input to the proportional current source 120 to adjust the tail current of the differential amplifier circuit 110, thereby realizing the adjustment of the gain of the differential amplifier circuit 110.

[0112] In some embodiments, the switching component 132 includes switching transistors, where

[0113] The first end of the switching transistor is connected to the second current source, the second end of the switching transistor is connected to the input terminal of the proportional current source 120, the control end of the switching transistor is used to input a control signal, and the switching transistor turns on or off the connection between the second current source and the input terminal of the proportional current source 120 based on the control of the control signal.

[0114] In a possible manner, the switching transistors NM7, NM6, and NM5 are respectively controlled by the control signals vb<0>, vb<1>, and vb<2> to achieve conduction or cutoff.

[0115] In a possible implementation manner, the control signal can be output by a controller, etc. The controller can turn on or off the current of the second current source through the control signal to adjust the gain of the differential amplifier circuit 110.

[0116] In some embodiments, there are 3 second current sources, and the output current ratio of the 3 second current sources is 1:2:4.

[0117] In some embodiments,

[0118] The minimum output current among the 3 second current sources is equal to 1 / I of the output current of the first current source, where I is an integer greater than or equal to 1; or

[0119] The minimum output current among the 3 second current sources is equal to J times the output current of the first current source, where J is an integer greater than or equal to 1.

[0120] In a possible implementation manner, I can be 10. The current output by the second current source is relatively small, and fine-tuning of the first current can be achieved on the basis of the output current of the first current source, improving the gain control accuracy.

[0121] In a possible implementation manner, I can be 2. The current output by the second current source is relatively large, and a larger range of gain control can be achieved on the basis of the output current of the first current source, expanding the application range of the amplifier circuit.

[0122] The following provides multiple specific examples in combination with any of the above embodiments:

[0123] Taking Figure 8 the amplifier circuit as an example for illustration

[0124] Gain control principle description:

[0125] 1) The input control signals vb<0>, vb<1> and vb<2> control the currents of IB1, IB2 and IB3 respectively. The currents are combined into IB4 through the on-off states of the three MOS transistors NM7, NM6 and NM5.

[0126] 2) The current in the NM4 transistor will generate a certain proportion of current in the NM3 transistor through mirroring. This current serves as the tail current in the module circuit, thereby changing the transconductance of the input pair transistors NM1 and NM2 in the limiting amplifier circuit.

[0127] 3) The amplification factor of the output signal is directly positively correlated with the magnitude of the input signal VIN and the product of the transconductances of NM1 and NM2.

[0128] Figure 8 Among them: the input pair transistors NM1 and NM2 have the same size and are symmetrically designed; the resistors R1 and R2 have the same size and are symmetrically designed; the inductors L1 and L2 have the same size and are symmetrically designed.

[0129] Preferably, IB1, IB2, and IB3 are designed according to a certain ratio, which can be designed according to 1:2:4. Their current magnitudes generally take 1 / 10 of the main bias current of IB4, so that the current can be effectively micro-adjusted;

[0130] Furthermore: it can also be set to 1 times the main bias current of IB4, so as to expand the application to a larger gain control range.

[0131] Figure 8 The equivalent circuit diagram on one side of the differential amplifier circuit 110 is as Figure 7 shown, and its transfer function is as shown in expression (3).

[0132] It can be seen from expression (3) that as the frequency increases, due to the introduction of the inductor element, a zero point will be added to the circuit, thereby expanding the bandwidth in the high-frequency band. Therefore, when using a cascade structure for amplification, the bandwidth and gain can be guaranteed to remain unchanged within a certain range, thereby improving the linearity of the circuit and further ensuring the linearity of the system as a whole.

[0133] On the other hand, the adjustment and control of each stage gain are still achieved by the circuits IB1, IB2, and IB3 in the bias circuit to correct IB4, so as to ensure the control of the gm transconductance, and further ensure that the overall gain of the circuit is controlled.

[0134] Figure 8 The shown amplifier circuit has good symmetry, which is beneficial to the robustness of the circuit during actual operation and facilitates engineering implementation. Moreover, in terms of noise performance, especially in suppressing analog noise, it shows outstanding performance. It has a simple structure and fewer variable factors, so the design is easier to implement and the control is more direct. It has strong gain controllability and is easy to expand in structure.

[0135] Figure 10 This embodiment proposes an optical module 0, such as Figure 10 shown, the optical module 0 includes: a broadband gain-controllable limiting amplifier circuit 1.

[0136] Specifically, the specific implementation manner of the broadband gain-controllable limiting amplifier circuit 1 is as described in the Figures 1 to 9 embodiment. It will not be elaborated here.

[0137] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present invention. This disclosure is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed in this disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the following claims.

[0138] It should be understood that the present invention is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A wideband gain controllable limiting amplifier circuit, characterized in that: The wide-band gain controllable limiting amplifier circuit comprises: a plurality of differential amplifier modules, wherein the plurality of differential amplifier modules are connected in series and used to amplify the input signal step by step; the differential amplifier module comprises: a differential amplifier circuit, a proportional current source and a current regulating circuit, wherein: The proportional current source is used to output a second current at the proportional current source output terminal according to a predetermined ratio based on the first current input to the proportional current source input terminal, so as to serve as the tail current of the differential amplifier circuit; The current regulating circuit comprises a plurality of parallel current sources for inputting current to the proportional current source input terminal, wherein at least one of the plurality of parallel current sources has a corresponding switch component, and the switch component is used to turn on or off the current input by the corresponding current source to the proportional current source input terminal to regulate the first current.

2. The wideband gain controllable limiting amplifier circuit according to claim 1, characterized in that: The differential amplifier circuit comprises: a first transistor, a second transistor, a first resistor, and a second resistor; wherein, The first end of the first resistor and the first end of the second resistor are connected to a power source, The second end of the first resistor is connected to the first end of the first transistor and serves as a first output end, and the second end of the second resistor is connected to the first end of the second transistor and serves as a second output end; The second end of the first transistor and the second end of the second transistor are connected to the output end of the proportional current source; The control end of the first transistor serves as the first input end of the differential amplifier circuit, and the control end of the second transistor serves as the second input end of the differential amplifier circuit.

3. The wideband gain controllable limiting amplifier circuit according to claim 2, characterized in that: The differential amplifier circuit further includes: a first inductor and a second inductor; wherein, The first inductor is arranged between the first end of the first resistor and the power supply; The second inductor is arranged between the first end of the second resistor and the power supply.

4. The wideband gain controllable limiting amplifier circuit according to claim 1, characterized in that: The proportional current source comprises: a third transistor and a fourth transistor, wherein: The first end of the fourth transistor is connected to the control end of the fourth transistor, and serves as the input end of the proportional current source to input the first current; The first terminal of the third transistor serves as an output terminal of a proportional current source to output the second current; The control end of the third transistor is connected to the control end of the fourth transistor; The second terminal of the third transistor, the second terminal of the fourth transistor and a power ground are connected.

5. The wideband gain controllable limiting amplifier circuit according to any one of claims 1 to 4, characterized in that: The plurality of parallel current sources include at least one of the following: a first current source directly connected to the proportional current source input terminal; N second current sources are respectively connected to the input terminal of the proportional current source through corresponding switch components, wherein N is an integer greater than or equal to 1.

6. The wideband gain controllable limiting amplifier circuit according to claim 5, characterized in that: The switch component comprises a switch transistor, wherein: The first end of the switching transistor is connected to the second current source, the second end of the switching transistor is connected to the proportional current source input end, the control end of the switching transistor is used to input a control signal, and the switching transistor opens or closes the connection between the second current source and the proportional current source input end based on the control of the control signal.

7. The wideband gain controllable limiting amplifier circuit according to claim 6, characterized in that: There are three second current sources, and the output current ratio of the three second current sources is 1:2:

4.

8. The wideband gain controllable limiting amplifier circuit according to claim 7, characterized in that: The minimum output current of the three second current sources is equal to one-th of the output current of the first current source, where I is an integer greater than or equal to 1; or The minimum output current of the three second current sources is equal to J times the output current of the first current source, where J is an integer greater than or equal to 1.

9. An optical module, characterized in that: The optical module comprises the wide-band gain controllable limiting amplifier circuit according to any one of claims 1 to 8.

Images