Quarter clock and bipartite clock compatible FFE system and method

Abstract

The invention aims to provide a quartered clock and bisected clock compatible FFE system and method, and the method comprises the steps: converting six-beat data into three-beat data through employing a low-speed clock in a four-phase clock mode; when the four-phase clock mode is converted into the two-phase clock mode, 0-degree and 180-degree phase clocks are adopted for beating; in the two-phase clock mode, a beat of delay is added behind the sampling clock of the fourth data set. According to the invention, a group of necessary DCC calibration and direct clock phase calibration can be reduced, and noise and power consumption are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a four-phase clock and two-phase clock compatible FFE system and method. Background Art

[0002] The FFE system is short for Feed Forward Equalizer, which is mainly used in communication systems to optimize signal transmission quality. The FFE system is an equalization technique mainly used to compensate for signal distortion caused by channel characteristics during transmission. Its core idea is to make the frequency response characteristic of the entire system flatter by adjusting the frequency response characteristic of the signal, thereby reducing inter-symbol interference (ISI). The FFE system is usually implemented using a digital filter, and the most common one is the finite impulse response (FIR) filter. The working principle of the FFE system is to apply appropriate delays at the transmitting end or receiving end to generate multipath signals, and then linearly scale and combine these signals to eliminate ISI caused by the channel. Specifically, the FFE system uses a digital filter to perform high-pass filtering on the signal, and adjusts the tap coefficients of the filter to change the frequency response characteristic, so that the high-frequency and low-frequency components are attenuated uniformly, optimizing the eye diagram. The FFE system is widely used in various communication systems, especially in high-speed serial interfaces such as PCIe. In the PCIe standard, the FFE system uses pre-emphasis and de-emphasis technologies to optimize signal transmission. Pre-emphasis is to intentionally enhance the signal amplitude of the signal transition edge, and de-emphasis is to reduce the signal amplitude outside the transition edge to reduce power consumption and external radiation.

[0003] In recent years, in high-speed clock transmission, the clock sampled at the rising and falling edges has been unable to meet the requirements of high-speed transmission. When the transmission rate reaches 56G, the bandwidth limitation of the process cannot reach the required 28GHz. Therefore, the 4-phase 14GHz clock has become the mainstream. However, for some low-speed applications, the additional phase calibration error brought by the 4-phase clock is a disadvantage. Therefore, this set of compatible FFE system is necessary. In high-speed design, the calibration scheme for the four-phase clock is generally to first calibrate the duty cycle (abbreviation: DCC) of the ck0 / c180 and ck90 / ck270 clocks. After calibrating the duty cycle, XOR is used to adjust the phase difference (abbreviation: QEC) between the two groups of clocks. When the system is compatible with low-speed protocols, the clock will be downscaled at the front end and then go through the low-speed DCC / QEC in sequence. Each stage of the clock will bring additional power consumption and noise. However, if it is directly output at the DCC output, these power consumption and noise can be effectively reduced, but it will cause incompatibility problems for the subsequent FFE design. Summary of the Invention

[0004] The object of the present invention is to provide a four-phase clock and two-phase clock compatible FFE system and method, which can reduce the calibration of a necessary set of DCC and the phase calibration between clocks, and effectively improve noise and power consumption.

[0005] A method for a four-phase clock and two-phase clock compatible FFE system, comprising: In the four-phase clock mode, use a slow clock to convert six-beat data into three-beat data; When the four-phase clock mode is converted to the two-phase clock mode, use 0° and 180° phase clocks for beating; In the two-phase clock mode, add a one-beat delay after the sampling clock of the fourth data group.

[0006] Preferably, before using a slow clock to convert six-beat data into three-beat data in the four-phase clock mode, data preprocessing is further included, specifically: Perform retimer processing on the data before entering the 4to1mux; Add two additional data before and after the current data to complete data preprocessing.

[0007] Preferably, when the four-phase clock mode is converted to the two-phase clock mode, using 0° and 180° phase clocks for beating includes: Use two phases of the four-phase clock as the clock mode of the DFF and add it to the FFE; When the four-phase clock switches to the two-phase clock, two clocks of the four-phase clock are set to CK90:0 and CK270:1 by RST, that is, the two clocks are turned off; The adjacent clocks AND to generate the sampling clock PULSE, reducing the original four sampling clock PULSEs to two, and they are the sampling clock PULSEs of the latter two phases, that is, 0° and 180° phase clocks.

[0008] Preferably, the conversion of the four-phase clock mode to the two-phase clock mode includes: When the sampling clock becomes two-phase, fully multiplex the third data and the fourth data in the four groups of data of the four-phase clock; Connect the first data transmission line of the four-phase clock to the transmission line of the third data; Connect the second data transmission line of the four-phase clock to the transmission line of the fourth data.

[0009] Preferably, connecting the first data transmission line of the four-phase clock to the transmission line of the third data includes: Control the selector according to the clock mode of the FFE system; When the FFE system is in the two-phase clock mode, connect the first data transmission line of the four-phase clock to the transmission line of the third data.

[0010] Preferably, the transmission line connecting the second data transmission line of the four-phase clock to the fourth data includes: A clock mode control selector according to the FFE system; When the FFE system is in the two-phase clock mode and the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data.

[0011] A four-phase clock and two-phase clock compatible FFE system, including: a third data sampling circuit; The third data sampling circuit includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a first selector; The CK terminal of the first flip-flop is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data; The CK terminal of the second flip-flop is connected to the inverted clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data; The CK terminal of the third flip-flop is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post-signal for sampling the third data; The CK terminal of the fourth flip-flop is connected to the inverted clock signal, the D terminal is connected to the post-signal for sampling the third data, and the Q terminal is connected to the delayed signal of the post-signal for sampling the third data; The positive input terminal of the first selector is connected to the Q terminal of the third flip-flop, and the negative input terminal is connected to the Q terminal of the fourth flip-flop.

[0012] Preferably, it further includes: a first data sampling circuit; The first data sampling circuit includes: a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, an eighth flip-flop and a second selector; The D terminal of the fifth flip-flop is connected to the input signal for sampling the first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the inverted clock signal; The D terminal of the sixth flip-flop is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal; The D terminal of the seventh flip-flop is connected to the pre-signal for sampling the first data, the Q terminal is connected to the main signal for sampling the first data, and the CK terminal is connected to the inverted clock signal; The D terminal of the eighth flip-flop is connected to the main signal for sampling the first data, the Q terminal is connected to the post-signal for sampling the first data, and the CK terminal is connected to the clock signal; The positive input terminal of the second selector is connected to the input signal for sampling the first data.

[0013] An electronic device, comprising: a chip, a processor, and a memory, where the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for a four-phase clock and two-phase clock compatible FFE system.

[0014] A computer-readable storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for a four-phase clock and two-phase clock compatible FFE system.

[0015] The beneficial effects of the present invention are as follows: 1. In the low-speed protocol of the present invention, switching to use a two-phase clock can reduce the calibration of a necessary set of DCC and the phase calibration between clocks, effectively improving noise and power consumption; 2. The present invention uses a two-phase clock as the input clock of the DFF. Although it sacrifices a part of the setup time, it saves a large amount of power consumption and also makes this part of the circuit compatible; 3. The present invention only needs to make a small part of circuit modifications to be compatible with both a four-phase clock and a two-phase clock simultaneously, and does not affect the setup time of data sampling. Description of the Drawings

[0016] The drawings here are incorporated into the specification and form a part of this specification, marking the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a flowchart of a method for a four-phase clock and two-phase clock compatible FFE system of the present invention; Figure 2 It is the third data sampling circuit diagram of the present invention; Figure 3 It is the first data sampling circuit diagram of the present invention; Figure 4 It is the four-phase clock sampling timing diagram of the present invention; Figure 5 It is the sampling timing diagram of the four-phase clock with FFE TAP added of the present invention; Figure 6 It is the optimized four-phase clock sampling timing diagram of the present invention; Figure 7Sampling timing diagram of the optimized four-phase clock with FFE TAP for the present invention; Figure 8 Four-phase clock sampling phase diagram of the present invention; Figure 9 Two-phase clock sampling phase diagram of the present invention; Figure 10 Two-phase clock FFE sampling and data distribution diagram of the present invention. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0021] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions conflicts or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0022] In high-speed clock transmission, the clock with upper and lower edge sampling can no longer meet the requirements of high-speed transmission. When the transmission rate reaches 56G, the bandwidth limitation of the process cannot reach the required 28GHz. Therefore, the 4-phase 14GHz clock has become the mainstream. However, for some low-speed applications, the additional phase calibration error brought by the 4-phase clock is actually a disadvantage. So this set of compatible FFE system is necessary. In high-speed design, the calibration scheme for the four-phase clock is generally to calibrate the duty cycle (abbreviation: DCC) of the ck0 / c180 and ck90 / ck270 clocks first. After calibrating the duty cycle, use XOR to adjust the phase difference between the two groups of clocks (abbreviation: QEC). When the system is compatible with low-speed protocols, the clock will be down-converted at the front end and then go through the low-speed DCC / QEC in sequence. Each stage of the clock will bring additional power consumption and noise. But if it is directly output at the DCC output, these power consumption and noise can be effectively reduced, but it will cause incompatibility problems for the subsequent FFE design.

[0023] The present invention can reduce a set of necessary DCC calibration and the direct phase calibration of the clock by switching to use two-phase clocks in low-speed protocols, effectively improving noise and power consumption; the present invention uses two-phase clocks as the input clock of the DFF. Although it sacrifices a part of the setup time, it saves a large amount of power consumption and also makes this part of the circuit compatible; the present invention only needs to modify a small part of the circuit to be compatible with both four-phase clocks and two-phase clocks, and does not affect the setup time of data sampling.

[0024] Embodiment 1 A method for a four-phase clock and two-phase clock compatible FFE system, refer to Figure 1 , including: S100, in the four-phase clock mode, use a slow clock to convert six-beat data into three-beat data; In a communication system, an FFE (Feed-Forward Equalizer) is used to compensate for channel distortion and usually includes multiple taps (TAPs), which are divided into three parts: PRE, MAIN, and POST: PRE TAP: Processes the leading part of the signal and mainly compensates for pre-cursor distortion (interference caused by the previous symbol). The PRE TAP can reduce the interference of the previous symbol on the current symbol. MAIN TAP: Processes the current part of the signal and compensates for the main cursor distortion (interference of the current symbol). The MAIN TAP can enhance the intensity of the current symbol. POST TAP: Processes the subsequent part of the signal and compensates for post-cursor distortion (interference caused by subsequent symbols). The POST TAP can reduce the interference of subsequent symbols on the current symbol.

[0025] Refer to Figure 6, in the four-phase clock mode, there are a total of four groups of data, namely D0, D1, D2, and D3. Each group of data consists of three taps, namely D0 PRE, D0 MAIN, D0 POST; D1 PRE, D1 MAIN, D1 POST; D2 PRE, D2 MAIN, D2 POST; D3 PRE, D3 MAIN, D3 POST; reference Figure 5 , a total of six clock beats are required to transmit all the data. However, six DFFs are needed for six clock beats, which will obviously consume a large amount of power and area. Therefore, in the embodiments of the present invention, by sampling the slow clock, the clock that originally required six beats is converted into a clock that requires three beats. Although the setup time of sampling is sacrificed, power consumption and area are saved. Reference Figure 7 , when this mode is combined with FFE, there is no need to add an extra DFF group to transmit Data, and it is still three groups, making the power consumption advantage even greater.

[0026] S200, when the four-phase clock mode is converted to the two-phase clock mode, 0° and 180° phase clocks are used for clocking; In a four-phase clock system, using 0° and 180° phase clock signals for "clocking" usually means using these two phase signals for some synchronization or control operations. A four-phase clock system consists of four clock signals with a phase difference of 90°, usually represented as: 0° phase clock (Phase 0), 90° phase clock (Phase 90), 180° phase clock (Phase 180), 270° phase clock (Phase 270). These clock signals are usually used for high-precision timing control, data sampling, or multi-phase signal processing. In the embodiments of the present invention, when the four-phase clock mode is converted to the two-phase clock mode, 0° and 180° phase clocks are used for clocking, and the two-phase clock mode can be easily switched to.

[0027] S300, in the two-phase clock mode, add one clock beat delay after the sampling clock of the fourth data group.

[0028] As mentioned above, although the four-phase clock can be directly switched to the two-phase clock by directly turning off two of the four-phase clocks, it will cause the clock signals to be misaligned. Therefore, the circuit needs to be modified so that in the two-phase clock mode, one clock beat delay can be added after the sampling clock of the fourth data group to align the clocks and make the FFE system compatible with both the four-phase clock mode and the two-phase clock mode.

[0029] Preferably, reference Figure 4 and Figure 5, S100, in the four-phase clock mode, before using the slow clock to convert the six-beat data into three-beat data, the data is also pre-processed, specifically: The data is retimed before entering 4to1mux; ‌Retimer is a hardware device used to improve signal quality‌. During signal transmission, when the signal is attenuated or distorted due to long-distance transmission or high-speed data transmission, the Retimer can receive these signals and regenerate and retime them to restore the signal quality‌.

[0030] Add two extra data before and after the current data to complete data preprocessing.

[0031] The present invention takes the TAP (PRE, MAIN, POST) of three FFEs as an example. When the transmission frequency reaches above 56G, the last level of parallel-to-serial circuit is generally completed by 4to1mux. In order to ensure that each bit has sufficient setup time / hold time when the clock of 4to1mux is sampled. Data will be retimed before entering 4to1. On this basis, two additional sets of data before and after can complete the retimer data processing of FFE. However, this method has a defect. Due to the large amount of data, a set of DFF is required for each beat of data, resulting in a large amount of power consumption and area. Therefore, only two phases of the 4-phase clock are used as the clock of the DFF. The setup time of sampling is sacrificed in exchange for power consumption and area, that is, a slow clock is used to convert six beats of data into three beats of data, so that the power consumption is smaller.

[0032] Preferably, reference Figure 8 and Figure 9 , S200, when the four-phase clock mode is converted to the two-phase clock mode, the 0° and 180° phase clocks are used for beating, including: A mode that uses two phases of a four-phase clock as the clock for DFF is added to FFE; When the four-phase clock is switched to the two-phase clock, the two clocks of the four-phase clock are set to CK90:0 CK270:1 by RST, that is, the two clocks are turned off; Adjacent clocks AND generate sampling clock PULSE, reducing the original four sampling clock PULSE to two, and the sampling clock PULSE are the latter two phases, namely, 0° and 180° phase clocks.

[0033] The 0° and 180° phase clocks are in antiphase, that is, their waveforms are exactly opposite. When the 0° phase clock is high, the 180° phase clock is low, and vice versa. "Beating" usually refers to triggering certain operations using the edges (rising edge or falling edge) of the clock signal. In the 0° and 180° phase clocks, their rising edges or falling edges can be used for alternating operations. The edges of the 0° and 180° phase clocks appear alternately and can be used to alternately trigger two operations. For example, the rising edge of the 0° clock triggers operation A, and the rising edge of the 180° clock triggers operation B. By using the edges of two antiphase clocks, the operation frequency can be doubled. For example, if the frequency of a single clock is ff, using the 0° and 180° clocks can achieve an operation frequency of 2f2f. In a system that requires strict synchronization, the 0° and 180° clocks can be used to control two alternately operating modules. In high-speed data acquisition, using the 0° and 180° clocks for alternating sampling can increase the sampling rate. In a communication system, multi-phase clocks are used for signal demodulation or modulation. In a digital circuit, using the 0° and 180° clocks to alternately trigger two modules can improve the system efficiency. By combining the 0° and 180° clocks, a clock signal with a lower frequency can be generated. Suppose there is a four-phase clock system with a clock frequency of ff, and the 0° and 180° clocks are used for alternating operations: Rising edge of the 0° clock: Trigger operation A. Rising edge of the 180° clock: Trigger operation B. Result: Operations A and B are alternately executed, and the overall operation frequency is 2f2f. In a four-phase clock system, using the 0° and 180° phase clocks for "beating" means using their antiphase relationship to improve the timing accuracy or operation frequency by alternately triggering operations.

[0034] In an embodiment of the present invention, Figure 8 is a schematic diagram of the sampling clock and phase of the four-phase clock of the present invention, Figure 9 is a schematic diagram of the sampling clock and phase of the two-phase clock of the present invention.

[0035] Preferably, referring to Figure 10 , the conversion of the four-phase clock mode to the two-phase clock mode includes: When the sampling clock becomes two-phase, the third data and the fourth data in the four groups of data of the four-phase clock are fully multiplexed; Connect the first data transmission line of the four-phase clock to the transmission line of the third data; Connect the second data transmission line of the four-phase clock to the transmission line of the fourth data.

[0036] When the four-phase clock mode is converted to the two-phase clock mode, the four original phases for transmitting four groups of data are changed to transmitting four groups of data by two phases. The conversion method from the four-phase clock mode to the two-phase clock mode is to turn off two groups of clocks. At this time, there are still two groups of clocks left. These two groups of clocks were originally used to transmit D2 and D3 data. At this time, the sampling clocks of D0 and D1 are turned off. Therefore, the clocks used to transmit D2 and D3 data should also transmit D0 and D1 while transmitting D2 and D3 data.

[0037] After the clock in the circuit becomes two-phase while the structure remains unchanged, the correct sampling DATA sequence of the present invention is as Figure 9 shown. It is very close to the four-phase here. The difference is that the Data sequence is incorrect. In the Figure 10 right half, the middle two groups of these groups of data can be fully reused (D3_pre / D2 and D3 / D2_POST). The first group D2_PRE does not exist, but the two groups of signals D0 / D1 are not used at all in the two-phase clock. So when inputting, D0 = D2; D1 = D3 can be set. Then, by replacing the first group of the two-phase clock with D0_PRE, the correct result can be directly obtained without modifying the circuit.

[0038] In addition, there will be one more group of DATA for the FFE data of the two phases. Originally, one more group of DFF was needed to generate this signal, but here only generating this one signal is enough. This is the only place that needs to be repaired for compatibility with the two groups of circuits. This part of the circuit can be moved forward logically to the DFF inside the retimer instead of using a MUX selection after the retimer finally, so as to ensure that the delay of each branch is equal.

[0039] Preferably, connecting the first data transmission line of the four-phase clock to the third data transmission line includes: A selector controlled according to the clock mode of the FFE system; When the FFE system is in the two-phase clock mode, connect the first data transmission line of the four-phase clock to the third data transmission line.

[0040] In Figure 9 , by comparing the DATA in the second row and the third row, the present invention can directly reuse (D3_PRE / D2 and D3 / D2_POST). For the DATA in the first row, although there is no data that can be reused, there are some D0 and D1 signals that are not used in the two-phase clock. Some simple processing can be performed at the low-speed parallel port of the data input so that in the two-phase clock mode, the DATA of D2 / D3 is copied to D1 / D0. In this way, when taking the DATA in the first row, D0_PRE can be directly taken, and the same result as D2_PRE will be obtained.

[0041] However, there is still an unsolved technical problem, that is, there is no corresponding DATA available for the data in the fourth row. The reason is that the four-phase clock plus PRE / POST requires a total of 6 (4 + 2) cycles, but after optimizing the four-phase clock, all PRE / POST signals can be completed within three half-speed cycles, so the DFF is only delayed by two cycles, while the two-phase clock requires a total of 4 (2 + 2) cycles, and the original circuit system cannot achieve this. It is necessary to add one more clock cycle after the original D3_POST to obtain D3_POST_POST to correspond to the data on the left. The circuit implementation is as Figure 2 .

[0042] Preferably, connecting the second data transmission line of the four-phase clock to the transmission line of the fourth data includes: A selector controlled according to the clock mode of the FFE system; When the FFE system is in the two-phase clock mode and when the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data.

[0043] According to the foregoing, after adding the supplementary circuit, the data compatibility problem between the two-phase clock and the four-phase clock is perfectly solved, and only one MUX in the figure needs to be added. However, the addition of this MUX increases the timing delay of one MUX in the 4-phase high-speed mode. The next-stage circuit is extremely sensitive to timing, so this design must be further optimized. Therefore, Figure 3 , Figure 3 Adjusting the position where the MUX appears can make the timing from the last-stage Tck-q to the next stage consistent. Such adjustment will also cause the D3_PRE and D3_MAIN in the original signal to be misaligned again to generate incorrect data. However, there is still a group of D1 data mentioned before that has not been used. If changes are made in the path of the D1 data and D3_POST in the two-phase clock mode is connected to D1_POST in the figure. Then the problem is truly and perfectly solved.

[0044] Embodiment 2 A four-phase clock and two-phase clock compatible FFE system, including: a third data sampling circuit; The third data sampling circuit includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a first selector; The CK terminal of the first flip-flop is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data; The CK terminal of the second flip-flop is connected to the inverted clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data; The CK terminal of the third flip-flop is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post-signal for sampling the third data; The CK terminal of the fourth flip-flop is connected to the inverted clock signal, the D terminal is connected to the post-signal for sampling the third data, and the Q terminal is connected to the delayed signal of the post-signal for sampling the third data; The positive input terminal of the first selector is connected to the Q terminal of the third flip-flop, and the negative input terminal is connected to the Q terminal of the fourth flip-flop.

[0045] In the embodiment of the present invention, the first selector makes a signal selection according to whether it is an enable signal of the two-phase clock. If the third data sampling circuit operates in the two-phase clock mode, then one more clock cycle is added after the original D3 POST to obtain D3 POST POST. If it is in the four-phase mode, no modification is required for D3 POST.

[0046] Preferably, it further includes: a first data sampling circuit; The first data sampling circuit includes: a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, an eighth flip-flop and a second selector; The D terminal of the fifth flip-flop is connected to the input signal for sampling the first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the inverted clock signal; The D terminal of the sixth flip-flop is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal; The D terminal of the seventh flip-flop is connected to the pre-signal for sampling the first data, the Q terminal is connected to the main signal for sampling the first data, and the CK terminal is connected to the inverted clock signal; The D terminal of the eighth flip-flop is connected to the main signal for sampling the first data, the Q terminal is connected to the post-signal for sampling the first data, and the CK terminal is connected to the clock signal; The positive input terminal of the second selector is connected to the input signal for sampling the first data.

[0047] In the embodiment of the present invention, the position of the selector needs to be moved forward to compensate for the timing misalignment problem in the four-phase clock mode. Figure 3 By adjusting the appearance position of the second selector, the Tck-q of the last stage can be made consistent with the timing of the next stage. Such adjustment will also cause the D3_PRE and D3_MAIN in the original signal to be misaligned again and generate incorrect data. However, there is still a group of D1 data mentioned before that has not been used. If changes are made in the path of the D1 data and then D3_POST in the two-phase clock mode is connected to D1_POST in the connection diagram, the timing misalignment problem and the problem of data not being transmitted with a sampling clock can be solved.

[0048] Embodiment 3 An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for a four-phase clock and two-phase clock compatible FFE system.

[0049] Embodiment 4 A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for a four-phase clock and two-phase clock compatible FFE system.

[0050] In the present invention, switching to use a two-phase clock in a low-speed protocol can reduce the calibration of a necessary set of DCCs and the phase calibration between clocks, effectively improving noise and power consumption. The present invention uses a two-phase clock as the input clock of the DFF. Although a part of the setup time is sacrificed, a large amount of power consumption is saved, and this part of the circuit also becomes compatible. The present invention only requires a small part of the circuit to be modified to be compatible with both a four-phase clock and a two-phase clock, and does not affect the setup time of data sampling.

[0051] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A four-point clock and two-point clock compatible FFE method, characterized in that: include: In the four-phase clock mode, a slow clock is used to convert six-beat data into three-beat data; When the four-phase clock mode is converted to the two-phase clock mode, the 0° and 180° phase clocks are used for beating; When the four-phase clock mode is converted to the two-phase clock mode, using the 0° and 180° phase clocks to beat includes: A mode that uses two phases of a four-phase clock as the clock for DFF is added to FFE; When the four-phase clock is switched to the two-phase clock, the two clocks of the four-phase clock are set to CK90:0 CK270:1 by RST, that is, the two clocks are turned off; Adjacent clocks AND generate sampling clock PULSE, reducing the original 4 sampling clock PULSE to two, and these are the sampling clock PULSE of the last two phases, namely 0° and 180° phase clocks; When the sampling clock becomes two-phase, the third data and the fourth data in the four groups of data of the four-phase clock are fully multiplexed; Connecting the first data transmission line of the four-phase clock to the third data transmission line; Connecting the second data transmission line of the four-phase clock to the fourth data transmission line; In the two-phase clock mode, a one-beat delay is added after the sampling clock of the fourth data group.

2. A four-minute clock and two-minute clock compatible FFE method according to claim 1, characterized in that: In the four-phase clock mode, the method of converting the six-beat data into three-beat data using the slow clock also includes pre-processing the data, specifically: The data is retimed before entering 4to1mux; Add two extra data before and after the current data to complete data preprocessing.

3. A four-minute clock and two-minute clock compatible FFE method according to claim 1, characterized in that: The method of connecting the first data transmission line of the four-phase clock to the third data transmission line comprises: Control selector according to clock mode of FFE system; When the FFE system is in the two-phase clock mode, the first data transmission line of the four-phase clock is connected to the third data transmission line.

4. A four-minute clock and two-minute clock compatible FFE method according to claim 1, characterized in that: The step of connecting the second data transmission line of the four-phase clock to the fourth data transmission line comprises: Control selector according to clock mode of FFE system; When the FFE system is in a two-phase clock mode, when the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data.

5. A four-minute clock and two-minute clock compatible FFE system, applied to a four-minute clock and two-minute clock compatible FFE method according to any one of claims 1 to 4, characterized in that: include: A third data sampling circuit; The third data sampling circuit includes: a first trigger, a second trigger, a third trigger, a fourth trigger and a first selector; The CK terminal of the first trigger is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data; The CK terminal of the second flip-flop is connected to the reverse clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data; The CK terminal of the third trigger is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post signal for sampling the third data; The CK terminal of the fourth trigger is connected to the reverse clock signal, the D terminal is connected to the post signal of the sampling third data, and the Q terminal is connected to the delayed signal of the post signal of the sampling third data; The positive input terminal of the first selector is connected to the Q terminal of the third trigger, and the negative input terminal of the first selector is connected to the Q terminal of the fourth trigger.

6. A four-minute clock and two-minute clock compatible FFE system according to claim 5, characterized in that: Also includes: a first data sampling circuit; The first data sampling circuit includes: a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger and a second selector; The D terminal of the fifth trigger is connected to the input signal of the sampled first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the reverse clock signal; The D terminal of the sixth trigger is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal; The D terminal of the seventh trigger is connected to the pre-signal of sampling the first data, the Q terminal is connected to the main signal of sampling the first data, and the CK terminal is connected to the reverse clock signal; The D terminal of the eighth trigger is connected to the main signal of the sampled first data, the Q terminal is connected to the post signal of the sampled first data, and the CK terminal is connected to the clock signal; The positive input terminal of the second selector is connected to an input signal of the sampled first data.

7. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a four-minute clock and two-minute clock compatible FFE method as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a four-minute clock and two-minute clock compatible FFE method as described in any one of claims 1 to 4.

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