Preparation method of semiconductor storage device

Abstract

The invention provides a preparation method of a semiconductor storage device, and is applied to the technical field of semiconductor preparation. In the invention, a photoresist layer and a photomask are not arranged, and the whole substrate is subjected to ion implantation for the first time, so that the purposes of reducing the photomask forming the first well region and the second well region, photoetching and other related processes are achieved, and then inversion ions are neutralized through subsequently implanted ions, so that the yield of the semiconductor device is improved. The third well region and the fourth well region which are opposite in conduction type are correspondingly formed, so that the purposes of reducing the steps of the manufacturing process, reducing the manufacturing cost of the embedded flash memory chip and improving the product competitiveness are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for manufacturing a semiconductor memory device. Background Art

[0002] In order to reduce the production cost of a single chip, the critical dimension of the embedded flash memory is continuously reduced to increase the number of chips on a single wafer. Currently, for small-sized fabs such as 8-inch fabs, due to the limitations of the machine capabilities, the continuous reduction of the critical dimension of the chip has reached the machine limit. Therefore, how to reduce the number of photolithography layers through process optimization has become an effective way to improve the competitiveness of small-sized products such as 8-inch wafers. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for manufacturing a semiconductor memory device, so as to reduce the steps of the manufacturing process, reduce the manufacturing cost of the embedded flash memory chip, and improve the product competitiveness.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor memory device, which at least includes the following steps:

[0005] Provide a substrate, including a first CMOS device region and a second CMOS device region with different operating voltages, where each CMOS device region includes a PMOS region and an NMOS region;

[0006] Form a floating gate layer and a mask layer stacked on top of each other, on the substrate in the first CMOS device region and the second CMOS device region;

[0007] Perform a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region;

[0008] Form a first photoresist layer on the mask layer in the PMOS regions of the first CMOS device region and the second CMOS device region;

[0009] Perform a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0010] In some optional examples, the conduction types of the doping ions in the first well region and the second well region are the same, and the doping ions include P-type ions.

[0011] In some optional examples, the concentration of the doping ions in the first well region is less than the concentration of the doping ions in the second well region.

[0012] In some alternative examples, the method for manufacturing the semiconductor memory device further includes:

[0013] Removing the mask layer and the floating gate layer in the first CMOS device region and the second CMOS device region.

[0014] In some alternative examples, after forming the second well region, it further includes:

[0015] Forming a second photoresist layer on the substrate that is newly exposed in the NMOS regions of the second CMOS device region and the first CMOS device region; and,

[0016] Performing a third ion implantation process on the substrate to form a third well region in the substrate corresponding to the PMOS region of the first CMOS device region.

[0017] In some alternative examples, after forming the second well region, it further includes:

[0018] Forming a third photoresist layer on the substrate that is newly exposed in the NMOS regions of the first CMOS device region and the second CMOS device region; and,

[0019] Performing a fourth ion implantation process on the substrate to form a fourth well region in the substrate corresponding to the PMOS region of the second CMOS device region.

[0020] In some alternative examples, the operating voltage of the first CMOS device region is greater than the operating voltage of the second CMOS device region.

[0021] In some alternative examples, the third well region and the fourth well region have the same conductivity type of doped ions, and the doped ions include N-type ions.

[0022] In some alternative examples, the concentration of doped ions in the third well region is less than the concentration of doped ions in the fourth well region.

[0023] In some alternative examples, the method for manufacturing the semiconductor memory device further includes: the substrate further includes a storage region, and the second photoresist layer and the third photoresist layer also compressively cover the substrate of the storage region.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] The present invention provides a method for manufacturing a semiconductor storage device, comprising: providing a substrate including a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region; forming a floating gate layer and a mask layer stacked on top of each other from bottom to top, located on the substrate of the first CMOS device region and the second CMOS device region; performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; forming a first photoresist layer on the mask layer in the PMOS regions of the first CMOS device region and the second CMOS device region; and performing a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0026] In the present invention, first, by not providing a photoresist layer and a photomask, a first ion implantation is performed on the entire substrate. While forming a first well region in the substrate corresponding to the NMOS region in the first CMOS device region, a low-dose P-type ion implantation is performed on other regions of the substrate. Then, a part of the substrate is shielded by forming a first photoresist layer, and a second well region with a high ion concentration is formed by the superposition of the P-type ion implantation in the second ion implantation and the P-type ion implantation in the first ion implantation in the substrate corresponding to the NMOS region in the second CMOS device region and inside it. Then, a part of the substrate is shielded by using a second photoresist layer and a third photoresist layer, and high-dose N-type ion implantations of a third ion implantation and a fourth ion implantation are performed. Thus, after neutralizing the P-type ions (ions implanted in the first ion implantation process) in the PMOS regions in the first CMOS device region and the second CMOS device region, third well regions and fourth well regions of N-type doping type are further formed, thereby reducing the photomasks, photolithography and other related processes for forming the first well region and the second well region, achieving the purpose of reducing the process steps of the manufacturing process, reducing the manufacturing cost of the embedded flash memory chip, and improving the product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:

[0028] Figure 1 It is a schematic flowchart of the method for manufacturing a semiconductor storage device in an embodiment of the present invention.

[0029] Figures 2 to 10 It is a schematic structural diagram of the semiconductor storage device provided in an embodiment of the present invention during the manufacturing process.

[0030] Wherein, in Figures 2 to 10 :

[0031] 100 - Substrate; 101 - Storage area, 102 - Logic area, 102HN - High - voltage PMOS area, 102HP - High - voltage NMOS area, 102LN - Low - voltage PMOS area, 102LP - Low - voltage NMOS area, 110 - Coupling oxide layer, 120 - Floating gate layer, 130 - Mask layer, 140 - Shallow trench isolation structure, 150 - First photoresist layer, 160 - Memory cell, 170 - Second photoresist layer, HPW - First well region, 180 - Third photoresist layer, LPW - Second well region, HNW - Third well region, LNW - Fourth well region, 191 - Word - line polysilicon layer, 192 - First dielectric layer, 201 - High - voltage gate oxide layer, 202 - High - voltage polysilicon layer, 210 - Fourth photoresist layer, 220 - Fifth photoresist layer.

[0032] In the drawings, like components are denoted by like reference numerals, and the drawings are not drawn to scale. Detailed embodiments

[0033] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided so as to more thoroughly understand the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0034] The present invention will be described more specifically by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and are not drawn to precise scale, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on", "above" and "over" in the present invention should be interpreted in the broadest way, so that "on" not only means "on" something without any intervening features or layers (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers.

[0035] In addition, for the sake of convenience of description, spatial relative terms such as "on", "above", "over", "upper", etc. may be used in this article to describe the relationship between one element or feature and another element or feature as shown in the drawings. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein can be interpreted accordingly.

[0036] In the embodiments of the present invention, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0037] Please refer to Figure 1 , which shows a flowchart of a method for manufacturing a semiconductor memory device in an embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture an embedded flash memory device. Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories.

[0038] As Figure 1 shown, the method for manufacturing the semiconductor memory device includes the following steps:

[0039] Step S101: Provide a substrate including a first CMOS device region and a second CMOS device region with different operating voltages, where each CMOS device region includes a PMOS region and an NMOS region.

[0040] Step S102: Form a floating gate layer and a mask layer stacked in sequence from bottom to top on the substrate in the first CMOS device region and the second CMOS device region.

[0041] Step S103: Perform a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region.

[0042] Step S104: Form a first photoresist layer on the mask layer in the PMOS regions of the first CMOS device region and the second CMOS device region.

[0043] Step S105: Perform a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0044] In the method for manufacturing a semiconductor memory device of the present invention, a storage region is used to fabricate MOS transistors of memory cells of a semiconductor memory device such as an embedded flash memory device, and a logic region is used to fabricate logic MOS devices of a semiconductor memory device such as an embedded flash memory device. Moreover, the logic region can be specifically divided into a high-voltage device region, a low-voltage region, etc. based on the actual operating voltage of the logic MOS device, but not limited thereto. Therefore, the present invention can reduce the related processes such as masks and photolithography for forming the first well region and the second well region by performing a first ion implantation on the entire substrate without setting a photoresist layer and a mask. Then, through the neutralization of the inverted ions by the subsequently implanted ions, the third well region and the fourth well region with opposite conduction types are correspondingly formed, thereby reducing the process steps of the manufacturing process, reducing the manufacturing cost of the embedded flash memory chip, and improving the product competitiveness.

[0045] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the method for manufacturing a semiconductor memory device in the embodiments of the present invention, the method for manufacturing a semiconductor memory device proposed by the present invention will be further described below in conjunction with various structural schematic diagrams in the manufacturing process of the manufacturing method. Please refer to Figures 2 to 10 As shown, what is illustrated is a structural schematic diagram in the manufacturing process of the method for manufacturing a semiconductor memory device provided in the embodiments of the present invention.

[0046] Execute the above step S101. Please refer to Figure 2, a substrate 100 is provided, and the substrate 100 may include a storage area 101 and a logic area 102. In an embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a group III-V compound substrate (such as a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate, or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates well-known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but not limited thereto. The storage area 101 and the logic area 102 may be arranged adjacent to each other, but not limited thereto. The logic area 102 may specifically include a first CMOS device area and a second CMOS device area with different operating voltages. Each CMOS device area may include a PMOS area and an NMOS area. Exemplarily, the first CMOS device area may be a high-voltage device area, and the second CMOS device area may be a low-voltage device area. The first CMOS device area may specifically include a high-voltage PMOS area 102HN for forming a PMOS transistor and a high-voltage NMOS area 102HP for forming an NMOS transistor. Similarly, the second CMOS device area may also specifically include a low-voltage PMOS area 102LN for forming a PMOS transistor and a low-voltage NMOS area 102LP for forming an NMOS transistor, but not limited thereto.

[0047] Execute the above step S102, please continue to refer to Figure 2 , by using a deposition process such as at least one of chemical vapor deposition process, physical vapor deposition process, and atomic layer deposition process, a layer-coupled oxide layer 110, a floating gate layer 120, and a mask layer 130 are sequentially formed in a stacked manner from bottom to top on the entire surface of the substrate 100; then, by using photolithography and etching processes, the plurality of shallow trench isolation structures 140 are formed, and on the substrate 100; then, by using a deposition process such as chemical vapor deposition process, the substrate 100 is divided into the storage area 101 and the logic area 102. In an embodiment, the materials of the coupled oxide layer 110 and the shallow trench isolation structures 140 may be oxides, such as silicon dioxide, the material of the floating gate layer 120 is a conductive material, such as polysilicon, the material of the mask layer 130 is an insulating material, such as silicon nitride, and the top surface of the shallow trench isolation structures 140 may be flush with the top surface of the mask layer 130 (as shown in Figure 2 ), or its top surface may be slightly lower than the top surface of the mask layer 130 (not shown), but not limited thereto.

[0048] Execute the above step S103, please continue to refer to Figure 2, without setting any photomask and photoresist layer, a first ion implantation process is performed on the entire substrate 100 of the storage area 101 and the logic area 102, so as to perform the first ion implantation in each substrate 100 area of the storage area 101 and the logic area 102 separated by the shallow trench isolation structure 140. In an embodiment, the ion type implanted in the first ion implantation process is P-type ions, such as phosphorus ions. Since the ion concentration required for the well region corresponding to the high-voltage NMOS region 102HP in the first CMOS device region in the logic area 102 is low, therefore, in the embodiment of the present invention, the concentration of the ions implanted in the first ion implantation process can be the same as the ion implantation concentration for forming the well region (i.e., the first well region HPW) of the high-voltage NMOS region in the logic area in the prior art. The difference between the present invention and the prior art is that: in the process of forming the first well region HPW of the high-voltage NMOS region in the logic area, the present invention synchronously performs low-concentration or low-dose P-type ion implantation in the substrate 100 of the storage area 101 and other regions of the logic area 102 of the substrate 100. Under this setting, the preparation method provided in the embodiment of the present invention can form the first well region HPW of the high-voltage NMOS region in the logic area without using any photomask, photolithography and other manufacturing processes, that is, the purpose of reducing the photomask, photolithography and other related processes for forming the first well region HPW of the high-voltage NMOS region is achieved.

[0049] Perform the above steps S104 and S105, please refer to Figure 3 , a first photoresist layer 150 can be formed on the mask layer 130 below the PMOS region 102LN in the first CMOS device region and the second CMOS device region by using a deposition process such as physical vapor deposition process. Then, a second ion implantation process is performed on the corresponding region of the substrate 100 that is not shielded by the first photoresist layer 150 (or the region exposed by the first photoresist layer 150) by using an ion implantation process, so as to form a second well region LPW. In an embodiment, the first photoresist layer 150 exposes the storage area 101 and the low-voltage NMOS region 102LP of the logic area 102. The ion type implanted in the second ion implantation process is P-type ions, and since the doping ion concentration of the low-voltage NMOS region 102LP in the logic area 102 needs to be greater than the ion concentration of the first well region HPW of the high-voltage NMOS region, therefore, after the P-type ion implantation of the first and second ion implantation processes in the embodiment of the present invention, well regions that meet the requirements corresponding to the high-voltage and low-voltage NMOS transistors in the logic area of the embedded flash memory device can be formed with different doping ion concentrations.

[0050] It should be understood that parameters such as the implantation dose and concentration of the P-type ions implanted in the second ion implantation process in the embodiments of the present invention are related to the parameters such as the implantation dose and concentration of the P-type ions implanted in the first ion implantation process. That is, since the total ion concentration in the second well region LPW is accumulated through the above two ion implantation processes, in order to make the ion concentration of the well regions in each region formed in the logic region 102 of the substrate 100 meet the design requirements, the parameters such as the implantation dose and concentration of the P-type ions implanted in the second ion implantation process can be adaptively adjusted based on the parameters such as the implantation dose and concentration of the P-type ions implanted in the first ion implantation process, but not limited thereto.

[0051] Continuing with the above step S105, please refer to Figure 4 , at least one of etching processes such as dry etching process or wet etching process can be used to remove the mask layer 130 and the floating gate layer 120 in the first CMOS device region and the second CMOS device region in the logic region 102, so as to expose the coupling oxide layer 110 in the logic region 102 again. Further, by using etching and deposition processes, a memory cell 160 of the embedded flash memory device is correspondingly formed on the substrate of the memory region 101, where the memory cell 160 may include components and / or devices such as a floating gate layer (not labeled), sidewalls (not labeled), a shared source line (not labeled), and a tunneling oxide layer (not labeled), but not limited thereto. Then, by using a deposition process such as chemical vapor deposition process, a second photoresist layer 170 is formed on the substrate 100 exposed again in the memory region 101, the second CMOS device region of the logic region 102, and the high-voltage NMOS region 102HP of the first CMOS device region. That is, the second photoresist layer 170 has an opening that exposes the substrate 100 corresponding to the high-voltage PMOS region 102HN in the first CMOS device region in the logic region 102.

[0052] Next, a third ion implantation process is performed on the substrate 100 corresponding to the high-voltage PMOS region 102HN in the first CMOS device region exposed by the opening, so as to form a third well region HNW in the substrate 100 corresponding to the PMOS region 102HN in the first CMOS device region. In one embodiment, the type of ions implanted in the third ion implantation process is N-type ions, that is, the type of ions implanted in the third ion implantation process is opposite to the type of ions implanted in the first ion implantation process or the second ion implantation process, and parameters such as the concentration and dose of the N-type ions implanted in the third ion implantation process are related to the parameters such as the concentration and dose of the P-type ions implanted in the first ion implantation process. Since in the embodiment of the present invention, when performing the first ion implantation process, P-type ion implantation is performed in each region of the substrate 100, therefore, in the process of forming the N-type doped third well region HNW by using the third ion implantation process, it is necessary to use the N-type ions implanted in the third ion implantation process to first neutralize the P-type ions in the substrate 100 corresponding to the PMOS region 102HN in the first CMOS device region, and then the N-type ions continuously implanted in the third ion implantation process further form the third well region HNW in this region. After that, a second photoresist layer 170 is removed by using an etching process such as a dry etching process.

[0053] Continuing from the above step S105, please refer to Figure 5 , a third photoresist layer 180 can be first formed on the substrate 100 newly exposed in the low-voltage NMOS regions 102LN of the first CMOS device region and the second CMOS device region by using a deposition process such as chemical vapor deposition. Then, under the shielding of the third photoresist layer 180, a fourth ion implantation process is performed on the substrate 100 corresponding to the low-voltage PMOS region 102LN in the second CMOS device region of the logic region 102 exposed by the third photoresist layer 180, so as to form a fourth well region LNW in the substrate 100 corresponding to this region. Based on the same principle as forming the third well region HNW, the type of ions implanted in the fourth ion implantation process in the embodiment of the present invention is N-type, and parameters such as the implantation dose and concentration of the N-type ions implanted in the fourth ion implantation process are related to the parameters such as the implantation dose and concentration of the P-type ions implanted in the first ion implantation process, which will not be described in detail here. In one embodiment, the concentration of N-type doped ions in the third well region HNW is less than the concentration of N-type doped ions in the fourth well region LNW.

[0054] Continuing from the above step S105, please refer to Figure 6, further using a deposition process such as chemical vapor deposition process, a word line polysilicon layer 191 and a first dielectric layer 192 stacked from bottom to top are conformally formed on the film layer structures corresponding to the storage area 101 and the logic area 102 of the substrate 100. In one embodiment, the material of the word line polysilicon layer 191 is polysilicon, and the material of the first dielectric layer 192 is an insulating material, such as silicon dioxide.

[0055] Continuing from the above step S105, please refer to Figure 7 , first form a photoresist layer (not shown) that shields the storage area 101 of the substrate 100 and part of the logic area 102. Among them, the exposed part of the logic area 102 of the photoresist layer can be the first CMOS device area. Then, using this photoresist layer as a mask, by using an etching process such as a dry etching process, the first dielectric layer 192 and the word line polysilicon layer 191 exposed in the first CMOS device area of the logic area 102 that are not shielded by the photoresist layer are removed to re-expose the coupling oxide layer 110 in the first CMOS device area.

[0056] Continuing from the above step S105, please refer to Figure 8 , further using a deposition process such as chemical vapor deposition process, a high-voltage gate oxide layer 201 and a high-voltage polysilicon layer 202 are formed on the substrate 100 of the storage area 101 and the logic area 102. Among them, the high-voltage gate oxide layer 201 is used as the gate oxide of the high-voltage device NMOS transistor and PMOS transistor, and the material of the high-voltage polysilicon layer 202 can be polysilicon and is used as the gate layer of the high-voltage device NMOS transistor and PMOS transistor.

[0057] Continuing from the above step S105, please refer to Figure 9 , a fourth photoresist layer 210 can be formed on the substrate 100 by using a deposition process such as chemical vapor deposition process, and part of the high-voltage polysilicon layer 202 and part of the high-voltage gate oxide layer 201 are etched and removed by using an etching process such as a dry etching process to form at least one discrete gate structure on the substrate 100 of the logic area 102; then the fourth photoresist layer 210 is removed.

[0058] Continuing from the above step S105, please refer to Figure 10 , a fifth photoresist layer 220 can be formed on the substrate 100 by using a deposition process such as chemical vapor deposition process, and part of the film layers in the second CMOS device area of the logic area 102 are etched and removed by using an etching process such as a dry etching process until a plurality of discrete gate structures are formed in the second CMOS device area; then the fifth photoresist layer 220 is removed.

[0059] It should be understood that in the embodiments of the present invention, "conformal" means constructing a continuous structural shape by utilizing the similarity and relevance in the morphology between two or more shapes.

[0060] In summary, the present invention provides a method for manufacturing a semiconductor storage device, including: providing a substrate including a first CMOS device region and a second CMOS device region with different operating voltages, where each CMOS device region includes a PMOS region and an NMOS region; forming a floating gate layer and a mask layer stacked in sequence from bottom to top on the substrate of the first CMOS device region and the second CMOS device region; performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; forming a first photoresist layer on the mask layer in the PMOS regions of the first CMOS device region and the second CMOS device region; performing a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0061] In the present invention, first, by not setting a photoresist layer and a photomask, a first ion implantation is performed on the entire substrate. While forming a first well region in the substrate corresponding to the NMOS region in the first CMOS device region, a low-dose P-type ion implantation is also performed on other regions of the substrate. Then, a part of the substrate is shielded by forming a first photoresist layer, and a second well region with a high ion concentration is formed by the superposition of the P-type ion implantation in the second ion implantation on the substrate corresponding to the NMOS region in the second CMOS device region and the P-type ion implantation in the first ion implantation therein. Then, a part of the substrate is shielded by using a second photoresist layer and a third photoresist layer, and high-dose N-type ion implantations of the third ion implantation and the fourth ion implantation are performed, so as to neutralize the P-type ions (ions implanted in the first ion implantation process) in the PMOS regions in the first CMOS device region and the second CMOS device region, and then further perform N-type doping for the third well region and the fourth well region. Thereby, the photomasks, photolithography and other related processes for forming the first well region and the second well region are reduced, the steps of the manufacturing process are reduced, the manufacturing cost of the embedded flash memory chip is reduced, and the product competitiveness is improved.

[0062] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor storage device, characterized in that: include: Providing a substrate, including a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region; Forming a floating gate layer and a mask layer stacked sequentially from bottom to top, located on the substrate in the first CMOS device area and the second CMOS device area; Performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; Forming a first photoresist layer on the mask layer in the PMOS region of the first CMOS device region and the second CMOS device region; A second ion implantation process is performed on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

2. The method for preparing a semiconductor memory device according to claim 1, wherein: The conductivity type of the doped ions in the first well region and the second well region is the same, and the doped ions include P-type ions.

3. The method for preparing a semiconductor memory device according to claim 1, wherein: The concentration of doped ions in the first well region is lower than the concentration of doped ions in the second well region.

4. The method for preparing a semiconductor memory device according to claim 3, wherein: Also includes: The mask layer and the floating gate layer in the first CMOS device region and the second CMOS device region are removed.

5. The method for preparing a semiconductor memory device according to claim 4, wherein: After forming the second well region, the method further comprises: forming a second photoresist layer on the re-exposed substrate in the second CMOS device region and the NMOS region of the first CMOS device region; and, A third ion implantation process is performed on the substrate to form a third well region in the substrate corresponding to the PMOS region of the first CMOS device region.

6. The method for preparing a semiconductor memory device according to claim 5, wherein: After forming the second well region, the method further comprises: forming a third photoresist layer on the re-exposed substrate in the NMOS region of the first CMOS device region and the second CMOS device region; and, A fourth ion implantation process is performed on the substrate to form a fourth well region in the substrate corresponding to the PMOS region of the second CMOS device region.

7. The method for preparing a semiconductor memory device according to any one of claims 1 to 6, characterized in that: An operating voltage of the first CMOS device area is greater than an operating voltage of the second CMOS device area.

8. The method for preparing a semiconductor memory device according to claim 6, wherein: The doping ions of the third well region and the fourth well region have the same conductivity type, and the doping ions include N-type ions.

9. The method for manufacturing a semiconductor memory device according to claim 6, wherein: The concentration of doped ions in the third well region is lower than the concentration of doped ions in the fourth well region.

10. The method for manufacturing a semiconductor memory device according to claim 6, wherein: Also includes: The substrate further includes a storage area, and the second photoresist layer and the third photoresist layer are further compressed and covered on the substrate in the storage area.

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