Wafer-level chip segmentation method

Abstract

The embodiment of the invention provides a wafer-level chip segmentation method, and relates to the technical field of silicon optical wafer-level chips. The wafer level chip method comprises: providing a wafer (101); coating photoresist (103) on the pattern surface of the wafer (101), exposing a cutting channel (102) for chip separation by means of exposure and development, and protecting pattern layers of other areas by the photoresist (103); etching the cutting channel (102) to a set depth by using a dry method or a wet method, the set depth being smaller than the final chip thickness; and covering the back surface of the wafer (101) with an expandable film (105), and performing laser stealth dicing on the wafer (101) to obtain a plurality of single chips. And damage such as edge breakage and breakage is not prone to occurring during cutting, the formed side face is smooth in appearance, and finally the high yield is obtained.

Description

Technical Field

[0001] This application relates to the technical field of silicon photonic wafer-level chips, and particularly to a method for slicing wafer-level chips. Background Art

[0002] Reference Solution 1: In the patent document with the publication number CN 109326560 A, the method for separating wafer chips is as follows: Through holes are formed along the cutting lines of the wafer. Then, the wafer is attached with a tape. As the tape is stretched, the wafer is separated into chips along the cutting lines, that is, relying on the pulling force of the tape, the through holes break to achieve chip separation. In the actual separation process of silicon photonic wafers, this solution will cause the substrate material to extend and break, resulting in chipping, debris, etc., and further leading to a decrease in chip separation quality and product yield. In addition, relying on the sidewall cross-section formed by the through holes, the side surface morphology is poor. For silicon photonic wafers, there are optical ports on the sidewalls, and the poor sidewall morphology will affect the performance of silicon photonic chips.

[0003] Reference Solution 2: In the patent document with the publication number CN 110379771 A, the wafer separation method relies on a mechanical knife cut. However, the mechanical heat generated during this process is likely to cause chipping, resulting in great damage to silicon photonic wafer chips, and the yield cannot meet the requirements of silicon photonic wafer chips. In addition, mechanical cutting has requirements for the width of the surface cutting track, limited utilization rate of the wafer itself, low cutting efficiency of the tool for cutting silicon wafer chips, and there is a curling phenomenon, which is prone to chipping, cracking, etc., resulting in a low finished product rate.

[0004] How to improve the separation quality of silicon photonic wafers and effectively avoid damage to silicon photonic wafer chips during the separation process is the technical problem to be solved by this application. Summary of the Invention

[0005] The purpose of this application is to provide a method for slicing wafer-level chips to solve the technical problem in the prior art of how to improve the separation quality of silicon photonic wafers and effectively avoid damage to silicon photonic wafer chips during the separation process.

[0006] The method for slicing wafer-level chips includes:

[0007] Provide a wafer (101), with two sides of the wafer (101) being a pattern side and a back side respectively;

[0008] Apply a photoresist (103) on the pattern side of the wafer (101). Through the method of exposure and development, the cutting tracks (102) for chip separation are exposed, and at the same time, the photoresist (103) protects the layers in other areas;

[0009] Use dry or wet etching to etch the cutting tracks (102) to a set depth, and the set depth is less than the final chip thickness;

[0010] An expandable film (105) is covered on the back surface of the wafer (101), and the wafer (101) is subjected to laser stealth dicing to obtain a plurality of single chips.

[0011] The present application has the following beneficial effects:

[0012] Compared with the separation and dicing methods of the prior art, in this wafer-level chip dicing method, etching is first performed to a certain depth, and then laser cutting is used. At this time, dicing is not prone to damage such as chipping and cracking, and the formed side surface morphology is flat, and finally a high yield is obtained.

[0013] Optionally, after the wafer (101) is subjected to laser stealth dicing, the wafer-level chip dicing method further includes:

[0014] Expanding the expandable film (105), and the expandable film (105) drives the single chips to separate.

[0015] The beneficial effect of the expandable film (105) is that it is easy to increase the distance between different single chips by expansion, so as to facilitate the picking of single chips.

[0016] Optionally, the step of expanding the expandable film (105) includes:

[0017] Fixing the outer periphery of the expandable film (105), and using a heating plate to push up the expandable film (105) to expand the expandable film (105).

[0018] Fixing the outer periphery of the expandable film (105) and using a heating plate to push up has the beneficial effect that this expansion method is easy to be realized by equipment automation, and the movement stroke is a simple linear motion.

[0019] Optionally, the heating temperature of the heating plate is 30°C to 50°C.

[0020] The beneficial effect of heating is to facilitate expansion, and the heating temperature is appropriate to avoid damage to the chips caused by high temperature.

[0021] Optionally, after the cutting channel (102) is etched to a set depth and before the wafer (101) is subjected to laser stealth dicing, the wafer-level chip dicing method further includes:

[0022] Removing the photoresist (103) and covering a protective film on the pattern surface of the wafer (101).

[0023] The function of the protective film is to protect the pattern surface of the wafer (101) and avoid accidental damage during steps such as laser cutting.

[0024] Optionally, the protective film is a back grinding tape;

[0025] After covering the patterned surface of the wafer (101) with a protective film, the wafer-level chip dicing method further includes:

[0026] Grinding the back surface of the wafer (101) to thin it down to a set chip thickness.

[0027] Inserting a thinning process at this time. The processes before thinning are applicable to thicker wafers, which can reduce the process difficulty. After thinning, it is beneficial to reduce the occupied volume of the chip. Thinning can also improve the heat dissipation performance of the chip: wafer thinning can significantly reduce the thermal resistance, enabling the heat generated by the chip to be dissipated more quickly.

[0028] Optionally, after grinding the back surface of the wafer (101) to thin it down to a set chip thickness, irradiate the back grinding tape with ultraviolet light.

[0029] The beneficial effect of irradiating the back grinding tape with ultraviolet light is to reduce the adhesion of the back grinding tape, facilitating the subsequent non-destructive peeling of the wafer or chip, and there is basically no residual glue during peeling, avoiding contamination of the wafer surface and the chip. The ultraviolet light irradiation has a fast reaction speed and can quickly complete the conversion of the tape adhesion.

[0030] Optionally, after irradiating the back grinding tape with ultraviolet light, do not remove the back grinding tape temporarily until after laser stealth dicing of the wafer (101), and then remove the back grinding tape.

[0031] The beneficial effect of performing laser stealth dicing while retaining the back grinding tape in this embodiment is that the back grinding tape can play a protective role during the laser stealth dicing stage. Removing the back grinding tape is beneficial for subsequent separation processing.

[0032] Optionally, after laser stealth dicing of the wafer (101), the wafer-level chip dicing method further includes:

[0033] Removing the back grinding tape, and then expanding the expandable film (105), and the expandable film (105) drives the separation of the single chips.

[0034] Removing the back grinding tape is beneficial for the separation between single chips.

[0035] Optionally, in the step of etching the cutting channel (102) to a set depth, the set depth is 1 / 5 of the final chip thickness.

[0036] This etching depth is beneficial for higher process efficiency and higher yield.

[0037] Optionally, after etching the scribe lane (102), the wafer-level chip dicing method further includes using the scribe lane (102) to insert a probe into the scribe lane for functional testing. At this time, the testing is beneficial to ensuring the yield rate. If there are problems, they can be discovered earlier and processed in a timely manner. Brief Description of the Drawings

[0038] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0039] Figure 1 Schematic diagram of a wafer 101 provided by an embodiment of the present application;

[0040] Figure 2 Schematic diagram of applying a photoresist 103 to the pattern side of a wafer 101 provided by an embodiment of the present application;

[0041] Figure 3 Schematic diagram of etching a scribe lane 102 to a set depth provided by an embodiment of the present application;

[0042] Figure 4 Schematic diagram of covering an expandable film 105 on the back side of a wafer 101 provided by an embodiment of the present application;

[0043] Figure 5 Schematic diagram of laser stealth dicing of a wafer 101 provided by an embodiment of the present application;

[0044] Figure 6 Schematic diagram of an expandable film 105 driving a single chip to move provided by an embodiment of the present application;

[0045] Figure 7 Schematic diagram of covering a protective film 104 on the pattern side of a wafer 101 provided by an embodiment of the present application;

[0046] Figure 8 Schematic diagram of covering an expandable film 105 on the back side of a wafer 101 after covering a protective film 104 on the pattern side of the wafer 101 provided by an embodiment of the present application;

[0047] Figure 9 Schematic diagram of laser stealth dicing of a wafer 101 on the basis of covering a protective film 104 on the pattern side of the wafer 101 provided by an embodiment of the present application;

[0048] Figure 10Schematic diagram of removing the protective film 104 after laser stealth dicing of the wafer 101 provided by an embodiment of the present application;

[0049] Figure 11 Schematic diagram of expanding the expandable film 105 after removing the protective film 104 provided by an embodiment of the present application;

[0050] Figure 12 Schematic diagram of fixing the outer periphery of the expandable film 105 and using a heating plate to push up the expandable film 105 provided by an embodiment of the present application.

[0051] Explanation of reference numerals:

[0052] 101 Wafer

[0053] 102 Dicing lane

[0054] 103 Photoresist

[0055] 104 Protective film

[0056] 105 Expandable film Detailed implementation manners

[0057] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. The described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application described herein are usually arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0059] An embodiment of the present application provides a wafer-level chip dicing method, and the wafer-level chip dicing method includes:

[0060] As Figure 1 , provide a wafer 101, with two sides of the wafer 101 being a pattern side and a back side respectively. In the figure, the upper side is the pattern side and the lower side is the back side;

[0061] As Figure 2 , apply a photoresist 103 on the pattern side of the wafer 101, and by means of exposure and development, expose the dicing lanes 102 for chip separation, and at the same time, the photoresist 103 protects the layers in other areas;

[0062] As Figure 3 , use dry or wet etching to etch the dicing channel 102 to a set depth, where the set depth is less than the final chip thickness; the set depth can be about 1 / 5 of the final chip thickness, i.e., between 1 / 4 and 1 / 6.

[0063] As Figure 4 , cover the back side of the wafer 101 with an expandable film 105.

[0064] As Figure 5 , perform laser stealth dicing on the wafer 101 to obtain multiple single chips, and a stealth dicing machine tool can be used for laser dicing.

[0065] After performing laser stealth dicing on the wafer 101, as Figure 6 , the expandable film 105 can be expanded, and the expandable film 105 drives the single chips to move, thereby increasing the distance between adjacent single chips and facilitating the picking up of single chips.

[0066] After etching the dicing channel 102, the probe can also be inserted into the dicing channel through the dicing channel 102 for functional testing.

[0067] In the above embodiment, during laser stealth dicing when the photoresist covers the pattern surface, the photoresist can play a protective role.

[0068] However, the above embodiment has drawbacks: the protective effect of the photoresist is weak. A protective film made of another material can be used for protection. Therefore, the wafer-level chip dicing method can be implemented in the following manner:

[0069] As Figure 1 , provide a wafer 101;

[0070] As Figure 2 , apply a photoresist 103 on the pattern surface of the wafer 101. Through the method of exposure and development, the dicing channel 102 for chip separation is exposed, and at the same time, the photoresist 103 protects the layers in other areas;

[0071] As Figure 3 , use dry or wet etching to etch the dicing channel 102 to a set depth, where the set depth is less than the final chip thickness;

[0072] As Figure 6 , remove the photoresist 103;

[0073] As Figure 7 , cover a protective film 104 on the pattern surface of the wafer 101;

[0074] As Figure 8 , at this time, cover the back side of the wafer 101 with an expandable film 105;

[0075] As Figure 9 , the wafer 101 is subjected to laser stealth dicing to obtain multiple single chips; the laser can penetrate through the protective film 104, and the protective film 104 can be made of a transparent material to enable the laser to penetrate better;

[0076] As Figure 10 , after the wafer 101 is subjected to laser stealth dicing, the protective film 104 is removed;

[0077] As Figure 11 , the expandable film 105 is expanded, and the expandable film 105 drives the single chips to separate from each other.

[0078] The above protective film can be a back grinding tape. The beneficial effect of using the back grinding tape as the above protective film is that it is convenient to add a thinning process. The wafer-level chip dicing method with a thinning process can be implemented in the following way:

[0079] As Figure 1 , a wafer 101 is provided;

[0080] As Figure 2 , a photoresist 103 is coated on the patterned surface of the wafer 101. By means of exposure and development, the dicing channels 102 for chip separation are exposed, and at the same time, the photoresist 103 protects the layers in other areas;

[0081] As Figure 3 , dry or wet etching is used to etch the dicing channels 102 to a set depth, and the set depth is less than the final chip thickness;

[0082] As Figure 6 , the photoresist 103 is removed;

[0083] As Figure 7 , a layer of back grinding tape is covered on the patterned surface of the wafer 101, and the back grinding tape serves as the protective film 104;

[0084] At this time, under the protection of the back grinding tape, a grinding machine can be used to grind the back surface of the wafer 101 to thin the wafer to the set chip thickness;

[0085] After the wafer is thinned to the set chip thickness, the back grinding tape can be removed, and then the steps of covering the expandable film 105 on the back surface of the wafer 101, performing laser stealth dicing on the wafer 101, and expanding the expandable film 105 can be continued.

[0086] However, there are drawbacks to immediately removing the back grinding tape after wafer thinning: after the back grinding tape is removed, the back grinding tape cannot play a role in protecting the patterned surface in subsequent processes.

[0087] Another implementation is that after the wafer is thinned to the set chip thickness, the back grinding tape can be left without removal first, and the protective effect of the back grinding tape can be continued. Under the protection of the back grinding tape, the steps of covering the expansion film 105 on the back of the wafer 101 and performing laser stealth dicing on the wafer 101 are continued, so as to obtain Figure 9 the structure shown

[0088] After obtaining Figure 9 the structure shown, the back grinding tape needs to be removed before expanding the expansion film 105

[0089] One way to remove the back grinding tape is to irradiate the back grinding tape with ultraviolet light first and then remove the back grinding tape. Irradiating the back grinding tape with ultraviolet light can reduce the viscosity of the back grinding tape, facilitate subsequent tape peeling, and there is basically no residual glue during peeling, avoiding contamination of the wafer surface and the chip. The ultraviolet light irradiation reaction speed is fast, and the tape viscosity conversion can be quickly completed

[0090] There are various implementation ways for the insertion position of the step of irradiating the back grinding tape with ultraviolet light

[0091] One implementation way is to irradiate the back grinding tape with ultraviolet light after obtaining Figure 9 the structure shown, and then immediately remove the back grinding tape

[0092] One implementation way is to irradiate the back grinding tape with ultraviolet light after back grinding the back of the wafer 101, then undergo laser stealth dicing, and after laser stealth dicing, remove the back grinding tape; this implementation way can first ensure that the viscosity of the back grinding tape is weakened, avoiding the adverse effect of laser on the viscosity

[0093] One implementation way is to irradiate the back grinding tape with ultraviolet light while undergoing laser stealth dicing after back grinding the back of the wafer 101, and after laser stealth dicing, remove the back grinding tape; this implementation way can save the time of the ultraviolet light irradiation process to the greatest extent, without reserving time for ultraviolet light irradiation, and improves the production efficiency

[0094] The expansion of the expansion film 105 can be used as the last step of the circular chip segmentation method, and there are various ways to expand the expansion film 105

[0095] One implementation way is to horizontally pull the two ends or the periphery of the expansion film 105 in a plane

[0096] Another implementation way is as shown in Figure 12, which is the outer periphery of the fixed expandable film 105. The heating plate is used to push up the expandable film 105 to expand the expandable film 105; the surface of the heating plate in contact with the expandable film 105 can be a circular flat surface and has a heating function. This embodiment can make the expansion of the expandable film 105 more uniform, and the heating function is beneficial to the expansion of the expandable film 105. For example, heating can soften the expandable film. The heating temperature of the heating plate is 30°C to 50°C. The heating temperature is appropriate to avoid damage to the chip caused by high temperature.

[0097] Based on the above embodiments, an embodiment of the present application further provides a semiconductor structure for the cutting step in the above wafer-level chip dicing method, such as Figure 9 , the semiconductor structure includes a wafer 101, and the two sides of the wafer 101 are a pattern side and a back side respectively; the pattern side of the wafer 101 has a dicing channel 102 etched to a set depth, and a protective film 104 is covered on the pattern side of the wafer 101, and an expandable film 105 is covered on the back side of the wafer 101.

[0098] The protective film 104 of the semiconductor structure can be a back grinding tape, and the protective film 104 can be removed by ultraviolet irradiation. The semiconductor structure can be formed into independent single chips after laser cutting, and then the expandable film 105 is used to separate the single chips from each other.

[0099] In summary, the present solution can achieve the following beneficial effects:

[0100] Applied in the processing of silicon photonics wafers, the pattern side of the silicon photonics wafer is always in a protected state, which can avoid damage to the layer during the process and provide good protection for the performance of silicon photonics chips;

[0101] The optical port area of the silicon photonics wafer chip for performance testing is located on both sides of the dicing channel. This solution can directly test the performance of silicon photonics products after the second etching, optimize production according to the yield situation, and reduce cost waste;

[0102] Effectively avoid damage to the silicon photonics wafer chip during the separation process, reduce the risk of cracking, and ensure the safety of the separation process;

[0103] Compared with mechanical cutting and other methods, there will be no debris, which can effectively reduce defects such as chipping and beveling, improve sidewall contamination, and improve the yield of silicon photonics products;

[0104] Reduce the mechanical heat problem during the separation of silicon photonics chips, achieve high-quality wafer chip separation, improve the strength and quality of the chips, and improve the separation efficiency of silicon photonics wafer chips;

[0105] Laser cutting helps to reduce the width of the dicing channel, increase the number of grains on the silicon photonics wafer, and improve the output rate of chips on the silicon photonics wafer per unit area;

[0106] Applicable to silicon photonic wafer chips of various thicknesses, the thickness can be adjusted according to actual requirements;

[0107] The requirements for materials and equipment are relatively low, so that the overall cost can be greatly reduced.

[0108] The device and system embodiments described above are only illustrative. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0109] The above is only a preferred specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A wafer-level chip dicing method, characterized in that Including: Providing a wafer (101), with two sides of the wafer (101) being a pattern side and a back side respectively; Coating a photoresist (103) on the pattern side of the wafer (101), and by means of exposure and development, exposing the scribing lanes (102) for chip separation, and at the same time, the photoresist (103) protecting the layers in other areas; Using dry or wet etching to etch the scribing lanes (102) to a set depth, the set depth being less than the final chip thickness; Covering an expandable film (105) on the back side of the wafer (101), and performing laser stealth dicing on the wafer (101) to obtain multiple single chips.

2. The wafer-level chip dicing method according to claim 1, wherein After performing laser stealth dicing on the wafer (101), the wafer-level chip dicing method further includes: Expanding the expandable film (105), and the expandable film (105) driving the separation of the single chips.

3. The wafer-level chip dicing method according to claim 2, wherein The step of expanding the expandable film (105) includes: Fixing the outer periphery of the expandable film (105), and using a hot plate to push up the expandable film (105) to expand the expandable film (105).

4. The wafer-level chip dicing method according to claim 3, wherein The heating temperature of the hot plate is 30°C to 50°C.

5. The wafer-level chip dicing method according to claim 1, wherein After etching the scribing lanes (102) to the set depth and before performing laser stealth dicing on the wafer (101), the wafer-level chip dicing method further includes: Removing the photoresist (103), and covering a protective film on the pattern side of the wafer (101).

6. The wafer-level chip dicing method according to claim 5, wherein The protective film is a back grinding tape; After covering the protective film on the pattern side of the wafer (101), the wafer-level chip dicing method further includes: Performing back grinding on the wafer (101) to thin it to the set chip thickness.

7. The wafer-level chip dicing method according to claim 6, wherein After performing back grinding on the wafer (101) to thin it to the set chip thickness, irradiating ultraviolet light on the back grinding tape.

8. The wafer-level chip dicing method according to claim 6, wherein After irradiating ultraviolet light on the back grinding tape, temporarily not removing the back grinding tape until after performing laser stealth dicing on the wafer (101), and then removing the back grinding tape.

9. The wafer-level chip dicing method according to claim 8, wherein After performing laser stealth dicing on the wafer (101), the wafer-level chip dicing method further includes: Removing the back grinding tape, and then expanding the expandable film (105), and the expandable film (105) driving the separation of the single chips.

10. The wafer-level chip dicing method according to claim 1, characterized in that, In the step of etching the scribing lanes (102) to the set depth, the set depth is 1 / 5 of the final chip thickness; After etching the scribing lanes (102), the wafer-level chip dicing method further includes using the scribing lanes (102) to insert a probe into the scribing lanes for functional testing.

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