Semiconductor storage device and preparation method thereof

Abstract

The invention provides a semiconductor storage device and a preparation method thereof, and is applied to the technical field of semiconductor preparation. According to the invention, in the process of forming the gate structure of the high-voltage device in the logic region, the polycrystalline silicon material of the polycrystalline silicon resistor is synchronously formed in the resistance region, so that the manufacturing method of the polycrystalline silicon resistor and the corresponding structure of the polycrystalline silicon resistor can be simplified on the basis of not additionally increasing the manufacturing process; and feasibility is provided for reducing related masks of the silicide blocking layer, namely, the process cost is reduced and the manufacturing period is shortened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor memory device and a method for manufacturing the same. Background Art

[0002] In the circuit design of semiconductor chips, polysilicon resistors are widely used. Generally, circuit designers mostly use traditional N-type or P-type polysilicon resistors. However, in the manufacturing process of these resistors, a silicide blocking layer (SAB) is required as an additional mask to protect the silicon wafer surface. Under its protection, the silicon wafer does not form unwanted metal silicides with other metals such as Ti and Co, that is, an additional photolithography step is needed. Specifically, the N-type doped polysilicon or P-type doped polysilicon as a polysilicon resistor in the prior art is formed by performing N-type ion implantation (usually high-concentration boron (B) ion implantation) or P-type ion implantation (usually high-concentration phosphorus (P) ion implantation) on logical polysilicon (which is undoped itself), and they both require a silicide blocking layer as a mask. However, the introduction of the silicide blocking layer increases the complexity of the process and the manufacturing cost. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide, in view of the above-mentioned defects in the prior art, a semiconductor memory device and a method for manufacturing the same, which can prevent the formation of metal silicides on the surface of the polysilicon resistor without using a silicide blocking layer, thereby increasing the resistivity of the polysilicon resistor, simplifying the manufacturing method of the polysilicon resistor, and the corresponding polysilicon resistor and semiconductor memory device structure.

[0004] In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor memory device, at least including the following steps:

[0005] Provide a substrate including a storage area, a logic area, and a resistor area;

[0006] Form a first storage polysilicon layer and an isolation layer, the first storage polysilicon layer is located on the substrate of the storage area, the logic area, and the resistor area, and the isolation layer is located on the first storage polysilicon layer;

[0007] Remove a part of the isolation layer and a part of the first storage polysilicon layer on the logic area, and expose a part of the substrate of the logic area;

[0008] Form a second storage polysilicon layer on the exposed part of the substrate of the logic area and the isolation layer of the resistor area;

[0009] A conductive plug is formed on the resistance region, and the bottom of the conductive plug is electrically connected to the top surface of the first storage polysilicon layer in the resistance region.

[0010] In an optional example, before forming the conductive plug, it may further include:

[0011] Removing a part of the second storage polysilicon layer in the logic region to form at least one discrete gate structure on the logic region.

[0012] In an optional example, during the process of removing a part of the second storage polysilicon layer in the logic region, a part of the second storage polysilicon layer in the resistance region is also removed synchronously to expose a part of the first storage polysilicon layer in the resistance region.

[0013] In an optional example, before forming the second storage polysilicon layer, it may further include:

[0014] Forming a logic region gate oxide layer on the exposed part of the substrate in the logic region and the isolation layer in the resistance region.

[0015] In an optional example, before forming the first storage polysilicon layer, it may further include:

[0016] Forming a trench isolation structure in the substrate of the resistance region.

[0017] In an optional example, the first storage polysilicon layer in the resistance region can be used as a polysilicon resistor.

[0018] In an optional example, the logic region may include a high-voltage device region; the part of the substrate exposed when removing a part of the isolation layer and the first storage polysilicon layer on the logic region is aligned with the high-voltage device region.

[0019] In an optional example, after forming the first storage polysilicon layer, it may further include:

[0020] Performing an ion implantation process on the first storage polysilicon layer in the resistance region.

[0021] In an optional example, the first storage polysilicon layer may include a word line layer of a storage unit in an embedded storage device.

[0022] In a second aspect, based on the same inventive concept, the present invention further provides a semiconductor storage device, which can be specifically prepared by using the preparation method of the semiconductor storage device as described above, wherein the substrate includes a resistance region, and the resistance region includes: a first storage polysilicon layer, an isolation layer, a logic region gate oxide layer, and a second storage polysilicon layer.

[0023] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0024] The present invention provides a method for preparing a semiconductor storage device, comprising: providing a substrate, comprising a storage area, a logic area and a resistance area, forming a first storage polysilicon layer and an isolation layer, wherein the first storage polysilicon layer is located on the storage area, the logic area, and the substrate of the resistance area, and the isolation layer is located on the first storage polysilicon layer, removing part of the isolation layer and part of the first storage polysilicon layer on the logic area, and exposing part of the substrate of the logic area, forming a second storage polysilicon layer located on the exposed part of the substrate of the logic area and the isolation layer of the resistance area, forming a conductive plug located on the resistance area, and the bottom of the conductive plug is electrically connected to the top surface of the first storage polysilicon layer in the resistance area.

[0025] In the present invention, on the one hand, by forming the gate structure of the high-voltage device in the logic area and the polysilicon material of the polysilicon resistor in the resistance area simultaneously, the purpose of simplifying the manufacturing method of the polysilicon resistor and the corresponding structure of the polysilicon resistor is achieved without adding any additional process technology; on the other hand, by stacking the first storage polysilicon layer and the second storage polysilicon layer in the resistance area, the second storage polysilicon layer plays the role of shielding the first storage polysilicon layer serving as the polysilicon resistor below from forming metal silicide, thereby playing the same function as the silicide blocking layer; therefore, the present invention advantageously avoids the use of the silicide blocking layer by utilizing the second storage polysilicon layer as a mask for the non-silicide structure, thereby eliminating all process technologies for forming the silicide blocking layer, that is, further simplifying the process technology of the semiconductor storage device, reducing the process cost and shortening the manufacturing cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0027] Figure 1 FIG. 4 is a flow chart of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

[0028] Figures 2 to 5 The figure is a schematic diagram of the structure of a semiconductor storage device during the preparation process provided in one embodiment of the present invention.

[0029] Among them, Figures 2 to 5 middle:

[0030] 100 - Substrate; 101 - Storage area, 102 - Logic area, 103 - Resistance area, 102HN - High - voltage N area, 102HP - High - voltage P area, 102LN - Low - voltage N area, 102LP - Low - voltage P area, 110 - Coupling oxide layer, 120 - Shallow trench isolation structure, 130 - Memory cell, 140 - First memory polysilicon layer, 150 - Isolation layer, 160 - Logic area gate oxide layer, 170 - Second memory polysilicon layer, 180 - Photoresist layer, 190 - Gate structure, 200 - Conductive plug.

[0031] In the drawings, like components are denoted by like reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners

[0032] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided so as to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0033] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and claims. It should be noted that the drawings are all in very simplified forms and use non - precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "over..." in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0034] In addition, for the sake of convenience of description, spatial relative terms such as "on...", "above...", "over...", "upper", "upper part", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and another element or feature. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein can be correspondingly interpreted.

[0035] In the embodiments of the present invention, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0036] Please refer to Figure 1 , which shows a flowchart of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture an embedded flash memory device, and the present invention can also be applied to other types of memories without departing from the spirit of the present invention.

[0037] As Figure 1 shown, the method for manufacturing the semiconductor memory device includes the following steps:

[0038] Step S101: Provide a substrate including a storage area, a logic area, and a resistance area.

[0039] Step S102: Form a first storage polysilicon layer and an isolation layer. The first storage polysilicon layer is located on the substrates of the storage area, the logic area, and the resistance area, and the isolation layer is located on the first storage polysilicon layer.

[0040] Step S103: Remove a part of the isolation layer and a part of the first storage polysilicon layer on the logic area and expose a part of the substrate of the logic area.

[0041] Step S104: Form a second storage polysilicon layer on the exposed part of the substrate of the logic area and the isolation layer of the resistance area.

[0042] Step S105: Form a conductive plug on the resistance area, and the bottom of the conductive plug is electrically connected to the top surface of the first storage polysilicon layer in the resistance area.

[0043] In the method for manufacturing a semiconductor memory device of the present invention, a memory region is used to fabricate MOS transistors of memory cells of a semiconductor memory device such as an embedded flash memory device, a logic region is used to fabricate logic MOS devices of a semiconductor memory device such as an embedded flash memory device, and a resistor region is used to fabricate resistors for the memory region or the logic region, such as a polysilicon resistor, but not limited thereto. Moreover, the logic region can be specifically divided into a high-voltage device region and a low-voltage region, etc., based on the actual operating voltage of the logic MOS device, but not limited thereto. Therefore, the present invention can form the polysilicon material of the polysilicon resistor in the resistor region synchronously during the process of forming the gate structure of the high-voltage device in the logic region, so as to simplify the manufacturing method of the polysilicon resistor and the corresponding structure of the polysilicon resistor without additional manufacturing processes, and provide the feasibility for reducing the mask for the silicide blocking layer, that is, reducing the process cost and shortening the manufacturing cycle.

[0044] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the method for manufacturing a semiconductor memory device in the embodiments of the present invention, the method for manufacturing the semiconductor memory device proposed by the present invention will be further described below in conjunction with various structural schematic diagrams in the manufacturing process of the manufacturing method. Please refer to Figures 2 to 5 As shown, what is illustrated is a structural schematic diagram in the manufacturing process of the method for manufacturing a semiconductor memory device provided in the embodiments of the present invention.

[0045] Execute the above step S101. Please refer to Figure 2 , provide a substrate 100, and the substrate 100 may include a memory region 101, a logic region 102, and a resistor region 103. In one embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (such as a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate, or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates well-known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but not limited thereto. The memory region 101, the logic region 102, and the resistor region 103 may be arranged adjacent to each other, but not limited thereto. The logic region 102 may specifically include a high-voltage device region and a low-voltage device region. The high-voltage device region may further include a high-voltage N region 102HN for forming an NMOS transistor and a high-voltage P region 102HP for forming a PMOS transistor. Similarly, the low-voltage device region may also include a low-voltage N region 102LN for forming an NMOS transistor and a low-voltage P region 102LP for forming a PMOS transistor, but not limited thereto.

[0046] It should be understood that in order to form the high-voltage or low-voltage NMOS transistor or PMOS transistor, after providing the substrate 100, N-type or P-type ion implantation can be performed on different parts of the substrate 100 based on the different partitions of the substrate 100 to form an N-well or P-well corresponding to the type of different types of transistors to be subsequently formed in different partitions, as well as a plurality of shallow trench isolation structures 120 for isolating different partitions, but not limited to this.

[0047] Execute the above step S102, please continue to refer to Figure 2 , a coupling oxide layer 110 is formed on the entire surface of the substrate 100 by using a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, and then a plurality of shallow trench isolation structures 120 are formed by using a photolithography and etching process, and a plurality of storage units 130 are formed on the storage area 101 of the substrate 100. The storage unit 130 may be a dual storage bit storage structure sharing a source line. To simplify the drawing, the drawings in the embodiments of the present invention only exemplarily draw a storage unit 130 on the storage area 101; then, a deposition process such as a chemical vapor deposition process is used to sequentially conformally form a first storage polysilicon layer 140 and an isolation layer 150 on the storage area 101, the logic area 102, and the resistance area 103 of the substrate 100.

[0048] In one embodiment, the material of the coupling oxide layer 110 and the shallow trench isolation structure 120 may be an oxide, such as silicon dioxide, and the storage unit 130 may include a floating gate layer (not marked), an interlayer dielectric layer (not marked), a control gate layer (not marked), a side wall (not marked), a source line (not marked) and other components and / or devices. The material of the first storage polysilicon layer 140 is polysilicon, and it may be a word line polysilicon layer (memoryploy, MPOL) of the storage unit 130, but is not limited to this; the material of the isolation layer 150 may be an oxide such as silicon dioxide, or it may be a nitride such as silicon nitride, but is not limited to this.

[0049] In other embodiments, at least one of the shallow trench isolation structures 120 may also be located within the substrate 100 of the resistance region 103, so that a subsequently formed film layer structure is located on the shallow trench isolation structure 120, but this is not limited to this; after forming the first storage polysilicon layer 140, an ion implantation process may be further used to perform N-type or P-type ion implantation on the first storage polysilicon layer 140 located in the resistance region 103, so as to change the resistance value of the first storage polysilicon layer 140 that serves as a polysilicon resistor, but this is not limited to this.

[0050] It should be understood that "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and relevance in the morphology between two or more shapes.

[0051] Perform the above step S103. Refer to Figure 3 , first form a photoresist layer (not shown) that shields the storage area 101, the resistance area 103, and a part of the logic area 102 of the substrate 100. Among them, the part of the logic area 102 exposed by the photoresist layer can be the high-voltage device area 102H. Then, using this photoresist layer as a mask, through an etching process such as a dry etching process, remove the exposed isolation layer 150 and the first storage polysilicon layer 140 in the high-voltage device area 102H within the logic area 102 that are not shielded by the photoresist layer, so as to expose the coupling oxide layer 110 of the high-voltage device area again.

[0052] Perform the above step S104. Refer to Figure 4 , further use a deposition process such as chemical vapor deposition to conformally form a logic area gate oxide layer 160 and a second storage polysilicon layer 170 that are stacked from bottom to top on the storage area 101, the logic area 102, and the resistance area 103 of the substrate 100. In one embodiment, the material of the logic area gate oxide layer 160 is silicon dioxide, which is used as the gate oxide of the high-voltage device NMOS transistor and PMOS transistor, and the material of the second storage polysilicon layer 170 can be polysilicon, which is used as the gate layer of the high-voltage device NMOS transistor and PMOS transistor.

[0053] Perform the above step S105. Refer to Figure 5 , first form a photoresist layer 180 that shields a part of the second storage polysilicon layer 170 in the logic area 102 and a part of the second storage polysilicon layer 170 in the resistance area 103, and exposes a part of the second storage polysilicon layer 170 in the logic area 102 and a part of the second storage polysilicon layer 170 in the resistance area 103. Then, using this photoresist layer 180 as a mask, etch downward in a direction perpendicular to the surface of the substrate 100 to remove the second storage polysilicon layer 170 and the logic area gate oxide layer 160 that are not shielded by the photoresist layer, so as to form a plurality of gate structures 190 in the high-voltage device area 102H of the logic area 102, such as the gate structures of the high-voltage device NMOS transistor and PMOS transistor. And, during the process of removing a part of the second storage polysilicon layer 170 in the logic area 102, a part of the second storage polysilicon layer 170 in the resistance area 103 is also synchronously removed, so as to expose a part of the first storage polysilicon layer 140 in the resistance area 103.

[0054] Next, a dielectric layer (not shown) may be further formed within the resistance region 103 of the substrate 100, and a plurality of conductive plugs 200 passing through the dielectric layer and electrically connected to the exposed first storage polysilicon layer 140 in the resistance region 103. In one embodiment, the material of the dielectric layer may be an insulating material, such as silicon oxide or silicon nitride, and the material of the conductive plug 200 may be tungsten metal or aluminum metal, but is not limited thereto.

[0055] In addition, based on the same inventive concept, the present invention also provides a semiconductor memory device formed by using the manufacturing method of the semiconductor memory device as described above. Wherein, the semiconductor memory device includes a substrate 100, the substrate 100 includes a resistance region 103, and the resistance region 103 includes: a first storage polysilicon layer 140, an isolation layer 150, a logic region gate oxide layer 160, and a second storage polysilicon layer 170. The specific formation process can refer to the explanation of the manufacturing method as described above, and the present invention will not repeat it here.

[0056] In summary, the present invention provides a manufacturing method of a semiconductor memory device, including: providing a substrate including a storage region, a logic region, and a resistance region; forming a first storage polysilicon layer and an isolation layer, the first storage polysilicon layer being located on the substrate of the storage region, the logic region, and the resistance region, and the isolation layer being located on the first storage polysilicon layer; removing a part of the isolation layer and a part of the first storage polysilicon layer on the logic region to expose a part of the substrate of the logic region; forming a second storage polysilicon layer on the exposed part of the substrate of the logic region and the isolation layer of the resistance region; and forming a conductive plug on the resistance region, the bottom of the conductive plug being electrically connected to the top surface of the first storage polysilicon layer in the resistance region.

[0057] In the present invention, on the one hand, by synchronously forming the polysilicon material of the polysilicon resistor in the resistance region during the process of forming the gate structure of the high-voltage device in the logic region, the purpose of simplifying the manufacturing method of the polysilicon resistor and the corresponding structure of the polysilicon resistor can be achieved without additionally increasing the manufacturing process; on the other hand, by stacking the first storage polysilicon layer and the second storage polysilicon layer in the resistance region, the second storage polysilicon layer functions to shield the underlying first storage polysilicon layer, which is used as a polysilicon resistor, from forming metal silicide, thereby achieving the same function as the silicide blocking layer; therefore, the present invention advantageously uses the second storage polysilicon layer as a mask for the non-silicide structure, avoiding the use of the silicide blocking layer, eliminating all the manufacturing processes for forming the silicide blocking layer, that is, further simplifying the manufacturing process of the semiconductor memory device, reducing the process cost, and shortening the manufacturing cycle.

[0058] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor storage device, characterized in that: include: Providing a substrate, including a storage area, a logic area, and a resistance area; forming a first storage polysilicon layer and an isolation layer, wherein the first storage polysilicon layer is located on the substrate of the storage area, the logic area, and the resistance area, and the isolation layer is located on the first storage polysilicon layer; removing a portion of the isolation layer and a portion of the first storage polysilicon layer on the logic area, and exposing a portion of the substrate in the logic area; forming a second storage polysilicon layer on the exposed portion of the substrate in the logic region and the isolation layer in the resistance region; A conductive plug is formed on the resistance region, and a bottom of the conductive plug is electrically connected to a top surface of the first storage polysilicon layer in the resistance region.

2. The method for preparing a semiconductor memory device according to claim 1, wherein: Before forming the conductive plug, the method further includes: A portion of the second storage polysilicon layer in the logic region is removed to form at least one discrete gate structure on the logic region.

3. The method for preparing a semiconductor memory device according to claim 2, wherein: In the process of removing a portion of the second storage polysilicon layer in the logic area, a portion of the second storage polysilicon layer in the resistance area is also removed synchronously to expose a portion of the first storage polysilicon layer in the resistance area.

4. The method for manufacturing a semiconductor memory device according to claim 1, wherein: Before forming the second storage polysilicon layer, the method further includes: A logic region gate oxide layer is formed on the exposed portion of the substrate in the logic region and the isolation layer in the resistance region.

5. The method for preparing a semiconductor memory device according to claim 1, wherein: Before forming the first storage polysilicon layer, the method further includes: A trench isolation structure is formed in the substrate of the resistor region.

6. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The first storage polysilicon layer located in the resistance region serves as a polysilicon resistor.

7. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The logic area includes a high-voltage device area; the part of the substrate exposed when the part of the isolation layer and the first storage polysilicon layer on the logic area is removed is aligned with the high-voltage device area.

8. The method for manufacturing a semiconductor memory device according to claim 1, wherein: After forming the first storage polysilicon layer, the method further includes: An ion implantation process is performed on the first storage polysilicon layer in the resistance region.

9. The method for manufacturing a semiconductor memory device according to claim 1, wherein: The first storage polysilicon layer comprises a word line layer of a storage unit in an embedded storage device.

10. A semiconductor storage device, characterized in that: The semiconductor storage device is prepared by the method for preparing the semiconductor storage device according to any one of claims 1 to 9, wherein the substrate comprises a resistance region, and the resistance region comprises: a first storage polysilicon layer, an isolation layer, a logic region gate oxide layer, and a second storage polysilicon layer.

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