Image forming apparatus

Abstract

The invention provides an imaging device capable of suppressing a reduction in performance. The imaging device includes: a semiconductor layer; a plurality of pixels disposed on the semiconductor layer; an inter-pixel separation portion disposed on the semiconductor layer and separating one pixel and another pixel adjacent to each other among the plurality of pixels; and a pixel transistor connected to the plurality of pixels, in which the pixel transistor includes a first transistor and a second transistor adjacent to the first transistor via the inter-pixel separation portion, and a gate electrode of the first transistor and a gate electrode of the second transistor are integrated via an upper portion of the inter-pixel separation portion.

Description

Technical Field

[0001] The present disclosure relates to an imaging device. Background Art

[0002] As an imaging device including a photodiode and a transistor that reads the charge photoelectrically converted at the photodiode, a CMOS image sensor is known. There are known structures that use an element isolation section to isolate pixels in a CMOS image sensor (for example, see Patent Document 1 and Patent Document 2).

[0003] [Citation List]

[0004] [Patent Document]

[0005] [Patent Document 1]: Japanese Patent Laid-Open No. 2020-13817

[0006] [Patent Document 2]: US Patent Application Publication No. 2020 / 0219925 Summary of the Invention

[0007] [Technical Problem]

[0008] There is a trend that as pixels are miniaturized, the space for configuring transistors, the space for configuring wirings, the space between adjacent transistors, and the space between adjacent wirings all decrease. If these spaces decrease, there is a possibility that the parasitic capacitance generated between adjacent vias (contacts) and between adjacent wirings increases and the performance of the imaging device deteriorates.

[0009] The present disclosure has been made in view of this situation, and an object thereof is to provide an imaging device that can reduce performance deterioration.

[0010] [Solution to the Problem]

[0011] An imaging device according to one aspect of the present disclosure includes a semiconductor layer; a plurality of pixels provided on the semiconductor layer; a pixel isolation section provided on the semiconductor layer and isolating one pixel and another pixel adjacent to each other among the plurality of pixels; and pixel transistors connected to the plurality of pixels, wherein the pixel transistors include a first transistor and a second transistor adjacent to the first transistor with the pixel isolation section therebetween, and a gate electrode of the first transistor and a gate electrode of the second transistor are integrated via an upper portion of the pixel isolation section.

[0012] According to this configuration, the gate electrodes of the first transistor and the second transistor can share vias (contacts) and the wirings connected thereto, the number of vias and the number of wirings can be reduced, and the lengths of the wirings can be decreased. Therefore, the distances between adjacent vias and between adjacent wirings can be increased, and the parasitic capacitances generated between the vias and between the wirings can be decreased. Accordingly, the degradation of the performance of the imaging device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0014] Figure 2 is a circuit diagram showing a configuration example of a shared pixel unit of an imaging device according to a first embodiment of the present disclosure.

[0015] Figure 3 is a plan view schematically showing a configuration example of a pixel region of an imaging device according to a first embodiment of the present disclosure.

[0016] Figure 4 is a plan view schematically showing a configuration example of a pixel region of an imaging device according to a first embodiment of the present disclosure.

[0017] Figure 5 is a plan view schematically showing a configuration example of a pixel region of an imaging device according to a first embodiment of the present disclosure.

[0018] Figure 6 is a plan view schematically showing a configuration example of a pixel region of an imaging device according to a first embodiment of the present disclosure.

[0019] Figure 7 is a cross-sectional view showing a configuration example of an imaging device according to a first embodiment of the present disclosure.

[0020] Figure 8 is a plan view showing a pixel region according to a comparative example of the present disclosure.

[0021] Figure 9 is a cross-sectional view showing a pixel region according to a comparative example of the present disclosure.

[0022] Figure 10A is a plan view schematically showing the configuration of a pixel region according to Modification 1-1 of a first embodiment of the present disclosure.

[0023] Figure 10B is a plan view schematically showing the configuration of a pixel region according to Modification 1-2 of a first embodiment of the present disclosure.

[0024] Figure 10CIt is a plan view schematically showing the constitution of a pixel region according to Modification Examples 1-3 of the first embodiment of the present disclosure.

[0025] Figure 11A It is a plan view schematically showing the constitution of a pixel region according to Modification Example 2-1 of the first embodiment of the present disclosure.

[0026] Figure 11B It is a plan view schematically showing the constitution of a pixel region according to Modification Example 2-2 of the first embodiment of the present disclosure.

[0027] Figure 11C It is a plan view schematically showing the constitution of a pixel region according to Modification Example 2-3 of the first embodiment of the present disclosure.

[0028] Figure 11D It is a plan view schematically showing the constitution of a pixel region according to Modification Example 2-4 of the first embodiment of the present disclosure.

[0029] Figure 12A It is a plan view schematically showing the constitution of a pixel region according to Modification Example 3-1 of the first embodiment of the present disclosure.

[0030] Figure 12B It is a plan view schematically showing the constitution of a pixel region according to Modification Example 3-2 of the first embodiment of the present disclosure.

[0031] Figure 13A It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-1 of the first embodiment of the present disclosure.

[0032] Figure 13B It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-2 of the first embodiment of the present disclosure.

[0033] Figure 13C It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-3 of the first embodiment of the present disclosure.

[0034] Figure 13D It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-4 of the first embodiment of the present disclosure.

[0035] Figure 13E It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-5 of the first embodiment of the present disclosure.

[0036] Figure 13F It is a plan view schematically showing the constitution of a pixel region according to Modification Example 4-6 of the first embodiment of the present disclosure.

[0037] Figure 14AIt is a plan view schematically showing the configuration of a pixel region according to Modification 5-1 of the first embodiment of the present disclosure.

[0038] Figure 14B It is a plan view schematically showing the configuration of a pixel region according to Modification 5-2 of the first embodiment of the present disclosure.

[0039] Figure 14C It is a plan view schematically showing the configuration of a pixel region according to Modification 5-3 of the first embodiment of the present disclosure.

[0040] Figure 15A It is a plan view schematically showing the configuration of a pixel region according to Modification 6-1 of the first embodiment of the present disclosure.

[0041] Figure 15B It is a plan view schematically showing the configuration of a pixel region according to Modification 6-2 of the first embodiment of the present disclosure.

[0042] Figure 15C It is a plan view schematically showing the configuration of a pixel region according to Modification 6-3 of the first embodiment of the present disclosure.

[0043] Figure 15D It is a plan view schematically showing the configuration of a pixel region according to Modification 6-4 of the first embodiment of the present disclosure.

[0044] Figure 15E It is a plan view schematically showing the configuration of a pixel region according to Modification 6-5 of the first embodiment of the present disclosure.

[0045] Figure 15F It is a plan view schematically showing the configuration of a pixel region according to Modification 6-6 of the first embodiment of the present disclosure.

[0046] Figure 16A It is a plan view schematically showing an example of the configuration of a pixel region according to the second embodiment of the present disclosure.

[0047] Figure 16B It is a plan view schematically showing an example of the configuration of a pixel region according to the second embodiment of the present disclosure.

[0048] Figure 17A It is a plan view schematically showing the configuration of a pixel region according to Modification 7-1 of the second embodiment of the present disclosure.

[0049] Figure 17B It is a plan view schematically showing the configuration of a pixel region according to Modification 7-2 of the second embodiment of the present disclosure.

[0050] Figure 17CIt is a plan view schematically showing the configuration of a pixel region according to Modification 7-3 of the second embodiment of the present disclosure.

[0051] Figure 17D It is a plan view schematically showing the configuration of a pixel region according to Modification 7-4 of the second embodiment of the present disclosure.

[0052] Figure 17E It is a plan view schematically showing the configuration of a pixel region according to Modification 7-5 of the second embodiment of the present disclosure.

[0053] Figure 17F It is a plan view schematically showing the configuration of a pixel region according to Modification 7-6 of the second embodiment of the present disclosure.

[0054] Figure 17G It is a plan view schematically showing the configuration of a pixel region according to Modification 7-7 of the second embodiment of the present disclosure.

[0055] Figure 17H It is a plan view schematically showing the configuration of a pixel region according to Modification 7-8 of the second embodiment of the present disclosure.

[0056] Figure 17I It is a plan view schematically showing the configuration of a pixel region according to Modification 7-9 of the second embodiment of the present disclosure.

[0057] Figure 17J It is a plan view schematically showing the configuration of a pixel region according to Modification 7-10 of the second embodiment of the present disclosure.

[0058] Figure 18 It is a plan view schematically showing a configuration example of a pixel region according to the third embodiment of the present disclosure.

[0059] Figure 19A It is a plan view schematically showing the configuration of a pixel region according to Modification 8-1 of the third embodiment of the present disclosure.

[0060] Figure 19B It is a plan view schematically showing the configuration of a pixel region according to Modification 8-2 of the third embodiment of the present disclosure.

[0061] Figure 19C It is a plan view schematically showing the configuration of a pixel region according to Modification 8-3 of the third embodiment of the present disclosure.

[0062] Figure 19D It is a plan view schematically showing the configuration of a pixel region according to Modification 8-4 of the third embodiment of the present disclosure.

[0063] Figure 19EIt is a plan view schematically showing the configuration of a pixel region according to Modification 8-5 of the third embodiment of the present disclosure.

[0064] Figure 19F It is a plan view schematically showing the configuration of a pixel region according to Modification 8-6 of the third embodiment of the present disclosure.

[0065] Figure 19G It is a plan view schematically showing the configuration of a pixel region according to Modification 8-7 of the third embodiment of the present disclosure.

[0066] Figure 19H It is a plan view schematically showing the configuration of a pixel region according to Modification 8-8 of the third embodiment of the present disclosure.

[0067] Figure 19I It is a plan view schematically showing the configuration of a pixel region according to Modification 8-9 of the third embodiment of the present disclosure.

[0068] Figure 20 It is a plan view schematically showing a configuration example of a pixel region according to the fourth embodiment of the present disclosure.

[0069] Figure 21A It is a plan view schematically showing the configuration of a pixel region according to Modification 9-1 of the fourth embodiment of the present disclosure.

[0070] Figure 21B It is a plan view schematically showing the configuration of a pixel region according to Modification 9-2 of the fourth embodiment of the present disclosure.

[0071] Figure 22 It is a circuit diagram showing Configuration Example 1 of a readout circuit according to the fifth embodiment of the present disclosure.

[0072] Figure 23 It is a circuit diagram showing Configuration Example 2 of a readout circuit according to the fifth embodiment of the present disclosure.

[0073] Figure 24 It is a circuit diagram showing Configuration Example 3 of a readout circuit according to the fifth embodiment of the present disclosure.

[0074] Figure 25 It is a circuit diagram showing Configuration Example 4 of a readout circuit according to the fifth embodiment of the present disclosure.

[0075] Figure 26 It is a circuit diagram showing Configuration Example 5 of a readout circuit according to the fifth embodiment of the present disclosure.

[0076] Figure 27 It is a circuit diagram showing Configuration Example 6 of a readout circuit according to the fifth embodiment of the present disclosure.

[0077] Figure 28 This is a circuit diagram showing Configuration Example 7 of a readout circuit according to the fifth embodiment of the present disclosure.

[0078] Figure 29 This is a circuit diagram showing Configuration Example 8 of a readout circuit according to the fifth embodiment of the present disclosure.

[0079] Figure 30 This is a circuit diagram showing Configuration Example 9 of a readout circuit according to the fifth embodiment of the present disclosure.

[0080] Figure 31 This is a circuit diagram showing Configuration Example 10 of a readout circuit according to the fifth embodiment of the present disclosure.

[0081] Figure 32 This is a circuit diagram showing Configuration Example 11 of a readout circuit according to the fifth embodiment of the present disclosure.

[0082] Figure 33 This is a circuit diagram showing Configuration Example 12 of a readout circuit according to the fifth embodiment of the present disclosure.

[0083] Figure 34 This is a circuit diagram showing Configuration Example 13 of a readout circuit according to the fifth embodiment of the present disclosure.

[0084] Figure 35 This is a circuit diagram showing Configuration Example 14 of a readout circuit according to the fifth embodiment of the present disclosure.

[0085] Figure 36 This is a cross-sectional view of an imaging device showing Configuration Example 1 according to the sixth embodiment of the present disclosure.

[0086] Figure 37 This is a cross-sectional view of an imaging device showing Configuration Example 2 according to the sixth embodiment of the present disclosure.

[0087] Figure 38 This is a plan view schematically showing Pixel Region 12M of Configuration Example 1 according to other embodiments of the present disclosure.

[0088] Figure 39 This is a plan view schematically showing Pixel Region 12N of Configuration Example 2 according to other embodiments of the present disclosure.

[0089] Figure 40 This is a plan view schematically showing Pixel Region 12P of Configuration Example 3 according to other embodiments of the present disclosure. Detailed Description of the Invention

[0090] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the description of the accompanying drawings referred to below, the same or similar parts are given the same or similar reference numerals. However, note that these figures are schematic diagrams, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual ones. Therefore, the specific thicknesses and dimensions should be determined in consideration of the following description. In addition, needless to say, the dimensions in different drawings have different relationships and ratios.

[0091] The definitions of directions such as the up-down direction in the following description are definitions simply used for convenience of explanation and do not limit the technical idea of the present disclosure. For example, needless to say, if the target object is observed after being rotated by 90°, the up-down direction described in the description of the target object is interpreted to mean the left-right direction, and if the target object is observed after being rotated by 180°, the up-down direction described in the description is interpreted to mean the reverse direction.

[0092] In some cases in the following description, the phrases "X-axis direction", "Y-axis direction", and "Z-axis direction" are used to describe directions. For example, the X-axis direction and the Y-axis direction are directions parallel to the front surface 11a of the semiconductor substrate 11. The X-axis direction and the Y-axis direction are also referred to as the horizontal directions. The Z-axis direction is the thickness direction of the semiconductor substrate 11 (i.e., the normal direction of the front surface 11a of the semiconductor substrate 11). The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

[0093] In addition, in the following description, a "planar view" refers to, for example, a view observed in the thickness direction of the semiconductor substrate 11 (i.e., the normal direction of the front surface 11a of the semiconductor substrate 11 and the Z-axis direction).

[0094] In the following description, the case where the first conductivity type is P-type and the second conductivity type is N-type is taken as an example for description. However, even if the conductivity types with the opposite relationship are selected, where the first conductivity type is N-type and the second conductivity type is P-type, there is no problem. In addition, the + attached to P or N means that the semiconductor layer represented by this symbol is a semiconductor layer having a relatively higher impurity concentration compared to the semiconductor layer represented by P or N without the attached +. However, using the same P and P to represent semiconductor layers does not mean that the impurity concentrations of the respective semiconductor layers are the same in a strict sense.

[0095] <First Embodiment>

[0096] (Example of the overall configuration of the imaging device)

[0097] Figure 1 is a block diagram showing an example of the configuration of an imaging device 1 according to the first embodiment of the present disclosure. As Figure 1As shown, the imaging device 1 includes a semiconductor substrate 11 (an example of the "semiconductor layer" of the present disclosure), a pixel region 12 provided on the semiconductor substrate 11, a vertical drive circuit 13, a column signal processing circuit 14, a horizontal drive circuit 15, an output circuit 16, and a control circuit 17. The vertical drive circuit 13, the column signal processing circuit 14, the horizontal drive circuit 15, the output circuit 16, and the control circuit 17 may be provided on the semiconductor substrate 11, or may be provided on a second semiconductor substrate (not shown) disposed on the front side of the (first) semiconductor substrate 11 via a multilayer wiring layer (not shown) including a wiring layer and an interlayer dielectric film.

[0098] The pixel region 12 is a light-receiving region that receives light collected by an optical system (not shown), and has a plurality of pixels 21. The plurality of pixels 21 are arranged in a matrix. The plurality of pixels 21 are connected to the vertical drive circuit 13 in units of rows via horizontal signal lines 22, and are connected to the column signal processing circuit 14 in units of columns via vertical signal lines 23. Each of the plurality of pixels 21 outputs a pixel signal at a level corresponding to the amount of light received by the pixel. An image of the subject is constructed based on these pixel signals.

[0099] The vertical drive circuit 13 supplies drive signals to the pixels 21 via the horizontal signal lines 22 to sequentially drive (transfer, select, reset, etc.) each of the pixels 21 in units of rows of the plurality of pixels 21. The column signal processing circuit 14 performs AD conversion on the pixel signals output from the plurality of pixels 21 via the vertical signal lines 23, and also removes reset noise by performing CDS (correlated double sampling) processing on the pixel signals.

[0100] The horizontal drive circuit 15 supplies a drive signal to the column signal processing circuit 14 to sequentially cause the column signal processing circuit 14 to output pixel signals to the data output signal line 24 in units of columns of the plurality of pixels 21. The output circuit 16 amplifies the pixel signals supplied from the column signal processing circuit 14 via the data output signal line 24 at the timing of the drive signal of the horizontal drive circuit 15, and outputs the pixel signals to a downstream signal processing circuit. The control circuit 17 controls the driving of each block inside the imaging device 1. For example, the control circuit 17 generates a clock signal according to the driving period of each block, and supplies the clock signal to each block.

[0101] Each pixel 21 includes a photodiode PD (an example of the "photoelectric conversion unit" of the present disclosure), a transfer transistor TR, a floating diffusion portion FD, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The transfer transistor TR, the floating diffusion portion FD, the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST form a readout circuit 30 that reads out charges (pixel signals) photoelectrically converted at the photodiode PD.

[0102] The photodiode PD is a photoelectric conversion section that converts incident light into charge through photoelectric conversion and accumulates the charge. The anode terminal of the photodiode PD is connected to ground, and the cathode terminal is connected to the transfer transistor TR. A transfer signal is supplied from the vertical drive circuit 13 to the gate electrode TRG of the transfer transistor TR. The transfer transistor TR is driven according to the transfer signal supplied to the gate electrode TRG. Hereinafter, the gate electrode TRG is also referred to as the transfer gate. When the transfer transistor TR is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion section FD. The floating diffusion section FD is a floating diffusion region connected to the gate electrode of the amplification transistor AMP and having a predetermined accumulation capacitance, and temporarily accumulates the charge transferred from the photodiode PD.

[0103] The amplification transistor AMP outputs a pixel signal corresponding to the charge accumulated in the floating diffusion section FD (i.e., the potential of the floating diffusion section FD) to the vertical signal line 23 via the selection transistor SEL. That is, with the configuration in which the floating diffusion section FD is connected to the gate electrode of the amplification transistor AMP, the floating diffusion section FD and the amplification transistor AMP function as a conversion section that amplifies the charge generated at the photodiode PD and converts the charge into a pixel signal having a level corresponding to the charge.

[0104] The selection transistor SEL is driven according to the selection signal supplied from the vertical drive circuit 13, and when the selection transistor SEL is turned on, the pixel signal output from the amplification transistor AMP can be output to the vertical signal line 23. The reset transistor RST is driven according to the reset signal supplied from the vertical drive circuit 13, and when the reset transistor RST is turned on, the charge accumulated in the floating diffusion section FD is discharged to the wiring 63, and the potential of the floating diffusion section FD is reset. The wiring 63 is connected to the power supply potential VDD.

[0105] Figure 2 is a circuit diagram showing a configuration example of the shared pixel unit 35 of the imaging device 1 according to the first embodiment of the present disclosure. As Figure 2 shown, in the imaging device 1, the photodiodes PD and the transfer transistors TR of a plurality of pixels 21 are connected in parallel to form the shared pixel unit 35. In the shared pixel unit 35, for example, the photodiodes PD of the respective pixels 21 included in the shared pixel unit 35 are connected to one floating diffusion section FD via the transfer transistors TR in the respective pixels 21.

[0106] (Configuration example of pixel)

[0107] (1) Configuration observed in a plan view

[0108] Figures 3 to 6 is a plan view schematically showing a configuration example of the pixel region 12 of the imaging device 1 according to the first embodiment of the present disclosure.Figure 3 An example of the shared pixel unit 35 is shown. Figure 4 An example of a repeating unit of the configuration of pixel transistors connected to one shared pixel unit 35 is shown. Figure 5 is Figure 3 and Figure 4 an enlarged view, and is a plan view showing an example of a first amplification transistor AMP1 and a second amplification transistor AMP2 adjacent to each other with a pixel separation portion 51 therebetween. Figure 6 is a diagram showing an example of wiring 61 and vias 62 connected to the amplification transistor AMP. Note that, to avoid complication of the drawings, Figure 3 and Figure 4 the floating diffusion portion FD (refer to Figure 5 ), the transfer transistor TR including the transfer gate TRG (refer to Figure 2 and Figure 5 ), and the photodiode PD (refer to Figure 7 ) described later are not shown and are omitted in

[0109] As Figure 3 shown, in the imaging device 1, a total of four pixels 21 each arranged in two in the horizontal direction (e.g., X-axis direction) and the vertical direction (e.g., Y-axis direction) in a plan view form one shared pixel unit 35. Depending on the number and configuration of the shared pixels, Figure 3 the shared pixel unit 35 shown in

[0110] is also referred to as a 2×2 type shared pixel unit.

[0111] As Figures 3 to 6 shown, in a plan view, each of the plurality of pixels 21 is individually surrounded by a pixel separation portion 51. One pixel 21 and another adjacent pixel 21 are separated by the pixel separation portion 51. In the 2×2 type shared pixel unit 35, the four floating diffusion portions FD are not integrated but are individually separated by the pixel separation portion 51. In the shared pixel unit 35, the four floating diffusion portions FD are connected to each other via wiring 61 and are connected to the gate electrode of the amplification transistor AMP.

[0112] Note that, in Figure 3 and Figure 4 the reference numeral “AA” denotes active regions such as source and drain regions of the photodiode PD, the floating diffusion portion FD, and the pixel transistor. For example, neither the pixel separation portion 51 nor the second trench isolation 512 (refer to Figure 7 ) is arranged on the front surface 11a of the semiconductor substrate 11 (refer to Figure 7) is equivalent to Figure 3 and Figure 4 the active region AA shown in

[0113] The pixel transistor includes a selection transistor SEL, a reset transistor RST, and an amplification transistor AMP. For example, the 2×2 type shared pixel unit 35 has one selection transistor, one reset transistor RST, and two amplification transistors AMP (a first amplification transistor AMP1 and a second amplification transistor AMP2) as pixel transistors. The first amplification transistor AMP1 is an example of the "first transistor" of the present disclosure. The second amplification transistor AMP2 is an example of the "second transistor" of the present disclosure.

[0114] In addition, in the imaging device 1, one pixel transistor is arranged at a position overlapping with one pixel 21 in a plan view. For example, among the four pixels 21 included in the 2×2 type shared pixel unit 35, the selection transistor SEL is arranged at a position overlapping with the first pixel 21 in a plan view. The reset transistor RST is arranged at a position overlapping with the second pixel 21 in a plan view. The first amplification transistor AMP1 is arranged at a position overlapping with the third pixel 21 in a plan view. The second amplification transistor AMP2 is arranged at a position overlapping with the fourth pixel 21 in a plan view.

[0115] Note that, as can be understood from the comparison between Figure 3 and Figure 4 in the imaging device 1, the first amplification transistor AMP1 (or the second amplification transistor AMP2) included in one shared pixel unit 35 is arranged at a position overlapping with the pixel 21 of another adjacent shared pixel unit 35 in a plan view.

[0116] Specifically, in the imaging device 1, the 2×2 type shared pixel units 35 are arranged in the horizontal direction (e.g., the X-axis direction) and the vertical direction (e.g., the Y-axis direction) in a plan view. The shared pixel unit 35 includes a first shared pixel unit 35-1 and a second shared pixel unit 35-2 adjacent to the first shared pixel unit 35-1 in the horizontal direction (X-axis direction). The second amplification transistor AMP2 included in the first shared pixel unit 35-1 is arranged at a position overlapping with one pixel 21 of the second shared pixel unit 35-2 in a plan view. In addition, the first amplification transistor AMP1 included in the second shared pixel unit 35-2 is arranged at a position overlapping with one pixel 21 of the first shared pixel unit 35-1 in a plan view.

[0117] Note that the multiple shared pixel units 35 have common components. In Figure 3In order to distinguish between adjacent shared pixel units 35, identification numbers (-1, -2, -3) are assigned to the end of the reference numerals of the shared pixel units 35, and they are referred to as the first shared pixel unit 35-1, the second shared pixel unit 35-2, and the third shared pixel unit 35-3. In addition, when distinction is not required, the identification number at the end is omitted, and the shared pixel unit 35 is simply referred to as the shared pixel unit 35.

[0118] Similarly, the first amplification transistor AMP1 and the second amplification transistor AMP2 have common components. In Figures 5 to 7 In order to distinguish between two adjacent amplification transistors AMP (the first amplification transistor AMP1 and the second amplification transistor AMP2), identification numbers (1, 2) are assigned to the ends of the reference numerals of the two amplification transistors AMP. When distinction is not required, the identification number at the end is omitted, and the amplification transistor AMP is simply referred to as the amplification transistor AMP.

[0119] As Figures 3 to 6 shown, in the imaging device 1, in each of the plurality of shared pixel units 35, the gate electrode G1 of the first amplification transistor AMP1 (refer to Figure 7 described later) and the gate electrode G2 of the second amplification transistor AMP2 adjacent to the first amplification transistor AMP1 with the pixel separation portion 51 therebetween (refer to Figure 7 described later) are integrated via the upper portion of the pixel separation portion 51.

[0120] For example, the gate electrode G1 of the first amplification transistor AMP1 included in the first shared pixel unit 35-1 and the gate electrode G2 of the second amplification transistor AMP2 included in the first shared pixel unit 35-1 are integrated via the upper portion of the pixel separation portion 51. Similarly, the gate electrode G1 of the first amplification transistor AMP1 included in the second shared pixel unit 35-2 and the gate electrode G2 of the second amplification transistor AMP2 included in the second shared pixel unit 35-2 are integrated via the upper portion of the pixel separation portion 51.

[0121] In addition, these integrated gate electrodes are arranged at constant intervals in one direction (for example, the Y-axis direction). For example, the integrated gate electrodes of the first amplification transistor AMP1 and the second amplification transistor AMP2 in the first shared pixel unit 35-1 are regarded as the first gate electrode. The integrated gate electrodes of the first amplification transistor AMP1 and the second amplification transistor in the second shared pixel unit 35-2 are regarded as the second gate electrode. In this case, the first gate electrode and the second gate electrode are adjacent to each other with the pixel separation portion 51 therebetween in the Y-axis direction.

[0122] In addition, as Figure 6As shown, the first shared pixel unit 35-1 has a first via 62-1 disposed on the first gate electrode and connected to the first gate electrode. The second shared pixel unit 35-2 has a second via 62-2 disposed on the second gate electrode and connected to the second gate electrode. Assuming that the shortest distance between the first via 62-1 and the second via 62-2 is Lv and the shortest distance between the first gate electrode and the second gate electrode is Le, the direction of the shortest distance Lv intersects the direction of the shortest distance Le.

[0123] For example, the direction of the shortest distance Le is the Y-axis direction. The direction of the shortest distance Lv intersects both the Y-axis direction and the X-axis direction. The direction of the shortest distance Lv is obliquely intersecting with the direction of the shortest distance Le in the plan view. Therefore, compared with the case where the direction of the shortest distance Lv coincides with the direction of the shortest distance Le (i.e., the comparative example described later (refer to Figure 8 and Figure 9 ))), the parasitic capacitance (i.e., unintended capacitive coupling) between the first via 62-1 and the second via 62-2 can be reduced.

[0124] In addition, the number of the first vias 62-1 disposed on the first gate electrode is one. Since the number of the first vias 62-1 and the second vias 62-2 is smaller compared with the comparative example described later (refer to Figure 8 and Figure 9 ), the length of the parallel portions of the wiring 61 connected to the first via 62-1 and the wiring 61 connected to the second via 62-2 can be reduced (i.e., a state where the wirings 61 are as far away from each other as possible can be created), and the parasitic capacitance between these wirings 61 can be reduced.

[0125] Note that in the embodiment of the present disclosure, the number of the first vias 62-1 disposed on the first gate electrode is not limited to one. Although in the form shown in this example, one first via 62-1 is disposed on one first gate electrode, this is merely an example. In the embodiment of the present disclosure, the number of vias disposed at one position does not have to be one.

[0126] Note that the first via 62-1 and the second via 62-2 have common components. Although in Figure 6 these reference numerals "62" are given identification numbers (-1, -2) at the end to distinguish them, when distinction is not required, the identification numbers at the end are omitted, and they are simply referred to as vias 62.

[0127] In each of the first shared pixel unit 35-1 and the second shared pixel unit 35-2, the drains of the first amplification transistor AMP1 and the second amplification transistor AMP2 are connected to each other via a wiring 63. Further, each drain is connected to a power supply potential VDD via the wiring 63. In the imaging device 1, the gate electrodes G1 and G2 are integrated, and the number of vias 62 connected to the gate electrodes G1 and G2 is one. Therefore, compared with the comparative examples described later (refer to Figure 8 and Figure 9 ), the length of the parallel portions of the wirings 61 and 63 can be reduced (that is, a state in which the wirings 61 and 63 are as far away from each other as possible can be created), and the parasitic capacitance between the wirings 61 and 63 can be reduced.

[0128] In the imaging device 1, not only the gate electrodes of the amplification transistors AMP, but also the gate electrodes of the selection transistors SEL included in one shared pixel unit and the gate electrodes of the selection transistors SEL of another shared pixel unit adjacent to the one shared pixel unit 35 are integrated via the upper portion of the inter-pixel separation portion 51. Therefore, in the imaging device 1, the selection transistor SEL included in one shared pixel unit can be regarded as an example of the "first transistor" of the present disclosure, and the selection transistor SEL of another shared pixel unit adjacent to the one shared pixel unit 35 can be regarded as an example of the "second transistor" of the present disclosure. In this case, the parasitic capacitance formed between the vias and the wirings of the selection transistors SEL adjacent to each other with the inter-pixel separation portion 51 therebetween can be reduced.

[0129] Similarly, in the imaging device 1, the gate electrodes of the reset transistors RST included in one shared pixel unit and the gate electrodes of the reset transistors RST of another shared pixel unit adjacent to the one shared pixel unit 35 are also integrated via the upper portion of the inter-pixel separation portion 51. Therefore, in the imaging device 1, the reset transistor RST included in one shared pixel unit can be regarded as an example of the "first transistor" of the present disclosure, and the reset transistor RST of another shared pixel unit adjacent to the one shared pixel unit 35 can be regarded as an example of the "second transistor" of the present disclosure. In this case, the parasitic capacitance formed between the vias and the wirings of the reset transistors RST adjacent to each other with the inter-pixel separation portion 51 therebetween can be reduced.

[0130] (2) Configuration Observed in Cross-Section

[0131] Next, the configuration of each pixel 21 when observed in a cross-sectional view will be described. Figure 7 is a cross-sectional view showing a configuration example of the imaging device 1 according to the first embodiment of the present disclosure. Figure 7 Shows along Figure 6The cross-section taken along line A-A' in the shown plan view.

[0132] As Figure 7 shown, the semiconductor substrate 11 has a front surface 11a and a back surface 11b on the opposite side of the front surface 11a. Pixel transistors such as amplification transistors AMP are arranged on the front surface 11a side of the semiconductor substrate 11. In addition, a multilayer wiring layer including a plurality of wirings and a plurality of interlayer dielectric films alternately laminated is provided on the front surface side of the semiconductor substrate 11. Figure 7 The wiring 61 as a part of the plurality of wirings included in the multilayer wiring layer and the interlayer dielectric film 55 as a part of the plurality of interlayer dielectric films are shown.

[0133] As Figure 7 shown, for example, the pixel isolation portion 51 around the outer periphery of each pixel 21 has a first trench isolation 511 provided to extend from the back surface 11b side of the semiconductor substrate 11 to the front surface 11a side of the semiconductor substrate 11 and a second trench isolation 512 provided on the front surface 11a side of the semiconductor substrate 11. The second trench isolation 512 is disposed on the first trench isolation 511 to form the pixel isolation portion 51. In addition, the second trench isolation 512 is partially provided within each pixel 21 and separates the elements within the pixel 21 (for example, separates the pixel transistor from the floating diffusion portion, etc.).

[0134] For example, the pixel transistor is an N-type MOS transistor provided in the P-type well region 52. The type of the channel portion 53 of the N-type MOS transistor is N-type (for example, N+ type) different from the type of the photodiode PD. For example, the potential of the P-type well region 52 is fixed at a reference potential (for example, ground potential (0V)) via a P-type contact region (not shown) provided on the front surface 11a side of the semiconductor substrate 11.

[0135] For example, the back surface 11b side of the semiconductor substrate 11 is a light incident surface, and an on-chip lens, a color filter, etc. (all not shown) are provided. For example, the imaging device 1 is a back-illuminated type CMOS image sensor that performs photoelectric conversion on light incident from the back surface 11b side of the semiconductor substrate 11.

[0136] (Comparative example)

[0137] Next, the comparative example will be described. Figure 8 is a plan view showing a pixel region 12' according to a comparative example of the present disclosure. Figure 9 is a cross-sectional view showing a pixel region 12' according to a comparative example of the present disclosure. Figure 7 Shows along Figure 6 the cross-section taken along line a-a' in the shown plan view.

[0138] As Figure 8 andFigure 9 As shown, in the comparative example, the gate electrode G1' of the first amplification transistor AMP1' included in the first shared pixel unit 35'-1 and the gate transistor G2' of the second amplification transistor AMP2' included in the first shared pixel unit 35'-1 are not integrated. Through holes 62' are provided on the gate electrode G1' of the first amplification transistor AMP1' and the gate electrode G2' of the second amplification transistor AMP2', respectively. In addition, a wiring 61' is provided to connect the through holes 62' to each other. The second shared pixel unit 35'-2 adjacent to the first shared pixel unit 35'-1 also has a configuration similar to that of the first shared pixel unit 35'-1.

[0139] In the comparative example, the direction of the shortest distance Lv' between the through hole 62' included in the first shared pixel unit 35'-1 and the through hole 62' included in the second shared pixel unit 35'-2 is the same as the direction of the shortest distance Le' between the gate electrode G1' of the first amplification transistor AMP1' included in the first shared pixel unit 35'-1 and the gate voltage G2' of the second amplification transistor AMP2' included in the second shared pixel unit 35'-2. Therefore, it is easier to generate parasitic capacitance between the through hole 62' of the first shared pixel unit 35'-1 and the through hole 62' of the second shared pixel unit 35'-2.

[0140] As Figure 8 shown, since the length of the parallel portion of the wiring 61' is short, it is also easier to generate parasitic capacitance between the wirings 61' of the first shared pixel unit 35'-1 and the second shared pixel unit 35'-2.

[0141] In each of the first shared pixel unit 35'-1 and the second shared pixel unit 35'-2, the drains of the first amplification transistor AMP1' and the second amplification transistor AMP2' are connected to the power supply potential VDD via a wiring 63'. In the comparative example, the wiring 61' is connected to each of the gate electrodes G1' and G2' via the through hole 62', and the length of the parallel portion of the wirings 61' and 63' is long. Therefore, it is also easier to generate parasitic capacitance between the wiring 61' and the wiring 63'.

[0142] (Effect of the First Embodiment)

[0143] As described above, the imaging device 1 according to the first embodiment of the present disclosure includes a semiconductor substrate 11, a plurality of pixels 21 provided on the semiconductor substrate 11, an inter-pixel separation portion 51 provided on the semiconductor substrate 11 and separating one pixel 21 and another pixel 21 adjacent to each other among the plurality of pixels 21, and pixel transistors connected to the plurality of pixels 21. The pixel transistors include a first amplification transistor AMP1 and a second amplification transistor AMP2 adjacent to the first amplification transistor AMP1 with the inter-pixel separation portion 51 therebetween. The gate electrode G1 of the first amplification transistor AMP1 and the gate electrode G2 of the second amplification transistor AMP2 are integrated via the upper portion of the inter-pixel separation portion 51.

[0144] According to this configuration, the gate electrode G1 of the first amplification transistor AMP1 and the gate electrode G2 of the second amplification transistor AMP2 can share vias (contacts) and the wirings connected thereto, the number of vias and the number of wirings can be reduced, and the length of the wirings can be decreased. Therefore, the distance between adjacent vias 62 and the distance between adjacent wirings 61 can be increased, and the parasitic capacitance generated between the via 62 and the wiring 61 can be decreased (for example, refer to Figure 6 ).

[0145] For example, the capacitive signal coupling (VDD-FD coupling) generated between the wiring 63 having the power supply potential VDD and the wiring 61 having the potential of the floating diffusion portion FD and the capacitive signal coupling (FD-FD coupling) generated between adjacent wirings 61 can be decreased. As a result, the deterioration of the performance of the imaging device 1 can be decreased.

[0146] (Modification of the First Embodiment)

[0147] (1) Modification 1

[0148] For example, as shown in Figure 3 and Figure 4 , in the form shown in the above first embodiment, the gate electrodes of the selection transistors SEL in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are integrated via the upper portion of the inter-pixel separation portion 51. Similarly, in the form shown, the gate electrodes of the reset transistors RST in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are integrated via the upper portion of the inter-pixel separation portion 51.

[0149] However, the embodiments of the present disclosure are not limited thereto. For example, the configurations in Modifications 1-1 to 1-3 shown below can be adopted. The configuration of each shared pixel unit 35 in Modifications 1-1 to 1-3 shown below is a 2×2 type configuration in which two pixels are arranged in the X-axis direction and two pixels are arranged in the Y-axis direction. Each shared pixel unit 35 has two amplification transistors AMP, one selection transistor SEL, and one reset transistor RST as pixel transistors. Similarly, with such a configuration, as in the first embodiment described above, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0150] (1-1) Modification 1-1

[0151] Figure 10A is a plan view schematically showing the configuration of the pixel region 12A-1 according to Modification 1-1 of the first embodiment of the present disclosure. As Figure 10A shown, in the pixel region 12A-1 according to Modification 1-1, the gate electrodes of each pair of amplification transistors AMP adjacent to each other in the X-axis direction are integrated.

[0152] In addition, the gate electrodes of the selection transistors SEL in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are not integrated, and the gate electrodes of the reset transistors RST in one shared pixel unit 35 and another shared pixel unit 35 are also not integrated.

[0153] In the pixel region 12A-1, the reset transistor RST in one shared pixel unit 35 and the selection transistor SEL in another shared pixel unit 35 adjacent to this shared pixel unit 35 in the X-axis direction are arranged adjacent to each other with the pixel separation portion 51 therebetween. Note that in the pixel region 12A-1, the outer shape (two-dot chain line) of each shared pixel unit 35 in the plan view and the outer shape (dotted line) of the repeating unit of the arrangement of the pixel transistors in the plan view do not coincide.

[0154] (1-2) Modification 1-2

[0155] Figure 10B is a plan view schematically showing the configuration of the pixel region 12A-2 according to Modification 1-2 of the first embodiment of the present disclosure. As Figure 10B shown, in the pixel region 12A-2 according to Modification 1-2, the gate electrodes of each pair of amplification transistors AMP adjacent to each other in the X-axis direction are integrated.

[0156] As Figure 10BAs shown, similarly in the pixel region 12A-2, the gate electrodes of a selection transistor SEL in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are not integrated, and the gate electrodes of a reset transistor RST in one shared pixel unit 35 and another shared pixel unit 35 are also not integrated. In the pixel region 12A-2, in each shared pixel unit 35, the selection transistor SEL and the reset transistor RST are arranged adjacent to each other with a pixel separation portion 51 therebetween. Note that in the pixel region 12A-2, the outer shape (two-dot chain line) of each shared pixel unit 35 in the plan view coincides with the outer shape (dotted line) of the repeating unit of the pixel transistor configuration in the plan view.

[0157] (1-3) Modification Examples 1-3

[0158] Figure 10C is a plan view schematically showing the configuration of a pixel region 12A-3 according to Modification Examples 1-3 of the first embodiment of the present disclosure. As Figure 10C shown, in the pixel region 12A-3 according to Modification Examples 1-3, the gate electrodes of each pair of amplifier transistors AMP adjacent to each other in the X-axis direction are integrated.

[0159] As Figure 10C shown, similarly in the pixel region 12A-3, the gate electrodes of a selection transistor SEL in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are not integrated, and the gate electrodes of a reset transistor RST in one shared pixel unit 35 and another shared pixel unit 35 are also not integrated. In the pixel region 12A-3, the reset transistor RST in one shared pixel unit 35 and the selection transistor SEL in another shared pixel unit 35 adjacent to the shared pixel unit 35 in the X-axis direction are arranged adjacent to each other with a pixel separation portion 51 therebetween.

[0160] In addition, the amplifier transistors AMP and other pixel transistors (selection transistor SEL, reset transistor RST) are alternately arranged in the Y-axis direction (column direction).

[0161] (2) Modification Example 2

[0162] For example, as Figure 3 and Figure 4As shown, in the form shown in the above first embodiment, the amplifying transistors AMP are arranged and configured in the Y-axis direction (column direction). Further, in the form shown, the selection transistors SEL and the reset transistors RST are alternately arranged and configured in the Y-axis direction (column direction). However, the embodiments of the present disclosure are not limited thereto. For example, the configurations in Modification Examples 2-1 to 2-4 shown below can be adopted. Similarly, with such a configuration, as in the above first embodiment, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the deterioration of the performance of the imaging device 1 can be reduced.

[0163] Note that the configuration of each of the shared pixel units 35 in Modification Examples 2-1 to 2-4 is a 2×2 type configuration. Each shared pixel unit 35 has two amplifying transistors AMP, one selection transistor SEL, and one reset transistor RST as pixel transistors.

[0164] (2-1) Modification Example 2-1

[0165] Figure 11A is a plan view schematically showing the configuration of the pixel region 12B-1 according to Modification Example 2-1 of the first embodiment of the present disclosure. As Figure 11A shown, in the pixel region 12B-1 according to Modification Example 2-1, the gate electrodes of each pair of pixel transistors (each pair of amplifying transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X-axis direction are integrated.

[0166] As Figure 11A shown, in the pixel region 12B-1, there are columns in which the amplifying transistors AMP are arranged in the Y-axis direction, columns in which the selection transistors SEL are arranged in the Y-axis direction, and columns in which the reset transistors RST are arranged in the Y-axis direction. The columns in which the selection transistors SEL are arranged in the Y-axis direction and the columns in which the reset transistors RST are arranged in the Y-axis direction are configured to be shifted by one row with respect to the columns in which the amplifying transistors AMP are arranged in the Y-axis direction.

[0167] (2-2) Modification Example 2-2

[0168] Figure 11B is a plan view schematically showing the configuration of the pixel region 12B-2 according to Modification Example 2-2 of the first embodiment of the present disclosure. As Figure 11B shown, in the pixel region 12B-2 according to Modification Example 2-2, the gate electrodes of each pair of amplifying transistors AMP adjacent to each other in the X-axis direction are integrated.

[0169] As Figure 11BAs shown, in pixel region 12B-2, except for the gate electrode of the amplifying transistor AMP, the gate electrodes of one pixel transistor (e.g., the selection transistor SEL) and another pixel transistor (e.g., the reset transistor RST) adjacent to each other in the X-axis direction are arranged adjacent to each other but not integrated.

[0170] (2-3) Modification Example 2-3

[0171] Figure 11C is a plan view schematically showing the configuration of pixel region 12B-3 according to Modification Example 2-3 of the first embodiment of the present disclosure. As Figure 11C shown, in pixel region 12B-3 according to Modification Example 2-3, the gate electrodes of each pair of pixel transistors (each pair of amplifying transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X-axis direction are integrated.

[0172] As Figure 11C shown, in pixel region 12B-3, there are columns in which the amplifying transistors AMP and the selection transistors SEL are alternately arranged in the Y-axis direction and columns in which the amplifying transistors AMP and the reset transistors RST are alternately arranged in the Y-axis direction. Therefore, the outer shape of the repeating unit of the pixel transistor configuration is a shape different from the shape of the repeating unit in pixel regions 12B-1 and 12B-2.

[0173] (2-4) Modification Example 2-4

[0174] Figure 11D is a plan view schematically showing the configuration of pixel region 12B-4 according to Modification Example 2-4 of the first embodiment of the present disclosure. As Figure 11D shown, in pixel region 12B-4 according to Modification Example 2-4, the gate electrodes of each pair of pixel transistors (each pair of amplifying transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X-axis direction are integrated.

[0175] As Figure 11D shown, in pixel region 12B-4, the amplifying transistors AMP, the selection transistors SEL, the amplifying transistors AMP, and the reset transistors RST are arranged in sequence in the Y-axis direction. Therefore, the outer shape of the repeating unit of the pixel transistor configuration is a shape different from Figure 11A and Figure 11B the shape of the repeating unit in pixel regions 12B-1 and 12B-2 shown.

[0176] (3) Modification Example 3

[0177] In an embodiment of the present disclosure, the pixel transistor may have a switching transistor FDG for switching the charge conversion efficiency of the amplification transistor AMP. For example, the configurations in Modification Examples 3-1 and 3-2 shown below may be adopted. The configuration of each shared pixel unit 35 in Modification Examples 3-1 and 3-2 is a 2×2 type configuration. Each shared pixel unit 35 has one amplification transistor AMP, one selection transistor SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors.

[0178] Similarly, with such a configuration, as in the first embodiment described above, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0179] (3-1) Modification Example 3-1

[0180] Figure 12A is a plan view schematically showing the configuration of the pixel region 12C-1 according to Modification Example 3-1 of the first embodiment of the present disclosure. As Figure 12A shown, in the pixel region 12C-1 according to Modification Example 3-1, the gate electrodes of each pair of selection transistors SEL adjacent to each other in the X-axis direction, the gate electrodes of each pair of reset transistors RST adjacent to each other in the X-axis direction, and the gate electrodes of each pair of switching transistors FDG adjacent to each other in the X-axis direction are integrated.

[0181] In addition, in the pixel region 12C-1, the gate electrodes of the switching transistors FDG in one shared pixel unit 35 and another shared pixel unit 35 adjacent to each other in the X-axis direction are integrated via the upper part of the inter-pixel separation portion 51.

[0182] On the other hand, the gate electrodes of the amplification transistors AMP in one shared pixel unit 35 and another shared image unit 35 adjacent to each other in the X-axis direction are not integrated.

[0183] As Figure 12A shown, in the pixel region 12C-1, there are provided columns in which the amplification transistors AMP and the selection transistors SEL are alternately arranged in the Y-axis direction and columns in which the reset transistors RST and the switching transistors FDG are alternately arranged in the Y-axis direction.

[0184] (3-2) Modification Example 3-2

[0185] Figure 12B is a plan view schematically showing the configuration of the pixel region 12C-2 according to Modification Example 3-2 of the first embodiment of the present disclosure. As Figure 12BAs shown, in pixel region 12C-2 according to Modification 3-2, the gate electrodes of each pair of selection transistors SEL adjacent to each other in the X-axis direction, the gate electrodes of each pair of reset transistors RST adjacent to each other in the X-axis direction, and the gate electrodes of each pair of switching transistors FDG adjacent to each other in the X-axis direction are integrated. The gate electrodes of each pair of amplification transistors AMP adjacent to each other in the X-axis direction are not integrated.

[0186] As Figure 12B shown, in pixel region 12C-2, amplification transistors AMP, selection transistors SEL, reset transistors RST, and switching transistors FDG are arranged in order in the Y-axis direction. Therefore, the outer shape of the repeating unit of the configuration of the pixel transistors is a shape different from that of the repeating unit in pixel region 12C-1 Figure 12A shown.

[0187] (4) Modification 4

[0188] In the embodiments of the present disclosure, the configuration of each shared pixel unit 35 is not limited to a 2×2 type configuration. For example, each shared pixel unit 35 may share a total of eight pixel transistors, including amplification transistors AMP, selection transistors SEL, and reset transistors RST.

[0189] For example, in Modifications 4-1 to 4-6 shown below, each shared pixel unit 35 has a total of eight pixel transistors, that is, four amplification transistors AMP, two selection transistors SEL, and two reset transistors RST. The configuration of each shared pixel unit 35 is a 4×2 type configuration, in which these eight pixel transistors are arranged four in the horizontal direction (e.g., X-axis direction) and two in the vertical direction (e.g., Y-axis direction) in the plan view. Similarly, with such a configuration, as in the first embodiment described above, the parasitic capacitance generated between vias 62 and between wirings 61 (e.g., refer to Figure 6 ) can be reduced, and the degradation of the performance of imaging device 1 can be reduced.

[0190] Note that although in the examples shown in the following Modifications 4-1 to 4-6, all a total of eight pixel transistors included in each shared pixel unit 35 are incorporated into the circuit, some of the total eight pixel transistors may not be incorporated into the circuit and may be dummy transistors.

[0191] (4-1) Modification 4-1

[0192] Figure 13A is a plan view schematically showing the configuration of pixel region 12D-1 according to Modification 4-1 of the first embodiment of the present disclosure. As Figure 13AAs shown, in the pixel region 12D-1 according to Modification Example 4-1, the gate electrodes of each pair of pixel transistors (each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X-axis direction are integrated.

[0193] (4-2) Modification Example 4-2

[0194] Figure 13B is a plan view schematically showing the configuration of the pixel region 12D-2 according to Modification Example 4-2 of the first embodiment of the present disclosure. As Figure 13B shown, in the pixel region 12D-2 according to Modification Example 4-2, the outer shape of the repeating unit of the arrangement of the pixel transistors is a shape different from the shape of the pixel region 12D-1 Figure 13A shown.

[0195] (4-3) Modification Example 4-3

[0196] Figure 13C is a plan view schematically showing the configuration of the pixel region 12D-3 according to Modification Example 4-3 of the first embodiment of the present disclosure. As Figure 13C shown, in the pixel region 12D-3 according to Modification Example 4-3, the outer shape of the repeating unit of the arrangement of the pixel transistors is a shape different from the shape of the pixel region 12D-1 Figure 13A shown.

[0197] (4-4) Modification Example 4-4

[0198] Figure 13D is a plan view schematically showing the configuration of the pixel region 12D-4 according to Modification Example 4-4 of the first embodiment of the present disclosure. As Figure 13D shown, in the pixel region 12D-4 according to Modification Example 4-4, the outer shape of the repeating unit of the arrangement of the pixel transistors is a shape different from the shape of the pixel region 12D-1 Figure 13A shown.

[0199] (4-5) Modification Example 4-5

[0200] Figure 13E is a plan view schematically showing the configuration of the pixel region 12D-5 according to Modification Example 4-5 of the first embodiment of the present disclosure. As Figure 13E shown, in the pixel region 12D-5 according to Modification Example 4-5, there are provided columns in which the amplification transistors AMP and the selection transistors SEL are alternately arranged in the Y-axis direction and columns in which the amplification transistors AMP and the reset transistors RST are alternately arranged in the Y-axis direction. Note that in the arrangement (rows) in the X-axis direction, there are provided columns in which only the amplification transistors AMP are arranged and columns in which the selection transistors SEL and the reset transistors RST are alternately arranged.

[0201] (4 - 6) Variants 4 - 6

[0202] Figure 13F is a plan view schematically showing the configuration of the pixel region 12D - 6 according to Variant 4 - 6 of the first embodiment of the present disclosure. As Figure 13F shown, in the pixel region 12D - 6 according to Variant 4 - 6, columns in which the amplifying transistors AMP and the selection transistors SEL are alternately arranged in the Y - axis direction and columns in which the amplifying transistors AMP and the reset transistors RST are alternately arranged in the Y - axis direction are provided. Focusing on the configuration (rows) in the X - axis direction, columns in which the amplifying transistors AMP and the selection transistors SEL are alternately arranged and columns in which the amplifying transistors AMP and the reset transistors RST are alternately arranged are provided.

[0203] (5) Variant 5

[0204] In addition, when the configuration of each shared pixel unit 35 is a 4×2 - type configuration, the pixel transistors in the (n + 1) - th column (n is an integer equal to or greater than 1) arranged in the Y - axis direction can be configured to be shifted by one row relative to the pixel transistors in the n - th column arranged in the Y - axis direction. For example, the configurations in Variants 5 - 1 to 5 - 3 shown below can be adopted. The configuration of each shared pixel unit 35 in Variants 5 - 1 to 5 - 3 is a 4×2 - type configuration. Each shared pixel unit 35 has four amplifying transistors AMP, two selection transistors SEL, and two reset transistors RST as pixel transistors. Similarly, with such a configuration, as in the above - mentioned first embodiment, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0205] (5 - 1) Variant 5 - 1

[0206] Figure 14A is a plan view schematically showing the configuration of the pixel region 12E - 1 according to Variant 5 - 1 of the first embodiment of the present disclosure. As Figure 14A shown, in the pixel region 12E - 1 according to Variant 5 - 1, the gate electrodes of each pair of pixel transistors (each pair of amplifying transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X - axis direction are integrated.

[0207] As Figure 14AAs shown, in pixel region 12E-1, columns A and B in which amplification transistors AMP are arranged in the Y-axis direction, columns in which selection transistors SEL are arranged in the Y-axis direction, and columns in which reset transistors RST are arranged in the Y-axis direction are provided. The columns in which selection transistors SEL are arranged in the Y-axis direction and the columns in which reset transistors RST are arranged in the Y-axis direction are configured to be shifted by one row relative to columns A and B in which amplification transistors AMP are arranged in the Y-axis direction.

[0208] In addition, column A in which amplification transistors AMP are arranged in the Y-axis direction, columns in which selection transistors SEL are arranged in the Y-axis direction, column B in which amplification transistors AMP are arranged in the Y-axis direction, and columns in which reset transistors RST are arranged in the Y-axis direction are arranged and configured repeatedly in sequence.

[0209] (5-2) Variant 5-2

[0210] Figure 14B is a plan view schematically showing the configuration of pixel region 12E-2 according to Variant 5-2 of the first embodiment of the present disclosure. As Figure 14B shown, in pixel region 12E-2 according to Variant 5-2, column B in which amplification transistors AMP are arranged in the Y-axis direction and columns in which reset transistors RST are arranged in the Y-axis direction are configured to be shifted by one row relative to column A in which amplification transistors AMP are arranged in the Y-axis direction and columns in which selection transistors SEL are arranged in the Y-axis direction.

[0211] In addition, column A in which amplification transistors AMP are arranged in the Y-axis direction, column B in which amplification transistors AMP are arranged in the Y-axis direction, columns in which selection transistors SEL are arranged in the Y-axis direction, and columns in which reset transistors RST are arranged in the Y-axis direction are arranged and configured repeatedly in sequence in the X-axis direction.

[0212] (5-3) Variant 5-3

[0213] Figure 14C is a plan view schematically showing the configuration of pixel region 12E-3 according to Variant 5-3 of the first embodiment of the present disclosure. As Figure 14C shown, in pixel region 12E-3 according to Variant 5-3, column B in which amplification transistors AMP are arranged in the Y-axis direction and columns in which reset transistors RST are arranged in the Y-axis direction are configured to be shifted by one row relative to column A in which amplification transistors AMP are arranged in the Y-axis direction and columns in which selection transistors SEL are arranged in the Y-axis direction.

[0214] In addition, the columns A in which the amplification transistors AMP are arranged in the Y-axis direction, the columns in which the reset transistors RST are arranged in the Y-axis direction, the columns in which the selection transistors SEL are arranged in the Y-axis direction, and the columns B in which the amplification transistors AMP are arranged in the Y-axis direction are repeatedly arranged and configured in the X-axis direction in sequence.

[0215] (6) Variant 6

[0216] In addition, when the configuration of each shared pixel unit 35 is a 4×2 type configuration, the pixel transistor may have a switching transistor FDG for switching the charge conversion efficiency of the amplification transistor AMP. For example, the configurations in Variants 6-1 to 6-6 shown below can be adopted.

[0217] The configuration of each shared pixel unit 35 in Variants 6-1 to 6-6 is a 4×2 type configuration. In Variants 6-1 and 6-2, each shared pixel unit 35 has two amplification transistors AMP, two selection transistors SEL, two reset transistors RST, and two switching transistors FDG as pixel transistors. In Variants 6-3 to 6-6, each shared pixel unit 35 has four amplification transistors AMP, two selection transistors SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. Similarly, with such a configuration, as in the above-described first embodiment, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0218] (6-1) Variant 6-1

[0219] Figure 15A is a plan view schematically showing the configuration of the pixel region 12F-1 according to Variant 6-1 of the first embodiment of the present disclosure. As Figure 15A shown, in the pixel region 12F-1 according to Variant 6-1, the gate electrodes of each pair of pixel transistors (each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST, each pair of switching transistors FDG) adjacent to each other in the X-axis direction are integrated.

[0220] (6-2) Variant 6-2

[0221] Figure 15B is a plan view schematically showing the configuration of the pixel region 12F-2 according to Variant 6-2 of the first embodiment of the present disclosure. As Figure 15B shown, in the pixel region 12F-2 according to Variant 6-2, the outer shape of the repeating unit of the pixel transistor configuration is a shape different from the shape of the pixel region 12F-1 shown in Figure 15A .

[0222] (6-3) Variant Example 6-3

[0223] Figure 15C is a plan view schematically showing the configuration of the pixel region 12F-3 according to Variant Example 6-3 of the first embodiment of the present disclosure. As Figure 15C shown, in the pixel region 12F-3 according to Variant Example 6-3, the gate electrodes of each pair of pixel transistors (each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST, each pair of switching transistors FDG) adjacent to each other in the X-axis direction are integrated.

[0224] In addition, in the pixel region 12F-3, one repeating unit and another repeating unit adjacent to each other in the X-axis direction have a layout that is left-right symmetric with respect to the Y-axis.

[0225] (6-4) Variant Example 6-4

[0226] Figure 15D is a plan view schematically showing the configuration of the pixel region 12F-4 according to Variant Example 6-4 of the first embodiment of the present disclosure. As Figure 15D shown, in the pixel region 12F-4 according to Variant Example 6-4, the outer shape of the repeating unit of the configuration of the pixel transistors is a shape different from that of the pixel region 12F-3 Figure 15C shown. For example, in the pixel region 12F-3, one repeating unit and another repeating unit adjacent to each other in the X-axis direction have a layout in which the reset transistor RST and the switching transistor FDG are replaced with each other.

[0227] (6-5) Variant Example 6-5

[0228] Figure 15E is a plan view schematically showing the configuration of the pixel region 12F-5 according to Variant Example 6-5 of the first embodiment of the present disclosure. As Figure 15E shown, in the pixel region 12F-5 according to Variant Example 6-5, the reset transistor RST and the switching transistor FDG are adjacent to each other in the X-axis direction with the pixel inter-separation portion 51 therebetween. The gate electrodes of the reset transistor RST and the switching transistor FDG adjacent to each other in the X-axis direction are not integrated. The gate electrodes of each pair of amplification transistors AMP adjacent to each other in the X-axis direction are integrated, and the gate electrodes of each pair of selection transistors adjacent to each other in the X-axis direction are integrated.

[0229] (6-6) Variant Example 6-6

[0230] Figure 15F is a plan view schematically showing the configuration of the pixel region 12F-6 according to Variant Example 6-6 of the first embodiment of the present disclosure. As Figure 15FAs shown, in the pixel region 12F-6 according to Modification Example 6-6, the outer shape of the repeating unit of the pixel transistor configuration is different from that of Figure 15E the shape of the pixel region 12F-6 shown.

[0231] <Second Embodiment>

[0232] In the cases described in the above First Embodiment and its modification examples, the configuration of each shared pixel unit 35 is a 2×2 type configuration or a 4×2 type structure. However, in the embodiments of the present disclosure, the configuration of each shared pixel unit 35 is not limited to this.

[0233] (Configuration Example)

[0234] Figure 16A and Figure 16B are plan views schematically showing a configuration example of a pixel region 12G according to a second embodiment of the present disclosure. Figure 16A An example of the shared pixel unit 35 is shown. Figure 16B An example of the repeating unit of the pixel transistor configuration connected to one shared pixel unit 35 is shown.

[0235] As Figure 16A shown, in the pixel region 12G according to the second embodiment, each shared pixel unit 35 has a total of eight pixel transistors, that is, four amplification transistors AMP, two selection transistors SEL, and two reset transistors RST. The configuration of each shared pixel unit 35 can be a 2×4 type configuration, in which these eight pixel transistors are arranged two in the horizontal direction (e.g., X-axis direction) and four in the vertical direction (e.g., Y-axis direction) in a plan view.

[0236] As Figure 16A and Figure 16B shown, in the pixel region 12G, there are columns in which the reset transistor RST, the selection transistor SEL, the selection transistor SEL, and the reset transistor RST are repeatedly arranged in order in the Y-axis direction, and columns in which the amplification transistors AMP are arranged in the Y-axis direction.

[0237] Furthermore, in the pixel region 12G, the gate electrodes of each pair of pixel transistors (each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST) adjacent to each other in the X-axis direction are integrated.

[0238] (Effects of the Second Embodiment)

[0239] Similarly, with such a configuration, as in the above First Embodiment, it is possible to reduce between the vias 62 and between the wirings 61 (e.g., refer to Figure 6The parasitic capacitance generated and the degradation of the performance of the imaging device 1 can be reduced.

[0240] Note that also in the pixel region 12G, some of the total eight pixel transistors included in each shared pixel unit 35 may not be incorporated into the circuit and may be dummy transistors.

[0241] (Modification of the second embodiment)

[0242] (7) Modification 7

[0243] In the second embodiment, the configurations in Modifications 7-1 to 7-10 shown below can be adopted. The configuration of each shared pixel unit 35 in Modifications 7-1 to 7-10 is a 2×4 type configuration. Each shared pixel unit 35 has four amplification transistors AMP, two selection transistors SEL, and two reset transistors RST as pixel transistors. Similarly, with such a configuration, as in the above-described first and second embodiments, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0244] Note that also in Modifications 7-1 to 7-10 shown below, some of the total eight pixel transistors included in each shared pixel unit 35 may not be incorporated into the circuit and may be dummy transistors.

[0245] (7-1) Modification 7-1

[0246] Figure 17A is a plan view schematically showing the configuration of the pixel region 12H-1 according to Modification 7-1 of the second embodiment of the present disclosure. As Figure 17A shown, in the pixel region 12H-1 according to Modification 7-1, compared with the pixel region 12G shown in FIG. 16, some positions of the reset transistor RST and the selection transistor SEL in each repeating unit are replaced with each other. The outer shape of the repeating unit of the arrangement of the pixel transistors is the same as the shape of the pixel region 12G shown in FIG. 16.

[0247] (7-2) Modification 7-2

[0248] Figure 17B is a plan view schematically showing the configuration of the pixel region 12H-2 according to Modification 7-2 of the second embodiment of the present disclosure. As Figure 17BAs shown, in the pixel region 12H-2 according to Modification 7-2, columns are provided in which the reset transistor RST, the amplification transistor AMP, the amplification transistor AMP, and the selection transistor SEL are repeatedly arranged in this order in the Y-axis direction. The outer shape of the repeating unit of the configuration of the pixel transistors is different from that of Figure 17A the shape of the pixel region 12H-1 shown in

[0249] (7-3) Modification 7-3

[0250] Figure 17C FIG. is a plan view schematically showing the configuration of the pixel region 12H-3 according to Modification 7-3 of the second embodiment of the present disclosure. As Figure 17C shown, in the pixel region 12H-3 according to Modification 7-3, the outer shape of the repeating unit of the configuration of the pixel transistors is different from that of Figure 17B the shape of the pixel region 12H-2 shown in

[0251] (7-4) Modification 7-4

[0252] Figure 17D FIG. is a plan view schematically showing the configuration of the pixel region 12H-4 according to Modification 7-4 of the second embodiment of the present disclosure. As Figure 17D shown, in the pixel region 12H-4 according to Modification 7-4, the outer shape of the repeating unit of the configuration of the pixel transistors is different from that of Figure 17A the pixel region 12H-1 shown in Figure 17B the pixel region 12H-2 shown in Figure 17C the pixel region 12H-3 shown in

[0253] (7-5) Modification 7-5

[0254] Figure 17E FIG. is a plan view schematically showing the configuration of the pixel region 12H-5 according to Modification 7-5 of the second embodiment of the present disclosure. As Figure 17E shown, in the pixel region 12H-5 according to Modification 7-5, compared with the pixel region 12H-4 shown in Figure 17D the positions of the selection transistor SEL and the amplification transistor AMP in each repeating unit are replaced with each other. The outer shape of the repeating unit of the configuration of the pixel transistors is the same as the shape of Figure 17D the pixel region 12H-4 shown in

[0255] (7-6) Modification 7-6

[0256] Figure 17F FIG. is a plan view schematically showing the configuration of the pixel region 12H-6 according to Modification 7-6 of the second embodiment of the present disclosure. AsFigure 17F As shown, in pixel region 12H-6 according to Modification Example 7-6, the outer shape of the repeating unit of the pixel transistor configuration is different from that of Figures 17A to 17E the shape of pixel regions 12H-1 to 12H-5 shown.

[0257] (7-7) Modification Example 7-7

[0258] Figure 17G is a plan view schematically showing the configuration of pixel region 12H-7 according to Modification Example 7-7 of the second embodiment of the present disclosure. As Figure 17G shown, in pixel region 12H-7 according to Modification Example 7-7, compared with Figure 17F pixel region 12H-6 shown, some positions of the selection transistor SEL and the amplification transistor AMP in each repeating unit are replaced with each other. The outer shape of the repeating unit of the pixel transistor configuration is different from that of Figure 17F the shape of pixel region 12H-5 shown.

[0259] (7-8) Modification Example 7-8

[0260] Figure 17H is a plan view schematically showing the configuration of pixel region 12H-8 according to Modification Example 7-8 of the second embodiment of the present disclosure. As Figure 17H shown, in pixel region 12H-8 according to Modification Example 7-8, the outer shape of the repeating unit of the pixel transistor configuration is different from that of Figure 17G pixel region 12H-7 shown. As Figure 17H shown, in pixel region 12H-8 according to Modification Example 7-8, the outer shape of the repeating unit of the pixel transistor configuration is different from that of Figures 17A to 17G the shape of pixel regions 12H-1 to 12H-7 shown.

[0261] (7-9) Modification Example 7-9

[0262] Figure 17I is a plan view schematically showing the configuration of pixel region 12H-9 according to Modification Example 7-9 of the second embodiment of the present disclosure. As Figure 17I shown, in pixel region 12H-9 according to Modification Example 7-9, the outer shape of the repeating unit of the pixel transistor configuration is different from that of Figures 17A to 17H the shape of pixel regions 12H-1 to 12H-8 shown.

[0263] (7-10) Modification Example 7-10

[0264] Figure 17JIt is a plan view schematically showing the configuration of the pixel region 12H-10 according to Modifications 7-10 of the second embodiment of the present disclosure. As Figure 17J shown, in the pixel region 12H-10 according to Modifications 7-10, compared with the Figure 17I shown pixel region 12H-9, some positions of the selection transistor SEL and the amplification transistor AMP in each repeating unit are replaced with each other. The outer shape of the repeating unit of the configuration of the pixel transistors is the same as the Figure 17I shown shape of the pixel region 12H-9.

[0265] <Third Embodiment>

[0266] In addition, when the configuration of each shared pixel unit 35 is a 2×4 type configuration, the pixel transistors may have a switching transistor FDG for switching the charge conversion efficiency of the amplification transistor AMP.

[0267] (Configuration Example)

[0268] Figure 18 It is a plan view schematically showing a configuration example of the pixel region 12I according to the third embodiment of the present disclosure. As Figure 18 shown, the configuration of each shared pixel unit 35 in the pixel region 12I is a 2×4 type configuration. Each shared pixel unit 35 has four amplification transistors AMP, two selection transistors SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors.

[0269] As Figure 18 shown, in the pixel region 12I, there are provided a column in which the switching transistor FDG, the selection transistor SEL, the selection transistor SEL, and the reset transistor RST are repeatedly arranged in order in the Y-axis direction and a column in which the amplification transistors AMP are arranged in the Y-axis direction.

[0270] In the pixel region 12I, the gate electrodes of each pair of pixel transistors (each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of reset transistors RST, each pair of switching transistors FDG) adjacent to each other in the X-axis direction are integrated.

[0271] (Effects of the Third Embodiment)

[0272] Similarly, with such a configuration, as in the above-described first embodiment, it is possible to reduce the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ), and it is possible to reduce the degradation of the performance of the imaging device 1.

[0273] Note that, also in the pixel region 12I, some of the total eight pixel transistors included in each shared pixel unit 35 may not be incorporated into the circuit and may be dummy transistors.

[0274] (8) Modification Example 8

[0275] In the third embodiment, the configurations in Modification Examples 8-1 to 8-9 shown below can be adopted. The configuration of each shared pixel unit 35 in Modification Examples 8-1 to 8-9 is a 2×4 type configuration. Each shared pixel unit 35 includes four amplification transistors AMP, two selection transistors SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. Similarly, with such a configuration, as in the above-described first and second embodiments, the parasitic capacitance generated between the vias 62 and between the wirings 61 (for example, refer to Figure 6 ) can be reduced, and the degradation of the performance of the imaging device 1 can be reduced.

[0276] Note that, also in Modification Examples 8-1 to 8-9 shown below, some of the total eight pixel transistors included in each shared pixel unit 35 may not be incorporated into the circuit and may be dummy transistors.

[0277] (8-1) Modification Example 8-1

[0278] Figure 19A is a plan view schematically showing the configuration of the pixel region 12J-1 according to Modification Example 8-1 of the third embodiment of the present disclosure. As Figure 19A shown, in the pixel region 12J-1 according to Modification Example 8-1, columns in which the switching transistor FDG, the reset transistor RST, the selection transistor SEL, and the selection transistor SEL are repeatedly arranged in the Y-axis direction in sequence, and a column in which the amplification transistor AMP is arranged in the Y-axis direction are provided. The outer shape of the repeating unit of the arrangement of the pixel transistors is the same as the shape of the pixel region 12I shown in Figure 18 .

[0279] (8-2) Modification Example 8-2

[0280] Figure 19B is a plan view schematically showing the configuration of the pixel region 12J-2 according to Modification Example 8-2 of the third embodiment of the present disclosure. As Figure 19B shown, in the pixel region 12J-2 according to Modification Example 8-2, columns in which the selection transistor SEL, the reset transistor RST, the amplification transistor AMP, and the amplification transistor AMP are repeatedly arranged in the Y-axis direction in sequence, and columns in which the selection transistor SEL, the switching transistor FDG, the amplification transistor AMP, and the amplification transistor AMP are repeatedly arranged in the Y-axis direction in sequence are provided. The outer shape of the repeating unit of the arrangement of the pixel transistors is the same as the shape of the pixel region 12I shown inFigure 18 The shapes of the pixel regions 12I shown are different shapes.

[0281] (8-3) Variant Example 8-3

[0282] Figure 19C It is a plan view schematically showing the configuration of the pixel region 12J-3 according to Variant Example 8-3 of the third embodiment of the present disclosure. As Figure 19C shown, in the pixel region 12J-3 according to Variant Example 8-3, there are provided columns in which switching transistors FDG, reset transistors RST, amplifying transistors AMP, and amplifying transistors AMP are repeatedly arranged in sequence in the Y-axis direction, and columns in which selection transistors SEL, selection transistors SEL, and amplifying transistors AMP are repeatedly arranged in sequence in the Y-axis direction. The outer shape of the repeating unit of the arrangement of the pixel transistors is the same as the shape of the pixel region 12J-2 shown in Figure 19B It is the same shape.

[0283] (8-4) Variant Example 8-4

[0284] Figure 19D It is a plan view schematically showing the configuration of the pixel region 12J-4 according to Variant Example 8-4 of the third embodiment of the present disclosure. As Figure 19D shown, in the pixel region 12J-4 according to Variant Example 8-4, the outer shape of the repeating unit of the arrangement of the pixel transistors is different from the shape of the pixel region 12J-3 shown in Figure 19C It is a different shape.

[0285] (8-5) Variant Example 8-5

[0286] Figure 19E It is a plan view schematically showing the configuration of the pixel region 12J-5 according to Variant Example 8-5 of the third embodiment of the present disclosure. As Figure 19E shown, in the pixel region 12J-5 according to Variant Example 8-5, compared with the pixel region 12J-4 shown in ​ some positions of the reset transistors RST and the selection transistors SEL in each repeating unit are replaced with each other. The outer shape of the repeating unit of the arrangement of the pixel transistors is the same as the shape of the pixel region 12J-4 shown in ​ It is the same shape.

[0287] (8-6) Variant Example 8-6

[0288] ​ It is a plan view schematically showing the configuration of the pixel region 12J-6 according to Variant Example 8-6 of the third embodiment of the present disclosure. As ​ shown, in the pixel region 12J-6 according to Variant Example 8-6, the outer shape of the repeating unit of the arrangement of the pixel transistors is the same as​ The shape of the pixel region 12J-5 shown is different shapes.

[0289] (8-7) Variation 8-7

[0290] ​ is a plan view schematically showing the configuration of the pixel region 12J-7 according to Variation 8-7 of the third embodiment of the present disclosure. As ​ shown, in the pixel region 12J-7 according to Variation 8-7, compared with ​ the pixel region 12J-6 shown, some positions of the reset transistor RST and the selection transistor SEL in each repeating unit are replaced with each other. In addition, the gate electrodes of the selection transistor SEL and the reset transistor RST adjacent to each other in the X-axis direction and the gate electrodes of the strobe transistor SEL and the switching transistor FDG adjacent to each other in the X-axis direction are not integrated. The gate electrodes of each pair of amplification transistors AMP adjacent to each other in the X-axis direction are integrated.

[0291] The outer shape of the repeating unit of the configuration of the pixel transistors is the same shape as that of the pixel region 12J-6 shown in ​ .

[0292] (8-8) Variation 8-8

[0293] ​ is a plan view schematically showing the configuration of the pixel region 12J-8 according to Variation 8-8 of the third embodiment of the present disclosure. As ​ shown, in the pixel region 12J-8 according to Variation 8-8, the outer shape of the repeating unit of the configuration of the pixel transistors is a different shape from that of the pixel region 12J-7 shown in ​ .

[0294] (8-9) Variation 8-9

[0295] ​ is a plan view schematically showing the configuration of the pixel region 12J-9 according to Variation 8-9 of the third embodiment of the present disclosure. As ​ shown, in the pixel region 12J-9 according to Variation 8-9, compared with ​ the pixel region 12J-8 shown, some positions of the amplification transistor AMP and the selection transistor SEL in each repeating unit are replaced with each other. The outer shape of the repeating unit of the configuration of the pixel transistors is the same shape as that of the pixel region 12J-8 shown in ​ .

[0296] <Fourth Embodiment>

[0297] In an embodiment of the present disclosure, the number of amplification transistors AMP included in each shared pixel unit 35 is not limited to two or four, and may be, for example, equal to or greater than six.

[0298] ​ FIG. is a plan view schematically showing a configuration example of a pixel region 12K according to a fourth embodiment of the present disclosure. As Figure 20 shown, in the pixel region 12K according to the fourth embodiment, the configuration of each shared pixel unit 35 is a 4×2 type configuration, and each shared pixel unit 35 includes six amplification transistors AMP, one selection transistor SEL, and one reset transistor RST as pixel transistors. Similarly, with such a configuration, as in the first to third embodiments described above, it is possible to reduce the parasitic capacitance generated between vias 62 and between wirings 61 (for example, refer to Figure 6 ), and it is possible to reduce the deterioration of the performance of the imaging device 1.

[0299] (9) Modification Example 9

[0300] For example, in the fourth embodiment, the configurations in Modification Examples 9-1 and 9-2 shown below may be adopted. The configuration of each shared pixel unit 35 in Modification Examples 9-1 and 9-2 is a 2×4 type configuration. Each shared pixel unit 35 includes four amplification transistors AMP, two selection transistors SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. Similarly, with such a configuration, as in the first to third embodiments described above, it is possible to reduce the parasitic capacitance generated between vias 62 and between wirings 61 (for example, refer to Figure 6 ), and it is possible to reduce the deterioration of the performance of the imaging device 1.

[0301] (9-1) Modification Example 9-1

[0302] Figure 21A FIG. is a plan view schematically showing the configuration of a pixel region 12L-1 according to Modification Example 9-1 of the fourth embodiment of the present disclosure. As Figure 21A shown, in the pixel region 12L-1 according to Modification Example 9-1, the outer shape of the repeating unit of the pixel transistor arrangement is a shape different from the shape of the Figure 20 shown pixel region 12K.

[0303] (9-2) Modification Example 9-2

[0304] Figure 21B FIG. is a plan view schematically showing the configuration of a pixel region 12L-2 according to Modification Example 9-2 of the fourth embodiment of the present disclosure. As Figure 21B shown, in the pixel region 12L-2 according to Modification Example 9-2, the outer shape of the repeating unit of the pixel transistor arrangement is a shape different from the shape of the Figure 21AThe shape of the pixel region 12L-1 shown is different shapes.

[0305] <Fifth Embodiment>

[0306] Next, a configuration example of the readout circuit 30 applicable to the above-described first to fourth embodiments and their modified examples will be shown.

[0307] (Configuration Example 1)

[0308] Figure 22 It is a circuit diagram showing Configuration Example 1 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figure 22 The Configuration Example 1 of the readout circuit 30 shown in is applicable to the case where the configuration of each shared pixel unit 35 is a 2×2 type configuration and each shared pixel unit 35 has two amplification transistors AMP, one selection transistor SEL, and one reset transistor RST as pixel transistors. For example, Figure 22 The Configuration Example 1 shown in can be applied to the above-described first embodiment, modified examples 1-1 to 1-3, and modified examples 2-1 to 2-4.

[0309] (Configuration Examples 2 and 3)

[0310] Figure 23 and Figure 24 It is a circuit diagram showing Configuration Examples 2 and 3 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figure 23 and Figure 24 The Configuration Examples 2 and 3 of the readout circuit 30 shown in are applicable to the case where the configuration of each shared pixel unit 35 is a 2×2 type configuration and each shared pixel unit 35 has one amplification transistor AMP, one selection transistor SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. For example, Figure 23 and Figure 24 The Configuration Examples 2 and 3 shown in can be applied to the above-described modified examples 3-1 and 3-2.

[0311] (Configuration Examples 4 and 5)

[0312] Figure 25 and Figure 26 It is a circuit diagram showing Configuration Examples 4 and 5 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figure 25 and Figure 26 The Configuration Examples 4 and 5 of the readout circuit 30 shown in are applicable to the case where the configuration of each shared pixel unit 35 is a 4×2 type (or 2×4 type) configuration and each shared pixel unit 35 has four amplification transistors AMP, two selection transistors SEL, and two reset transistors RST as pixel transistors. For example, Figure 25 and Figure 26The configuration examples 4 and 5 shown in the above can be applied to the above-described modification examples 4-1 to 4-6 and 5-1 to 5-3 (or modification examples 7-1 to 7-10).

[0313] (Configuration examples 6 to 9)

[0314] Figures 27 to 30 FIGS. are circuit diagrams showing configuration examples 6 to 9 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figures 27 to 30 The configuration examples 6 to 9 of the readout circuit 30 shown in FIGS. are applicable to the case where the configuration of each shared pixel unit 35 is a 4×2 type configuration and each shared pixel unit 35 has two amplification transistors AMP, two selection transistors SEL, two reset transistors RST, and two switching transistors FDG as pixel transistors. For example, Figures 27 to 30 The configuration examples 6 to 9 shown in FIGS. can be applied to the above-described modification examples 6-1 and 6-2.

[0315] (Configuration examples 10 to 13)

[0316] Figures 31 to 34 FIGS. are circuit diagrams showing configuration examples 10 to 13 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figures 31 to 34 The configuration examples 10 to 13 of the readout circuit 30 shown in FIGS. are applicable to the case where the configuration of each shared pixel unit 35 is a 4×2 type (or 2×4 type) configuration and each shared pixel unit 35 has four amplification transistors AMP, two selection transistors SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. For example, Figures 31 to 34 The configuration examples 10 to 13 shown in FIGS. can be applied to the above-described modification examples 6-3 to 6-6 (or the third embodiment, modification examples 8-1 to 8-9).

[0317] (Configuration example 14)

[0318] Figure 35 FIG. is a circuit diagram showing configuration example 14 of the readout circuit 30 according to the fifth embodiment of the present disclosure. Figure 35 The configuration example 14 of the readout circuit 30 shown in FIGS. is applicable to the case where the configuration of each shared pixel unit 35 is a 4×2 type (or 2×4 type) configuration and each shared pixel unit 35 has six amplification transistors AMP, one selection transistor SEL, one reset transistor RST, and one switching transistor FDG as pixel transistors. For example, Figure 35 The configuration example 14 shown in FIGS. can be applied to the above-described fourth embodiment.

[0319] <Sixth embodiment>

[0320] The pixel transistors (e.g., at least one or more of the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the switching transistor FDG) according to the embodiments of the present disclosure are not limited to pixel transistors having a planar gate structure as shown in Figure 7 . The pixel transistor may be a FinFET (fin field-effect transistor), in which a semiconductor substrate or a semiconductor layer in which a channel is formed is formed in a fin shape. Hereinafter, a case where the amplification transistor AMP, which is an example of the pixel transistor, is a FinFET is shown.

[0321] (Constitution Example 1)

[0322] Figure 36 FIG. is a cross-sectional view of an imaging device 1A according to Constitution Example 1 of the sixth embodiment of the present disclosure. As shown in Figure 36 , in the imaging device 1A according to the sixth embodiment, the first amplification transistor AMP1 and the second amplification transistor AMP2 are FinFETs.

[0323] For example, a fin-shaped semiconductor layer 110 is provided on the front surface 11a of the semiconductor substrate 11. The semiconductor layer 110 is a single-crystalline semiconductor formed on the front surface 11a of the semiconductor substrate 11 by an epitaxial growth method, and is patterned into a fin shape by a photolithography or etching technique. For example, the fin shape is a rectangular parallelepiped shape, which is long in the gate length direction and short in the gate width direction orthogonal to the gate length direction. The upper side of the semiconductor layer 110 is located above the front surface 11a of the semiconductor substrate 11.

[0324] As shown in Figure 36 , gate electrodes G1 and G2 are provided to continuously cover the upper side and the left and right sides of the semiconductor layer 110 with a gate insulating film (not shown) interposed therebetween. According to this configuration, the gate electrodes G1 and G2 can simultaneously apply a gate voltage to the upper side and the left and right sides of the semiconductor layer 110. That is, the gate electrodes G1 and G2 can apply a gate voltage to the semiconductor layer 110 simultaneously from a total of three directions (from the upper side and the left and right sides). Therefore, for example, the gate electrodes G1 and G2 can completely deplete or almost completely deplete the semiconductor layer 110, and can improve the controllability of the channel region. In addition, the gate electrodes G1 and G2 make it possible to increase the gate width of the first amplification transistor AMP1 and the second amplification transistor AMP2 while preventing an increase in area in the plan view.

[0325] In addition, as shown in Figure 36 , also in the imaging device 1A, since the gate electrodes G1 and G2 adjacent to each other in the X-axis direction are integrated, the parasitic capacitance generated between the vias 62 and between the wirings 61 can be reduced, and the deterioration of the performance of the imaging device 1 can be reduced.

[0326] (Configuration Example 2)

[0327] Figure 37 FIG. 4 is a cross-sectional view showing the imaging device 1B according to Configuration Example 2 of the sixth embodiment of the present disclosure. As Figure 37 shown, in the imaging device 1B according to the sixth embodiment, the first amplification transistor AMP1 and the second amplification transistor AMP2 are FinFETs.

[0328] For example, a fin-shaped semiconductor region 111 is provided on the front surface 11a side of the semiconductor substrate 11. The front surface 11a of the semiconductor substrate 11 is patterned into a fin shape by lithography and etching techniques, thereby forming the semiconductor region 111. The height of the upper side of the semiconductor region 111 is the same as or almost the same as the height of the front surface 11a of the semiconductor substrate 11.

[0329] Similarly, in the imaging device 1B, the gate electrodes G1 and G2 can apply a gate voltage to the upper side and the left and right sides of the semiconductor layer 110 simultaneously. That is, the gate electrodes G1 and G2 can apply a gate voltage to the semiconductor layer 110 from a total of three directions (from the upper side and the left and right sides) simultaneously. As a result, an effect similar to that of the imaging device 1A shown in Figure 36 is achieved.

[0330] In addition, as Figure 37 shown, similarly, in the imaging device 1B, since the gate electrodes G1 and G2 adjacent to each other in the X-axis direction are integrated, the parasitic capacitance generated between the vias 62 and between the wirings 61 can be reduced, and the deterioration of the performance of the imaging device 1 can be reduced.

[0331] <Other Embodiments>

[0332] However, as described above, the present disclosure has been described using embodiments and variations, and the statements and drawings forming a part of the present disclosure should not be construed as limiting the present disclosure. Through the present disclosure, those skilled in the art will be clear about various alternative embodiments, examples, and operation techniques. For example, the embodiments of the present disclosure may include Figure 38 or Figure 39 the forms shown in.

[0333] Figure 38 FIG. 5 is a plan view schematically showing the pixel region 12M according to Configuration Example 1 of other embodiments of the present disclosure. As Figure 38 shown, for example, the configuration of each shared pixel unit 35 in the pixel region 12M is a 2×2 type configuration. Two reset transistors RST, two amplification transistors AMP, and two selection transistors SEL are arranged at the center of each shared pixel unit 35. The gate electrodes of each pair of pixel transistors (each pair of reset transistors RST, each pair of amplification transistors AMP, each pair of selection transistors SEL) adjacent to each other in the Y-axis direction are integrated.

[0334] Figure 39 is a plan view schematically showing the pixel region 12N of Configuration Example 2 according to other embodiments of the present disclosure. As Figure 39 shown, the pixel region 12N has a dummy transistor Dum as part of the pixel transistor. For example, the dummy transistor Dum is not connected to other elements and does not output a signal.

[0335] For example, the configuration of each shared pixel unit 35 in the pixel region 12N is a 2×4 type configuration. Two reset transistors RST and two amplification transistors AMP are arranged at the center of each shared pixel unit 35. One selection transistor SEL and one dummy transistor Dum are arranged at one end of each shared pixel unit 35 in the Y-axis direction. One selection transistor SEL and one dummy transistor Dum are arranged at the other end of each shared pixel unit 35 in the Y-axis direction. The gate electrodes of each pair of pixel transistors (each pair of reset transistors RST, each pair of amplification transistors AMP, each pair of selection transistors SEL, each pair of dummy transistors Dum) adjacent to each other in the Y-axis direction are integrated.

[0336] Figure 40 is a plan view schematically showing the pixel region 12P of Configuration Example 3 according to other embodiments of the present disclosure. By replacing the reset transistor RST and the selection transistor SEL in the configuration of the pixel region 12N as Figure 39 shown, the pixel region 12P having the configuration as Figure 40 shown is obtained. Except for this, Figure 40 the configuration of the pixel region 12P as Figure 39 shown is the same as the configuration of the pixel region 12N as

[0337] In Figure 38 the pixel region 12M as Figure 39 shown, Figure 40 the pixel region 12N as

[0338] In Figure 38 the pixel region 12M as Figure 39 shown, Figure 40 the pixel region 12N as

[0339] As described above, needless to say, the present technology includes various embodiments and the like not described herein. Within the scope not departing from the gist of the above-described embodiments and variations, at least one of various types of omissions, substitutions, and changes of the constituent elements can be carried out. In addition, the effects described in this specification are merely illustrative examples, and the effects of the present disclosure are not limited thereto, and other effects may also be possessed.

[0340] Note that the present disclosure may also adopt the following configuration.

[0341] (1) An imaging device, comprising:

[0342] A semiconductor layer;

[0343] A plurality of pixels provided on the semiconductor layer;

[0344] An inter-pixel separation portion provided on the semiconductor layer and separating one pixel adjacent to another pixel among the plurality of pixels; and

[0345] A pixel transistor connected to the plurality of pixels, wherein

[0346] The pixel transistor includes a first transistor and a second transistor adjacent to the first transistor with the inter-pixel separation portion therebetween, and

[0347] The gate electrode of the first transistor and the gate electrode of the second transistor are integrated via the upper portion of the inter-pixel separation portion.

[0348] (2) The imaging device according to the above (1), wherein

[0349] In a plan view observed from the thickness direction of the semiconductor layer, a transistor included in each of the pixel transistors is disposed in each of the plurality of pixels.

[0350] (3) The imaging device according to the above (1) or (2), wherein

[0351] The plurality of pixels form a shared pixel unit that shares the pixel transistor.

[0352] (4) The imaging device according to the above (3), wherein

[0353] As the shared pixel unit, it includes a first shared pixel unit and a second shared pixel unit adjacent to the first shared pixel unit, and

[0354] The gate electrode of the first transistor included in the first shared pixel unit and the gate electrode of the second transistor included in the first shared pixel unit are integrated via the upper portion of the inter-pixel separation portion.

[0355] (5) The imaging device according to (4) above, wherein

[0356] The first transistor included in the first shared pixel unit is disposed at a position overlapping with one of the plurality of pixels included in the first shared pixel unit in a plan view observed from the thickness direction of the semiconductor layer, and

[0357] The second transistor included in the first shared pixel unit is disposed at a position overlapping with one of the plurality of pixels included in the second shared pixel unit in a plan view.

[0358] (6) The imaging device according to (4) or (5) above, wherein

[0359] The integrated gate electrode of the first transistor and the second transistor in the first shared pixel unit is used as the first gate electrode, and the integrated gate electrode of the first transistor and the second transistor in the second shared pixel unit is used as the second gate electrode,

[0360] The first gate electrode and the second gate electrode are adjacent to each other with the pixel isolation portion therebetween.

[0361] The first shared pixel unit has a first via hole provided on the first gate electrode and connected to the first gate electrode,

[0362] The second shared pixel unit has a second via hole provided on the second gate electrode and connected to the second gate electrode, and

[0363] The direction of the shortest distance between the first via hole and the second via hole intersects the direction of the shortest distance between the first gate electrode and the second gate electrode.

[0364] (7) The imaging device according to any one of (1) to (6) above, wherein

[0365] Each of the plurality of pixels has

[0366] A photoelectric conversion portion,

[0367] A floating diffusion portion, and

[0368] A transfer transistor that transfers the charge generated by the photoelectric conversion portion to the floating diffusion portion, and

[0369] The first transistor and the second transistor are amplification transistors that amplify a signal at a level corresponding to the charge accumulated in the floating diffusion portion.

[0370] (8) The imaging device according to any one of (1) to (7) above, wherein

[0371] The pixel isolation portion includes trench isolation.

[0372] (9) The imaging device according to any one of (1) to (8) above, wherein

[0373] the first transistor and the second transistor are FinFETs.

[0374] [List of reference numerals]

[0375] 1, 1A, 1B: Imaging device

[0376] 11: Semiconductor substrate

[0377] 11a: Front surface

[0378] 11b: Back surface

[0379] 12, 12A-1 to 12A-3, 12B-1 to 12B4, pixel region, 12C-1, 12C-2, 12D-1 to 12D-6, 12E-1 to 12E-3, 12F-1 to 12F-6, 12G, 12H-1 to 12H-9, 12I, 12J-1 to 12J-9, 12K, 12L-1 to 12L-3, 12M, 12N, 12P: Pixel region

[0380] 13: Vertical drive circuit

[0381] 14: Column signal processing circuit

[0382] 15: Horizontal drive circuit

[0383] 16: Output circuit

[0384] 17: Control circuit

[0385] 21: Pixel (first pixel, second pixel, third pixel, fourth pixel)

[0386] 22: Horizontal signal line

[0387] 23: Vertical signal line

[0388] 24: Data output signal line

[0389] 30: Readout circuit

[0390] 35: Shared pixel unit

[0391] 35-1: First shared pixel unit

[0392] 35-2: Second shared pixel unit

[0393] 35-3: Third shared pixel unit

[0394] 51: Pixel separation section

[0395] 52: Well region

[0396] 53: Channel portion

[0397] 55: Interlayer dielectric film

[0398] 61, 63: Wiring

[0399] 62: Via

[0400] 62-1: First via

[0401] 62-2: Second via

[0402] 110: Semiconductor layer

[0403] 111: Semiconductor region

[0404] 511: First trench isolation

[0405] 512: Second trench isolation

[0406] AA: Active region

[0407] AMP: Amplifying transistor

[0408] AMP1: First amplifying transistor

[0409] AMP2: Second amplifying transistor

[0410] Dum:Dummy transistor

[0411] FD: Floating diffusion portion

[0412] FDG: Switching transistor

[0413] G1, G2: Gate electrode

[0414] Le: Shortest distance

[0415] Lv: Shortest distance

[0416] PD: Photodiode

[0417] RST: Reset transistor

[0418] SEL: Selection transistor

[0419] TR: Transfer transistor

[0420] TRG: Gate electrode (of transfer transistor)

[0421] VDD: Power supply potential

Claims

1. An imaging device, comprising: a semiconductor layer; a plurality of pixels disposed on the semiconductor layer; an inter-pixel separation portion disposed on the semiconductor layer and separating one pixel adjacent to another pixel among the plurality of pixels; and a pixel transistor connected to the plurality of pixels, wherein the pixel transistor includes a first transistor and a second transistor adjacent to the first transistor across the inter-pixel separation portion, and a gate electrode of the first transistor and a gate electrode of the second transistor are integrated via an upper portion of the inter-pixel separation portion.

2. The imaging device according to claim 1, wherein in a plan view observed from the thickness direction of the semiconductor layer, one transistor included in each of the pixel transistors is disposed in each of the plurality of pixels.

3. The imaging device according to claim 1, wherein the plurality of pixels form a shared pixel unit sharing the pixel transistor.

4. The imaging device according to claim 3, wherein as the shared pixel unit, it includes a first shared pixel unit and a second shared pixel unit adjacent to the first shared pixel unit, and a gate electrode of the first transistor included in the first shared pixel unit and a gate electrode of the second transistor included in the first shared pixel unit are integrated via an upper portion of the inter-pixel separation portion.

5. The imaging device according to claim 4, wherein the first transistor included in the first shared pixel unit is disposed at a position overlapping with one pixel among the plurality of pixels included in the first shared pixel unit in a plan view observed from the thickness direction of the semiconductor layer, and the second transistor included in the first shared pixel unit is disposed at a position overlapping with one pixel among the plurality of pixels included in the second shared pixel unit in the plan view.

6. The imaging device according to claim 4, wherein the integrated gate electrode of the first transistor and the second transistor in the first shared pixel unit is used as a first gate electrode, and the integrated gate electrode of the first transistor and the second transistor in the second shared pixel unit is used as a second gate electrode, the first gate electrode and the second gate electrode are adjacent to each other across the pixel separation portion, the first shared pixel unit has a first via hole disposed on the first gate electrode and connected to the first gate electrode, the second shared pixel unit has a second via hole disposed on the second gate electrode and connected to the second gate electrode, and the direction of the shortest distance between the first via hole and the second via hole intersects with the direction of the shortest distance between the first gate electrode and the second gate electrode.

7. The imaging device according to claim 1, wherein each of the plurality of pixels has a photoelectric conversion portion, a floating diffusion portion, and a transfer transistor that transfers charges generated by the photoelectric conversion portion to the floating diffusion portion, and the first transistor and the second transistor are amplification transistors that amplify a signal at a level corresponding to the charges accumulated in the floating diffusion portion.

8. The imaging device according to claim 1, wherein the inter-pixel separation portion includes trench isolation.

9. The imaging device according to claim 1, wherein the first transistor and the second transistor are FinFETs.

Images